linaro-toolchain

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6 participants
5578 discussions

[Activity] 04 May 2015 -- 08 May 2015

by Yao Qi

* UK bank holiday on Monday [2/10] # Progress # * arm/aarch64 gdb bug fixing [1/10]. ** TCWG-765 fails in gdb.base/coredump-filter.exp. Patch is pushed it in. ** TCWG-767, patch is pushed it in. * TCWG-805, aarch64 native debugging multi-arch support. [2/10]. Let arm use newer ptrace PTRACE_GETREGSET in order to align with aarch64. Ongoing. * Think about debugging programs on different exception levels (EL3, EL2 and EL1). Read doc about EL in aarch64. Looks they need multi-inferior debugging. Request more details. [2/10] * Misc [3/10] ** Book travel and get travel insurance. It is my first travel in ARM, familiarise myself with the travel process. ** Visa application. # Plan # * TCWG-805, aarch64 native debugging multi-arch support. * Other things needed for visa application. -- Yao

10 years

writing a new Machine Description file (e.g cortex-a57.md) in gcc

by Virendra Kumar Pathak

Hi Linaro Toolchain Group, I am new to gcc development. I am trying to write a new md file describing pipeline information for a processor. Please suggest some good reference document for understanding machine description file. Few questions from cortex-a53.md file: For first integer pipeline following is defined - (define_cpu_unit "cortex_a53_slot0" "cortex_a53") Is name cortex_a53_slot0 is a keyword or it is any general string? Is there any convention in choosing names for cpu units? If ‘cortex_a53_slot0’ a general string, how assembler knows it is first integer pipeline? How these *.md files are used? When they are compiled and how they are used? How to verify an md file for a processor is written correctly or not? How to test it? What other design consideration must be kept in mind while writing a new md file? Thanks. with regards, Virendra Kumar Pathak

10 years

[ANNOUNCE] Linaro GCC 4.9 2015.04 snapshot re-spin

by Yvan Roux

This is a re-spin of the Linaro GCC 4.9 2015.04 source package snapshot. The re-spin of this snapshot includes a new configure-time option to enable by default a workaround for Cortex-A53 erratum number 843419 and options to explicitly disable or enable it during compilation. This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.04-1 Original release notes for GCC 4.9 2015.04 snapshot: The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.04 snapshot of the Linaro GCC 4.9 source package. Linaro GCC 4.9 2015.04 is the first Linaro GCC source package snapshot in the 4.9 series. It is based on FSF GCC 4.9.3-pre+svn222035 and includes performance improvements and bug fixes. With the imminent release of ARMv8 hardware and the recent release of the GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides stable[1] quarterly releases and monthly snapshots[2]. Interesting changes in this GCC source package snapshot include: * Linaro bugzilla PR fixed: #415, #1382, #1391 * Updates to GCC 4.9.3-pre+svn222035 * Backport of instruction scheduler improvements * Backport of [AArch64,Neon] Add patterns + builtins for vld[234](q?)_lane_* intrinsics * Backport of [AArch64] Implement fusion adrp+add/movk+movk * Backport of [AArch32] Cortex-A17 support * Backport of [AArch64] Fix __builtin_aarch64_absdi, must not fold to ABS_EXPR * Backport of PR rtl-optimization/63917 * Backport of PR tree-optimization/62178 tree-ssa-loop-ivopts * Backport of [AArch64] Add TARGET_MIN_DIVISIONS_FOR_RECIP_MUL * Backport of [AArch64] Simplify patterns for sshr_n_[us]64 intrinsic * Backport of [AArch64] Simplify+improve patterns for ushr(d?)_n_u64 intrinsic * Backport of [AArch32] Fix reservation pattern in cortex-a9-neon.md * Backport of [AArch64] Don't disparage add/sub in SIMD registers * Backport of [AArch64] Add SIMD-reg variants of logical operators and/ior/xor/not * Backport of [AArch64] Fix XOR_one_cmpl pattern; add SIMD-reg variants for BIC,ORN,EON * Backport of [AArch32] Use Cortex-A17 tuning parameters for Cortex-A12 * Backport of [AArch32] Make CLZ_DEFINED_VALUE_AT_ZERO and CTZ_DEFINED_VALUE_AT_ZERO return 2. * Backport of [AArch32] Minor optimization on thumb2 tail call * Backport of [AArch64] Update APM/XGene-1 * Backport of [AArch64] Add a new scheduling description for the ARM Cortex-A57 processor * Backport of [AArch64] Fix PR 64263: Do not try to split constants when destination is SIMD reg * Backport of [AArch64] Add support for -mcpu=cortex-a72 This snapshot tarball is available on: http://snapshots.linaro.org/components/toolchain/gcc-linaro/4.9-2015.04 Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in bugzilla against GCC product: http://bugs.linaro.org/enter_bug.cgi?product=GCC * Interested in commercial support? inquire at "Linaro support": mailto:support@linaro.org [1] Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2] Source package snapshots are defined when the compiler is only put through unit-testing and full validation is not performed.

10 years

502 connecting to abe.tcwglab.linaro.org

by Christopher Covington

Hi, We've had trouble using ABE recently. abe$ ./abe.sh --target aarch64-linux-gnu NOTE: Downloading md5sums to abe/snapshots RUN: /usr/bin/wget --timeout=10 --tries=2 --directory-prefix=abe/snapshots/ http://abe.tcwglab.linaro.org/snapshots/md5sums --2015-04-21 16:02:33-- http://abe.tcwglab.linaro.org/snapshots/md5sums Resolving abe.tcwglab.linaro.org (abe.tcwglab.linaro.org)... 81.128.185.43 Connecting to abe.tcwglab.linaro.org (abe.tcwglab.linaro.org)|81.128.185.43|:80... connected. HTTP request sent, awaiting response... 502 cannotconnect 2015-04-21 16:02:42 ERROR 502: cannotconnect. Thanks, Chris -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project

10 years

[ACTIVITY] 27 April - 1 May 2015

by Omair Javaid

== Progress == LLDB development -- Wrote hardware breakpoint handlers for NativeLinuxRegisterContext ARM [2/10] [TCWG-770] -- Debugging for issues and code cleanup AArch64 LLDB watchpoint support [2/10] [TCWG-771] -- Fix, test, debug, cleanup and patch re-submission. [1/10] -- Resubmitted, update and commited ARM SysV ABI implementation. [TCWG-643] -- Resubmitted, update and commit AArch64 SysV ABI implementation. [TCWG-715] -- Setting up android test environment [TCWG-651] GDB development [1/10] [TCWG-677] -- Clean-up arm-linux record replay test cases Miscellaneous [2/10] -- Meetings, emails, discussions etc. -- Toolchain Sprint travel bookings and visa application preparation. Public Holiday [2/10] -- Friday 1st May 2015 (Labor Day) == Plan == LLDB development -- Complete work on AArch64 watchpoints and hardware breakpoints -- Hopefully submit ARM watchpoint work may be later in the week. -- Figure out android development Miscellaneous -- Complete and submit France visa application GDB development -- Gather ARM/AArch64 record-replay testsuite work and submit patches for yao.

10 years

[ACTIVITY] April 27th-May 1st

by Christophe Lyon

* Short week: Friday public holiday == Progress == * Linaro-GCC 4.8-2015.04 - prepared fsf-4.8 branch merge - some problems with validation infra * GCC trunk - Committed cleanup patch for Neon intrinsics tests * Validation - learnt how to create jobs for ci.linaro.org * Misc - meetings, conf-calls, emails, ... == Next == * Linaro-GCC-4.8-2015.04 * Submit remaining Neon intrinsics tests * Validation

10 years

[ACTIVITY] Week 18

by Yvan Roux

Friday off (Labor Day) == Issue == * none == Progress == o Upstream GCC (6/8) * [TCWG-785] ARM backend insn cleanup - Addressed comments after submission - Committed at rev 22528 * [TCWG-762] - GCC Maintenance - PR64208 (iWMMXT LRA bug): Updated submission thread after validation ended. - PR65924 (ICE on arm-none-eabi): Fixed and committed at rev. 22572 o 2015.01 and 2015.04 re-spin (_/_) * Prepared GCC patch that adds flags for Cortex-a53 erratum #843419 * Tagged and re-spun 2014.01 with the erratum fix * Start 2015.04 re-spin o Misc (2/10) * Various meetings * Continue GCC git repository branches cleanup == Plan == - Finish 2015.04 re-spin - Continue upstream pending work

10 years

[Weekly] 27 APR-01 MAY 2015

by Michael Collison

* Absence (illness) (9/10) * Misc (1/10) - Conference calls == Next week == - Unsure due to computer related injury

10 years

27 April -- 01 May 2015

by Kugan

- Public holiday (2/10) == Progress == * Upstream GCC (3/10) - TCWG-796 Zero/sign extension elimination with vrp. - TCWG-555 posted patch for compiler pass to widen computation to back-end promoted mode * IRA (4/10) - Looked at https://bugs.linaro.org/show_bug.cgi?id=540 (TCWG-773 Median of three has unneeded register moves) * Misc (1/10) - gcc-patches, gcc-bugs list - Meetings == Plan == - Continue with gcc stage1 activities - Look at register allocation

10 years

[ACTIVITY] Week 18

by Prathamesh Kulkarni

== This week == * TCWG-619 (8/10) PR65858 - workaround: add explicit casts in the file cld_generated_cjk_uni_prop_80.cc - created reduced test case: http://pastebin.com/WJvKRjn2 - commit r222249 introduced the issue - patch submitted upstream: https://gcc.gnu.org/ml/gcc-patches/2015-04/msg02063.html - Paolo Carlini pointed out it doesn't work with -w option, instead of testing on warn_narrowing flag, he modified it to check on pedwarn()'s return value, which covers up for both -Wno-narrowing and -w, and committed with this modification (r222700). PR65837 - patch to lto-wrapper rejected. - Another hack to pass driver's argv to lto-wrapper via another environment variable COLLECT_GCC_OPTIONS_DRIVER rejected by Richard. - Ramana and Richard pointed out the proper fix would be to handle target attributes in ARM backend. - I could try extending Christian Bruel's target attribute patches for fpu options after they're checked in which would then fix the PR. chromium LTO build - Many instances of same error message during LINK chrome: chrome.ltrans0.s:18399164: Error: Thumb2 branch out of range chrome.ltrans0.s:9671243: Error: branch out of range works fine for non-lto. A similar issue, occurred for v8 LTO build - PR65778, but it was marked resolved invalid. - chromium builds with LTO for chrome component. - ld.bfd segfault while building chromium with LTO not reproducible with master. - non-LTO build undefined reference to libattr1 functions not reproducible with ld.bfd master. This probably was sysroot/libc issue than issue with ld.bfd. * PR49551 (2/10) - reverting r221297 reproduces the ICE - tried to fix with following patch: http://pastebin.com/knuWeY0C - fixes the ICE but following regressions observed on arm-linux-gnueabihf: http://pastebin.com/E1zLtq8s == Issues == - Can't login to cards.linaro.org (was able to before). I get error - "You do not have permission to login". == Next Week == - Investigate testsuite failures for PR49551 - Selectively enable LTO on components in chromium. - exams preparation

10 years

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