linaro-toolchain

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[ACTIVITY] 13-17 July

by Charles Baylis

Holiday [4/10] Benchmarking [3/10] TCWG-867 - AArch64 post-idx addressing [2/10] . prototype patch Misc [1/10]

10 years, 1 month

[ACTIVITY] 27th - 31st July

by Bernie Ogden

Benchmark infrastructure - TCWG-360 [8/10] * Testing found many problems in multinode * Iterating to solutions Misc [2/10] =Plan= Holiday next week. Then back to fixing multinode, incorporating into jenkins, noise control experiments

10 years, 1 month

[ACTIVITY] 27th - 31th July

by Yao Qi

# Progress # * TCWG-806, aarch64 remote debugging multi-arch support. [4/10] Patches are posted upstream. * TCWG-860, aarch64 fast tracepoint. [1/10] Patch review and some discussions. * TCWG-757, upstream patch review. [2/10]. ** Review NIOS II R2 patches. ** Fix PR record/18691. * Misc, meeting. [3/10] # Plan # * TCWG-857, Investigate multi-arch HW watchpoint support in GDB and linux kernel. Clean up aarch64 HW watchpoint code. * GNU Tools Cauldron. -- Yao

10 years, 1 month

ABE - bug in copy_gcc_libs_to_sysroot() while building native toolchain for aarch64

by Virendra Kumar Pathak

Hi Linaro Toolchain Group, I am building a native toolchain for aarch64 with below configurations: --build=x86_64-unknown-linux-gnu --host=aarch64-linux-gnu --target=aarch64-linux-gnu. In copy_gcc_libs_to_sysroot() - which copy libgcc.a to sysroot, current implementation try to find the absolute path of libgcc.a as below : libgcc="`${local_builds}/destdir/${host}/bin/${target}-gcc -print-file-name=${libgcc}` But above line will not execute (i.e. gcc -print-file-name) on x86_64 as the toolchain is native toolchain for aarch64-linux-gnu. Thus a infinite loop will be created in copy command i.e. copying directory x in x. however, when I hard coded the libgcc.a path in my machine (as below), everything went fine. libgcc="/home/vpathak/arm/toolchain/build_abe_new/builds/destdir/aarch64-linux-gnu/lib/gcc/aarch64-linux-gnu/5.1.1/libgcc.a" I think this is a bug in ABE build infrastructure. Thanks. -- with regards, Virendra Kumar Pathak

10 years, 1 month

RE: [ACTIVITY] 20th - 24th July

by duane＠duaneellis.com

* TCWG-806, aarch64 remote debugging multi-arch support. [4/10] Patches are done. Need to test them and polish them. Fix various multi-arch issues when --wrapper is used in GDBserver. Patches are pushed in to mainline. Could you describe this activity in more detail? Is the goal here to support mixed aarch32/aarch64 in the same GDB binary and detect the change at runtime? Thanks. -Duane

10 years, 1 month

[ACTIVITY] 20th - 24th July

by Kugan

== Progress == * Factor conversion out of COND_EXPR - TCWG-849 (5/10) - Iterated through the review and more testing * Looked at widening pass and the test-case from Wilco (1/10) * Misc (2/10) - Connect slides. - gcc-patches, gcc-bugs list - Meetings * Sick (2/10) == Plan == - GCC Bugs - Widening pass - Linaro bug 1318

10 years, 1 month

[Weekly] 20-24 JULY 2015

by Michael Collison

== This week == * TCWG-146 - Detect smin/umin idiom (1/10) - Made change recommended upstream and resubmitted * TCWG-140 - Transform end of loop conditions to min_expr (1/10) - Validated and submitted upstream * TCWG-833 - Exploit Wide Add operations when appropriate (5/10) - Added early clobber and forced operand 0 and operand 2 to match - Finished Aarch32 by using mode iterators - Developed patch for Aarch64 - Wide add instructions are now emitted for both Aarch32 and Aarch64 * TCWG-834 - Use non-unit stride loads by preference when applicable (2/10) - Further Aarch32 investigation * Misc (1/10) - Conference calls == Next week == - Validate patches for TCWG-833 and submit upstream - Further TCWG-834 investigation - Linaro connect presentation preparation

10 years, 1 month

[activity] 20 - 24 July 2015

by Prathamesh Kulkarni

* TCWG-835 (6/10) - Looked at newton raphson method - Need to write new md pattern that matches sdiv_optab for modes == v2sf, v4sf - First attempt for patch: http://pastebin.com/NKy8WdWC * TCWG-830 (2/10) - Ran Charles's benchmarks on ARM and AArch64. - Investigating testsuite fallout for ARM patch. - Still blocked by permissions to do benchmarking * Misc (2/10) - Conference Calls - US visa collection == Next Week == - Continue with TCWG-830, TCWG-835, TCWG-777

10 years, 1 month

binutils - question on decoding decision tree for aarch64

by Virendra Kumar Pathak

Hi Linaro Toolchain Group, I am trying to learn the 'decoding decision tree' for aarch64 in binutils by trying to add a new assembly instruction 'addvp'. For example: addvp x0, x0, 9 For this, I added a entry in struct aarch64_opcode aarch64_opcode_table[] (file opcodes/aarch64-tbl.h) as below: {"addvp", 0x01000000, 0x7f000000, addsub_imm, 0, CORE, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF}, ARM manual say, bit 27 & bit 28 are unallocated. Thus for addvp, I am giving opcode 01000000 (with bit 27 & 28 as 0). With this, generating object file from assembly file is successful (test.s --> test.o); but while disassembling using objdump, it say undefined instruction. >From objdump log: 81002400 .inst 0x81002400 ; undefined (but instruction was generated correct i.e. 81002400 !!!). I know since addvp is a hack instruction, it won't execute on cpu. But still disassembly should succeed. 1. Please help me in knowing what I am doing wrong here ? What else I should do to add a new instruction in binutils ? 2. I also saw some printf in opcodes/aarch64-gen.c which I guess create decoding tree (initialize_decoder_tree()). How to print them ? I made debug =1 but still print is not coming. 3. There are some auto-generated files like aarch64-asm-2.c, aarch64-dis-2.c. How to re-generate them ? Thanks. -- with regards, Virendra Kumar Pathak

10 years, 1 month

[ACTIVITY]

by Renato Golin

== Progress == * Maintenance (CARD-1833 5/10) - Building libc++/abi/unwind in LLVM/Clang tree - Fixing some build errors (D11486) - Addressing comments to submissions from last week - Committing approved ones - Re-working the others * Releases (CARD-1431 1/10) - Building 3.7.0-RC1 on ARM and AArch64, uploading * Benchmarks (CARD-716 2/10) - Running LNT, SPEC and EEMBC on ARM and AArch64 for 3.7.0 * Background (2/10) - Code review, meetings, discussions, etc. - Upgraded APM to Debian, kernel 3.16 - Perf still segfaults. :( == Plan == * Finish open reviews * Continue getting libc++ to build and pass the tests in tree * Look at some of the performance regressions in 3.7

10 years, 1 month

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