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[ACTIVITY] Weekly report for week 37 to 39

by Thomas Preudhomme

=== Work done during these past 3 weeks === * DSGHACK-25 (Support arithmetic on FileCheck regex variable): + all my tests pass, started to implement further minor changes to the syntax * PR87374: external review + investigate bug, write patch, test it and send for external review * GCC PR85434 / CVE-2018-12886: rework needed + Approved upstream but found when doing last minute testing after rebase + Testing on a wide number of targets a patch to register allocator to properly ignore some operand when told to * Linaro Connect Vancouver 2018 + prepare talk, attend event and write up reports * Regression testing of LLVM release: + extend script to do a LLVM release to be able to build from an arbitrary branch + make weekly regression build from trunk + fix here-doc in regression job to test release when scripts it use change Misc: + bits of line management + catching up on emails === Plan for week 40 === * GCC PR85434 / CVE-2018-12886: + finish testing, and get both register allocator fix and stack protector fix committed * PR87374: external review + add documentation and send back for external review * DSGHACK-25 (Support arithmetic on FileCheck regex variable): + finish change to suport last syntax changes + extend testcase coverage (add tests for latest syntax change and add more negative testing) + start cleaning up the code * Try to reproduce perf issue mentioned in week #30's weekly report on latest perf * Line management

7 years, 1 month

[ACTIVITY] report week ending 28 Sep

by Peter Maydell

Progress: * Post-travel/holiday catchup (email, expenses claims, code review, team meetings etc) (this was the lion's share of the time) * VIRT-65 [QEMU upstream maintainership] - some patches to fix clang warnings about taking the address of a field in a packed struct - make the compatibility "virt-2.10" machine really behave like the 2.10 QEMU's virt board: don't generate external aborts for accesses to bad physical addresses. (It turns out a few misconfigured Linux kernels do this.) - noticed that we only have another 40 or so devices to convert to be able to complete an API transition (sysbus init methods): wrote this up for the list to nudge people into doing some conversions thanks -- PMM

7 years, 1 month

[ACTIVITY] report week ending 21 Sep

by Peter Maydell

Progress: This week was Linaro Connect (Vancouver). Recordings are online for most sessions I think; some may still be in the process of being uploaded. For other presentations see: https://connect.linaro.org/resources/yvr18/ Interesting presentations: * "My other Machine is Virtual" -- Alex's talk summarising QEMU's current tracing/debug facilities: https://connect.linaro.org/resources/yvr18/yvr18-118/ * "SBSA QEMU" -- Summary of work on an "enterprise" model in QEMU intended for use as a development platform for firmware and other lower-level code. https://connect.linaro.org/resources/yvr18/yvr18-511/ * "How to build a C++ processing tool using the clang libraries" -- Peter Smith doing a fast pass through the clang library APIs you can use for refactoring-type tools that operate on C++ source. Watch the talk to figure out if this is something you want to do at all; read the slides separately for the fine detail and links to where to find more info, if the answer is "yes"... https://connect.linaro.org/resources/yvr18/yvr18-223/ * "Diary of a drive-by coder: tips and tricks for working with upstream" -- James Bottomley talks about successes and failures in upstreaming one-off patches if you're not a member of the community. I also asked in the Q&A about what communities can do to make life easier for such contributors (answer mostly revolved around better and clearer communication about the chances of a change being accepted) https://connect.linaro.org/resources/yvr18/yvr18-503/ * "An open source developer and a lawyer walk into a bar..." -- Jilayne Lovejoy's keynote (Personal takeaway: try to reduce my use of "IANAL, but...".) https://connect.linaro.org/resources/yvr18/yvr18-200k2/ * Fujitsu's keynote on their new A64FX CPU: https://connect.linaro.org/resources/yvr18/yvr18-400k1/ * Arm Architecture Enhancements in 2018 Matt Gretton-Dann's presentation of ARM v8A 8.5 features. I was particularly encouraged to see that Arm have been able to make public the system register and ISA XML on the same day they announce the new features publicly. https://connect.linaro.org/resources/yvr18/yvr18-104/ Useful meetings: * discussion with RTH about handling CPU ID register fields vs internal QEMU "enable this feature" bits (we have a bit of an ugly mix of specifying the same thing in both places, and also overriding ID reg fields from feature bits in some cases; we'd like to achieve a bit more consistency in what we do...) * discussion with RTH/Alex on instrumentation plugin APIs. I hope we're now more or less on the same page about the general principles. * QEMU roadmap sync with Alex/RTH/Maxim: - finish v8M work - heterogenous CPU support (for Musca board emulation) - finish SVE - fill in other v8.x missing emulation support - instrumentation work Other: * Greensocs have sent out some QEMU patches to do with modelling clock trees, which also touch a bit on reset. QEMU's modelling of reset at the moment is pretty terrible, so I had a think about how we might manage to do it better. (Notably we currently only model power-on reset, and we don't have a good answer for "device A in reset wants to assert a signal that connects to device B, but there's no guarantee about what order A and B will reset in". Does anybody know of any good existing treatments of modelling device reset ?) thanks -- PMM

7 years, 1 month

[ACTIVITY] Week 38

by Yvan Roux

o LLVM * Machine Outliner on ARM prototype: - Rebased on trunk - Thumb support on-going * Bots babysitting o Misc * Various meetings and discussions.

7 years, 1 month

[ANNOUNCE] Arm Binary A-profile Toolchain Release GCC 8.2-2018.08

by Przemyslaw Wirkus

The Arm GNU Toolchain for the A-profile Architecture ===================================================== The Arm GNU Toolchain for the A-profile Architecture 8.2-2018.08 Release is now available. Arm is pleased to announce the first Arm-built release of the pre-built GNU cross-toolchain for the A-profile cores: GCC 8.2-2018.08. This is the same toolchain that was previously built and distributed by Linaro. For the official announcement, see: https://community.arm.com/tools/b/blog/posts/pre-built-gnu8-cross-toolchain… For more information about the GNU Arm toolchain and to download the release packages, see the Arm Developer website at: https://developer.arm.com/open-source/gnu-toolchain/gnu-a For an explanation of FSF GCC 8 series changes see: https://gcc.gnu.org/gcc-8/changes.html For help in porting to GCC 8 see the following explanation: https://gcc.gnu.org/gcc-8/porting_to.html Download the release packages from: (sources) https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads (binaries) https://developer.arm.com/open-source/gnu-toolchain/gnu-a/downloads Previous snapshots and release-candidates for GCC 7 and earlier are at: (sources) https://releases.linaro.org/components/toolchain/gcc-linaro/ (binaries) http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases for GCC 7 and earlier are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the Arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== * Ubuntu 14.04 LTS x86_64 or later or RHEL 6.9 x86_64: * x86_64 hosted cross compiler for AArch64 ELF bare-metal target (x86_64-aarch64-elf). * x86_64 hosted cross compiler for AArch64 ELF bare-metal, big-endian target (x86_64-aarch64_be-elf). * x86_64 hosted cross compiler for AArch64 GNU/Linux target (x86_64-aarch64-linux-gnu). * x86_64 hosted cross compiler for AArch64 GNU/Linux big-endian target (x86_64-aarch64_be-linux-gnu). * x86_64 hosted cross compiler for AArch32 bare-metal target (x86_64-arm-eabi). * x86_64 hosted cross compiler for AArch32 target with soft float (x86_64-arm-linux-gnueabi). * x86_64 hosted cross compiler for AArch32 target with hard float (x86_64-arm-linux-gnueabihf). * Windows 7 or later, for 32 and 64 bit OS: * i686-mingw32 hosted cross compiler for AArch32 bare-metal target (i686-mingw32-arm-eabi). * i686-mingw32 hosted cross compiler for AArch64 ELF bare-metal target (i686-mingw32-aarch64-elf). Package Versions ================= GCC 8.2.1 https://gcc.gnu.org/gcc-8/changes.html FSF glibc 2.28 http://lists.gnu.org/archive/html/info-gnu/2018-08/msg00000.html Newlib 3.0.0 https://sourceware.org/ml/newlib/2018/msg00019.html GNU Binutils 2.30 https://lists.gnu.org/archive/html/info-gnu/2018-01/msg00010.html FSF GDB 8.1.1 https://www.gnu.org/software/gdb/download/ANNOUNCEMENT libiconv 1.15 https://savannah.gnu.org/forum/forum.php?forum_id=8790 libexpat 2.2.5 https://github.com/libexpat/libexpat/blob/R_2_2_5/expat/Changes libgmp 4.3.2 libisl 0.15 libmpfr 3.1.6 libmpc 0.8.2 Sources provided in release source tar ball. News for GCC 8 (as of GCC 8.2-2018.08) ======================================= * All GCC 8.2 features. For details on GCC 8 release series, please refer to the list of changes, new features, and fixes. * Linaro specific pre-processor macros to ensure that this is a continuation from the Linaro releases. * Spectre v1 mitigation backport from upstream FSF trunk include the revisions listed below. This is an initial backport of those mitigations in the GNU toolchain and should be regarded as support for prototyping and early access only. Moreover, while the backports include support for the other architectures, they are included for completeness and all issues regarding these patches must be taken up upstream in the https://gcc.gnu.org/bugzilla by reproducing the same with upstream FSF trunk. Arm is interested in feedback regarding these workarounds for Spectre v1. A description of the mitigation has been published on LWN.net. For more details about Spectre V1 defense in GCC visit: https://lwn.net/Articles/759423/ Contact Arm ============ For any questions, please use the Arm Communities forums at: https://community.arm.com/tools/ Please report any bugs via the Linaro Bugzilla at: https://bugs.linaro.org/

7 years, 1 month

[ACTIVITY] Week 37

by Yvan Roux

o LLVM * Buildbots babysitting: - Investigating armv7 bots failures, having hard time to reproduce the issue * Machine Outliner on ARM prototype: - worked on LTO integration - more stack fixups to handle o Misc * Various meetings and discussions.

7 years, 1 month

[ACTIVITY] week ending Sep. 16 2018

by Alex Bennée

QEMU Tooling ([VIRT-252]) ========================= - thoughts after reviewing {Qemu-devel} {RFC PATCH v2 0/7} QEMU binary instrumentation prototype Message-Id: <152819515565.30857.16834004920507717324.stgit@pasha-ThinkPad-T60> - we want rich tooling but don't want to leak internals to plugins - the proposed helper per insn is pretty limited/hacky - I think we could expand exiting trace support with plugins - plugin hook to trace points - plugin either filters trace points or does in-situ analysis - existing trace infrastructure used to export data [VIRT-252] https://projects.linaro.org/browse/VIRT-252 Upstream Work ([VIRT-109]) ========================== - investigating CI failure in master: - The [Travis builds have been broken for a while] - meanwhile it looks like [atomic_8 issues have broken 32 bit builds] - reviewed {PATCH 0/6} i386 + x86_64 mttcg Message-Id: <20180903171831.15446-1-cota(a)braap.org> - posted {RFC PATCH 0/4} Add Nios II cross-compiler and enable tests/tcg Message-Id: <8346c1bb-9cb6-4c08-66a2-b5e5a31903d4(a)vivier.eu> [VIRT-109] https://projects.linaro.org/browse/VIRT-109 [Travis builds have been broken for a while] https://travis-ci.org/qemu/qemu/builds [atomic_8 issues have broken 32 bit builds] https://app.shippable.com/github/qemu/qemu/dashboard Other Tasks =========== - Continued working on "My Other Machine is Virtual" talk for YVR18 - finished main talk, iterating and practising now - also made a few [fixes and enhacements for tlb tracking] - Administrava - caught up with expense claims for SynQuacer - organising for KVM Forum 2018 - organising/travel to Connect [fixes and enhacements for tlb tracking] https://github.com/stsquad/qemu/tree/misc/dfilter-and-trace-tweaks-v2 Completed Reviews [4/4] ======================= {PATCH 0/6} target/arm: More sve-ish fixes Message-Id: <20180810193129.1556-1-richard.henderson(a)linaro.org> - CLOSING NOTE [2018-09-07 Fri 16:36] Already in target-arm.next {Qemu-devel} {PATCH 0/3} synchronization profiler Message-Id: <20180813171132.21939-3-cota(a)braap.org> - CLOSING NOTE [2018-09-07 Fri 17:41] Already merged {PATCH 0/6} i386 + x86_64 mttcg Message-Id: <20180903171831.15446-1-cota(a)braap.org> - CLOSING NOTE [2018-09-10 Mon 10:18] Quick pass, looks OK but a question about __thread w.r.t tcg globals {PATCH v2 0/2} softfloat tests based on berkeley's testfloat Message-Id: <20180908191735.22861-1-cota(a)braap.org> - CLOSING NOTE [2018-09-10 Mon 12:27] Looks like an improvement on IBM test suite but needs a few more tweaks. Absences ======== - YVR18 Connect (17th-21st September 2018) - KVM Forum 2018 (24th-26th October 2018) Current Review Queue ==================== * {PATCH v3 0/3} softfloat tests based on berkeley's testfloat Message-Id: <20180913213910.28189-1-cota(a)braap.org> * {PATCH v3 00/13} i386 + x86_64 mttcg Message-Id: <20180911202823.21657-1-cota(a)braap.org> * {PATCH v6 00/25} Fixing record/replay and adding reverse debugging Message-Id: <20180912081747.3228.21861.stgit@pasha-VirtualBox> * {Qemu-devel} {PATCH v2 00/11} convert CPU list to RCU Message-Id: <374f82bc-1680-a59d-aa71-31e88e4936a2(a)redhat.com> * {Qemu-arm} {PATCH 00/15} gdbstub: support for the multiprocess extension Message-Id: <20180901124639.19735-1-luc.michel(a)greensocs.com> * {Qemu-devel} {PATCH v4 0/5} Acceptance/functional tests Message-Id: <20180530184156.15634-1-crosa(a)redhat.com> -- Alex Bennée

7 years, 1 month

[ACTIVITY] 2 weeks ending 17 Sep 2018

by Richard Henderson

Last week: Holiday. 3 days at GNU Cauldron. Highlights: * Talked with arm folk re the sve simd abi, * Talked with arm folk re valgrind support for sve, * Talked with riscv folk re their nascent vector extension, * Peter Sewell's memory object semantics for defacto c. This week: Caught up on email backlog. Queued a few patch sets for first 3.1 tcg-next pull. Posted an rfc for adjusting arm id system regs vs feature bits. r~

7 years, 1 month

Python test error

by Kugan Vivekanandarajah

Hi Mathias, I am not able to reproduce error in https://objectstorage.prodstack4-5.canonical.com/v1/AUTH_77e2ada1e7a84929a7… Do you have any instructions for reproducing it locally. This is what I have done: Downloaded https://www.python.org/ftp/python/2.7.4/Python-2.7.4.tgz Applied following patch to build for aarch64: diff -r 84cef4f1999a -r 05e8999a3901 Modules/_ctypes/libffi/fficonfig.py.in --- a/Modules/_ctypes/libffi/fficonfig.py.in Mon Apr 29 16:09:39 2013 -0400 +++ b/Modules/_ctypes/libffi/fficonfig.py.in Tue Apr 30 01:00:34 2013 +0200 @@ -28,6 +28,7 @@ 'PA': ['src/pa/linux.S', 'src/pa/ffi.c'], 'PA_LINUX': ['src/pa/linux.S', 'src/pa/ffi.c'], 'PA_HPUX': ['src/pa/hpux32.S', 'src/pa/ffi.c'], + 'AARCH64' : ['src/aarch64/ffi.c', 'src/aarch64/sysv.S'], } ffi_sources += ffi_platforms['@TARGET@'] ./configure Also tried ./configure --enable-pydebug and --disable-optimization Also tried changing to -O0 manually in the make file make ./python Lib/test/regrtest.py -v test_ctypes Used gcc version 8.2.1 20180907 (GCC) Results are OK. Thanks, Kugan

7 years, 1 month

[ACTIVITY] 3-9 September 2018

by Christophe Lyon

== Progress == * FDPIC - GCC: handling feedback on v2 patches * GCC upstream validation: - started looking at backlog of regression reports * misc (conf-calls, meetings, emails, ....) - preparing short session on FDPIC for Connect (TCWG hacking room) - Jira prioritization - Attended GNU Cauldron 2018 == Next == FDPIC: - GCC: handle v2 patches feedback - uclibc-ng: look at how to test fdpic mode with openadk - Connect: prepare hacking room presentation

7 years, 1 month

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