The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2019.01 snapshot of the Linaro GCC 7 source package.
The GCC 7 series introduced an ABI change for ARM targets by fixing a bug (present since GCC 5, see link below) that affects conformance to the procedure call standard (AAPCS). The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
This snapshot1 is based on FSF GCC 7.4+svn267072 and includes performance improvements and bug fixes backported from mainline GCC. The contents of this snapshot will be part of the 2019.01 stable2 periodic release.
Interesting changes in this GCC source package snapshot include:
Updates to GCC 7.4+svn267072
Linaro bug 4007: “Internal compiler error with -mcpu=thunderx2t99” is fixed
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[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
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== Progress ==
* SVE ACLE
- Revised svmla, svmls, svmad and svmsb and committed after getting ACK
- Revised again posted for review
* svabs, svneg, svnot and svsqrt series
* svdiv series
* svmulh series
* svand, svorr, and sveor series
* svdot series
== Plan ==
* Contine with sve acle
[LLVM-520] LLD Fix movt/movw relocation overflow
Now committed upstream.
[LLVM-521] Taking the address of an ifunc in AArch64
Prompted by a bug report and comment about pointer equivalence, spent
some time looking into gold, lld and bfd behaviour to ensure that LLD
is at least correct.
Other
Some investigation into LLD non-support of common-page-size and
whether this is significant for code-size. Used in response to query
about whether LLD should change default value of max-page-size.
Thoughts about whether a linker must generate cantunwind .ARM.exidx
sections for code sections missing a .ARM.exidx section. If C++ code
with exceptions is interleaved with some assembly code without
.ARM.exidx sections then the assembly code can match the address range
of the C++ code that precedes it.
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ rth's pointer-auth emulation patchset
+ more devices for the microbit board model
+ support for u-boot "noload" image type
+ gdbstub multiprocess extension support for use when the board
model has multiple asymmetric clusters (like Xilinx Zynq boards)
- finished debugging patch for aarch64 host linux-user to distinguish
SEGV on read from SEGV on write by looking at the ESR context struct
from the kernel rather than by looking at the faulting insn; sent it.
- sent patch to fix linux-user pread64/pwrite64 with NULL buffer and 0 length
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
- Sent out patchset fixing heterogenous CPU support (required a lot
of thought about what we might need to fix and not all that much
code, in the end)
- Started work on refactoring our IoTKit model to also support
the extra pieces required by the SSE-200 subsystem used in the Musca
thanks
-- PMM
Upstream Work ([VIRT-109])
==========================
- posted {PATCH v1 0/6} current fpu/next queue Message-Id:
<20190108162154.22259-1-alex.bennee(a)linaro.org>
- posted {PATCH v1 0/3} gitdm updates Message-Id:
<20190107111129.2087-2-alex.bennee(a)linaro.org>
- posted {PATCH v1 00/19} testing/next queue for travis and docker
Message-Id: <20190110174516.21586-1-alex.bennee(a)linaro.org>
- also managed to trigger two of the occasional Travis failures
locally
- one is a segfault in mcount (gprof/RCU related)
- the other seems to be a O_NONBLOCK/make interaction (using eBPF
to track it)
- did a little more on re-work of [system test and misc arch] tests
- will be useful for test cases for plugins
- respin {PATCH v3 0/5} support reading some CPUID/CNT registers from
user-space Message-Id:
<20180625160009.17437-1-alex.bennee(a)linaro.org> :todo
- in branch [v3 branch]
[VIRT-109] https://projects.linaro.org/browse/VIRT-109
[system test and misc arch]
https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v2
[v3 branch]
https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3
Completed Reviews [2/2]
=======================
{PATCH v3 0/2} tests: Reorganize MIPS TCG directories and files
Message-Id: <1546621859-28227-1-git-send-email-aleksandar.markovic(a)rt-rk.com>
- CLOSING NOTE [2019-01-07 Mon 11:23]
A few notes about keeping makefile
{PATCH 00/13} Misc fixes / improvements for the docker and travis configs
Message-Id: <20190109163114.17010-1-berrange(a)redhat.com>
- CLOSING NOTE [2019-01-10 Thu 12:34]
Queued a chunk of these into testing/next
Absences
========
- Connect BKK19 (1-5th April 2019)
- holiday after Connect
Current Review Queue
====================
* {Qemu-devel} {PATCH 00/11} target/arm: Implement ARMv8.5-BTI
Message-Id: <20190110121736.23448-1-richard.henderson(a)linaro.org>
* {PATCH v9 00/21} Fixing record/replay and adding reverse debugging
Message-Id: <154703587757.13472.3898702635363120794.stgit@pasha-VirtualBox>
* {Qemu-devel} {PATCH 0/4} tcg: support heterogenous CPU clusters
Message-Id: <20190108163008.7006-1-peter.maydell(a)linaro.org>
* {Qemu-devel} {PATCH v3 00/31} target/arm: Implement ARMv8.3-PAuth
Message-Id: <20190108223129.5570-1-richard.henderson(a)linaro.org>
* {Qemu-arm} {PATCH 0/3} target/arm: Vector expansion improvments.
Message-Id: <20190106225035.5671-1-richard.henderson(a)linaro.org>
* {Qemu-devel} {PATCH} configure: Force the C standard to gnu11
Message-Id: <1546857926-5958-1-git-send-email-thuth(a)redhat.com>
--
Alex Bennée
== Progress ==
* FDPIC
- (GNU-499) GCC: wait for feedback on v4 patches, but GCC just entered
stage4, so it's probably too late for gcc-9 :-(
- (GNU-411) GDB: hacked to build gdbserver, but the resulting binary
does not start.
* GCC upstream validation:
- reported a few regressions
- dealing with some random results, still
- qemu-3.1.0-rc3, memory consumption: more experiments under LSF show
"random" reports for memory consumption. It seems qemu-3.1 consumes
more memory in some cases, though.
* GCC:
- (GNU-99) rebased ubsan / bare-metal patches. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing/submitted infra script patches
- dealing with nasty ST-internal infrastructure problems
- (GNU-592): improved benchmarking scripts
- (TCWG-1501) looking at new build servers configs
== Next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
Validation:
- isolate if/why qemu-3.1.0-rc3 consumes more memory than 2.11 for
aarch64-linux target
== Progress ==
* [ARM GlobalISel] Select complicated G_CONSTANT [LLVM-491]
- Negative constants in particular cause a lot of fallbacks in the
test-suite/selfhost
- Need to help TableGen produce code for MOVi32imm
- Ready to commit next week
- Looked a bit into enabling MVNi as well, but that seems to require
more effort
* Use new version of GCC on buildbots [LLVM-515]
- Talked to doko and got a different PPA
- Didn't get a chance to test it yet, will do next week
* Sanity checks for docker builbbot containers
- Sent a quick patch to check slavenames and compatibility between
slave and image when starting a bot container
* Investigated some buildbot failures
- Marked 2 sanitizer tests as unsupported on ARM
- Need to investigate further so we can re-enable them
- I've been emailing the author, hopefully he can help debug
== Plan ==
* More of the same
