linaro-toolchain

linaro-toolchain@lists.linaro.org

2 participants
5601 discussions

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + code review: - 'SBSA reference' model (now quite close to being in shape to go in) - RTH's BTI patchset - RTH's patchset adding TBI support to user-mode emulation + sent patches fixing the last lot of clang -Waddress-of-packed-member warnings + had another look at the prototype work I did to use Sphinx for QEMU's documentation -- updated the patchset and started looking at how to tie it into our makefiles. + sent patches fixing a handful of underdecodings in our A64 decoder, where we should have UNDEFed but did not * VIRT-268 [QEMU support for dual-core Cortex-M Musca board] + sent out v1 of the patchset implementing the SSE-200 and MPS2 AN521 model + read through the Musca-B1 docs to confirm what we can easily put into an initial implementation of a model thanks -- PMM

6 years, 5 months

[ACTIVITY] 21 - 25 January 2019

by Diana Picus

== Progress == * Out of office on Monday * [Thumb GlobalISel] Support G_SHL, G_ASHR, G_LSHR [LLVM-517] - Committed upstream * [Thumb GlobalISel] Support G_SDIV and G_UDIV [LLVM-516] - Most of the work done, ready to commit next week * LLVM 8.0 Release for ARM & AArch64 [LLVM-526] - Started a few jobs, but ran into some trouble with our containers - Will look more into it next week * Use new version of GCC on buildbots [LLVM-515] - Got it to work and committed patch; we have 2 silent bots running with GCC-7 - Will keep monitoring the bots and if they seem stable we can merge to tcwg-llvmprod next week == Plan == * Test LLVM 8.0.0 RC1 * Commit LLVM-516 * More GlobalISel * Out of office on Friday

6 years, 5 months

[ANNOUNCE] Linaro Binary Toolchain Release GCC 7.4-2019.02

by Mark Murray

The Linaro Binary Toolchain ============================ The Linaro GCC 7.4-2019.02 Release is now available. *Notice*: GCC 7.1 ABI change for arm*-*-* targets, and note for aarch64*-*-* targets >From GCC 7.1 release notes: On ARM targets (arm*-*-*), a bug introduced in GCC 5 that affects conformance to the procedure call standard (AAPCS) has been fixed. The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. This is an ABI change. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected. https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728 GCC 5 and GCC 6 releases will continue to be affected by the ABI bug, since changing ABI in these releases is not practical. A warning enabled by -Wpsabi option was added to GCC 5 and GCC 6 toolchains to diagnose codebases that might be affected by the ABI bug. Additionally, this same bug was present in AArch64 backend in development versions of GCC 7. There was no releases of GCC with this bug present in AArch64 backend, therefore the release notes does not mention this. However, be advised that any code bases built with development versions of GCC 7 need to be recompiled with released version of GCC 7 to conform to ABI. For an explanation of GCC 7 series changes please see the following website: https://gcc.gnu.org/gcc-7/changes.html For help in porting to GCC 7 please see the following explanation: https://gcc.gnu.org/gcc-7/porting_to.html Download release packages from: (sources) http://releases.linaro.org/components/toolchain/gcc-linaro/7.4-2019.02/ (binaries) http://releases.linaro.org/components/toolchain/binaries/7.4-2019.02/ Previous snapshots and release-candidates are at: http://snapshots.linaro.org/components/toolchain/binaries/ Previous releases are at: http://releases.linaro.org/components/toolchain/binaries/ A description of the arm and AArch64 target triples can be found at: https://collaborate.linaro.org/display/TCWGPUB/ARM+and+AArch64+Target+Tripl… Host Requirements ================== Linaro officially supports the current and previous Ubuntu LTS releases (as of the time of this release). This does not mean that the toolchain will not work on other/older Linux distributions. See the following for the life-time of Ubuntu LTS releases. https://wiki.ubuntu.com/Releases The host system upon which the cross-compiler will run requires a minimum of glibc 2.14, because of API changes to glibc's memcpy API. https://bugs.linaro.org/show_bug.cgi?id=1869 Package Versions ================= Linaro GCC 7.4-2019.02 http://releases.linaro.org/components/toolchain/gcc-linaro/7.4-2019.02/ FSF glibc 2.25 (release/2.25) https://lists.gnu.org/archive/html/info-gnu/2017-02/msg00002.html Newlib 2.5 (newlib-2_5_0 tag) https://sourceware.org/ml/newlib/2016/msg01191.html GNU Binutils 2.28 (users/linaro/binutils-2_28-branch) https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=blob_plain;f=bin… FSF GDB 8.2 (gdb-8.2-branch) https://lists.gnu.org/archive/html/info-gnu/2018-09/msg00001.html Linaro toolchain package git branches are hosted at: http://git.linaro.org/toolchain NEWS for GCC 7 (as of Linaro GCC 7.4-2019.02) ============================================== * Runtest and gdbserver are no longer installed in the toolchain bin/ directory. Binary releases no longer include runtest at all, and gdbserver is a target tool; it is now shipped in the sysroot under usr/bin/. LDTS case #2211: gdbserver and runtest in GCC binary release are in the wrong place or have the wrong name * Gdbserver is no longer linked statically, because this is currently unsupported. Linaro bugzilla #3344: gdbserver broken in Linaro 2017.02 https://bugs.linaro.org/show_bug.cgi?id=3344 * The Linaro GCC 7.4-2019.01 snapshot added a fix for Linaro bug 4007: "Internal compiler error with -mcpu=thunderx2t99". * The Linaro GCC 7.2-2017.09 snapshot added float and integer moves improvement for AArch64 targets. * The Linaro GCC 7.1-2017.07 snapshot added prefetching configuration improvement for AArch64 targets and laid groundwork to enabling prefetching in more cases. * Previous MinGW hosted version of Linaro GCC C preprocessor failed to convert character set used for string, character constants, etc. This is fixed in this release. Linaro bugzilla #3040 : CC1 and cc1plus cannot convert UTF-8. https://bugs.linaro.org/show_bug.cgi?id=3040 * Performance related backports from the following snapshots have been included: Linaro GCC 7.1-2017.05, Linaro GCC 7.1-2017.06, Linaro GCC 7.1-2017.07, Linaro GCC 7.2-2017.08, Linaro GCC 7.2-2017.09, Linaro GCC 7.2-2017.10, Linaro GCC 7.2-2018.04 and Linaro GCC 7.4-2019.01. See the following Linaro GCC snapshots: http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.05/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.06/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.07/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.08/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.09/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2017.10/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.2-2018.04/ http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.4-2019.01/ Contact Linaro =============== File bugs at http://bugs.linaro.org For Linaro member support see http://support.linaro.org For Linaro community support email linaro-toolchain(a)lists.linaro.org

6 years, 5 months

Any 4.8.5 cross compile toolchain?

by xinliang

Hi Martin and Linaro-toolchain team, We want to use 4.8.5 cross compile toolchain to build ko. But we can't find such version on the release site[1]. Is there a 4.8.5 cross compile toolchain? [1] https://releases.linaro.org/components/toolchain/gcc-linaro/ Best, Xinliang

6 years, 5 months

[ACTIVITY] Week 03

by Yvan Roux

o Still part time at university. o LLVM * Preparing machine outliner upstream submission as an RFC.

6 years, 5 months

[ACTIVITY] 14-18 January 2019

by Kugan Vivekanandarajah

== Progress == * SVE ACLE - Committed patches for * svabs, svneg, svnot and svsqrt series * svdiv series * svmulh series * svand, svorr, and sveor series * svdot series - Working on svbic and svbic_b variants * Others - Looking into tree-reassoc improvements for next stage1 - Looked into kernel plugin issue for arm == Plan == * Continue with SVE ACLE * Continue with tree-reassoc

6 years, 5 months

[ACTIVITY] week ending 20 Jan 2019

by Richard Henderson

[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Posted v1. [VIRT-327 # Richard's upstream QEMU work ] Posted v6 of linux-user split. Based on Laurent's feedback, I'm running LTP myself this time, at least for a few guests. r~

6 years, 5 months

[ACTIVITY] week ending Jan. 20 2019

by Alex Bennée

Upstream Work ([VIRT-109]) ========================== - posted {PULL 0/5} gitdm updates with final 2018 stats Message-Id: <20190114160956.7513-1-alex.bennee(a)linaro.org> - posted {PULL 00/21} misc testing fixes for Travis and docker Message-Id: <20190114150129.1013-1-alex.bennee(a)linaro.org> - we have gone green again - posted {PULL 0/7} check-softfloat, fp-bench and clang compile fixes Message-Id: <20190117132703.17790-1-alex.bennee(a)linaro.org> - some alt-OS issues and a weird failure on s390x - spent some time getting a working s390x setup to investigate - posted {PATCH} target/s390x: define TCG_GUEST_DEFAULT_MO for MTTCG Message-Id: <20190118171848.27332-1-alex.bennee(a)linaro.org> - need to investigate why s390x breaks so weirdly - messed around with a little [CONFIG_TCG type cleanups] - need to finish the re-work of [system test and misc arch] tests :todo - will be useful for test cases for plugins - also more test cases queued up for system tests - respin {PATCH v3 0/5} support reading some CPUID/CNT registers from user-space Message-Id: <20180625160009.17437-1-alex.bennee(a)linaro.org> :todo - in branch [v3 branch] [VIRT-109] https://projects.linaro.org/browse/VIRT-109 [CONFIG_TCG type cleanups] https://github.com/stsquad/qemu/tree/misc/config-tcg-cleanups [system test and misc arch] https://github.com/stsquad/qemu/tree/testing/enable-system-tcg-tests-v2 [v3 branch] https://github.com/stsquad/qemu/tree/misc/cnt-and-misc-reg-fixes-v3 Other Tasks =========== - wrote up and submitted abstract for Connect - I still hope to the history of TCG for TCWG room as well Completed Reviews [4/4] ======================= {Qemu-devel} {PATCH} .cirrus.yml: basic compile and test for FreeBSD Message-Id: <CAPyFy2Dw2F3ks_5f8cvWjrsOTS0_Ybr5kELUpyHQmOQWUaeuFg(a)mail.gmail.com> - CLOSING NOTE [2019-01-16 Wed 15:01] Adds FreeBSD testing, yet another CI system {PATCH v2} softfloat: enforce softfloat if the host's FMA is broken Message-Id: <20181225070305.18221-1-cota(a)braap.org> - CLOSING NOTE [2019-01-16 Wed 15:03] Queued to my tree {PATCH v6 0/3} Dynamic TLB sizing Message-Id: <20190114165017.27298-1-cota(a)braap.org> - CLOSING NOTE [2019-01-17 Thu 10:53] Found a few issues. {PATCH v7 0/3} Dynamic TLB sizing Message-Id: <20190116170114.26802-1-cota(a)braap.org> - CLOSING NOTE [2019-01-18 Fri 16:54] Looks good to me now. Absences ======== - Connect BKK19 (1-5th April 2019) - holiday after Connect Current Review Queue ==================== * {PATCH 0/2} contrib: gitdm: Some updates Message-Id: <1547807155-4526-1-git-send-email-aleksandar.markovic(a)rt-rk.com> * {PATCH 00/18} Acceptance Tests: target architecture support Message-Id: <20190117185628.21862-1-crosa(a)redhat.com> * {Qemu-devel} {PATCH 00/11} target/arm: Implement ARMv8.5-BTI Message-Id: <20190110121736.23448-1-richard.henderson(a)linaro.org> * {PATCH v5 00/73} per-CPU locks Message-Id: <20181213050453.9677-1-cota(a)braap.org> * {RFC v2 00/38} Plugin support Message-Id: <20181209193749.12277-1-cota(a)braap.org> * {RFC} arm: Allow system registers for KVM guests to be changed by QEMU code Message-Id: <20181206151401.13455-1-peter.maydell(a)linaro.org> -- Alex Bennée

6 years, 5 months

[ACTIVITY] report week ending 18 Jan

by Peter Smith

[LLVM-521] LLD and taking the address of an ifunc Went through the possible combinations (pic, pie, non-pic, exec, shared,...) found one relocation that gcc uses that clang doesn't, hence mc and LLD don't support. Raised upstream pr. Also found that clang's code-sequence for -fpie doesn't seem to guarantee ifunc pointer equivalence when linking -fpie (non-got generating sequence used when ifunc is in same translation unit). Will need some further investigation to confirm. [LLVM-499] Support for linking the linux kernel Committed -pic-veneer support and associated overflow fix, now merged to 8.0 branch. Other: - Started work on Fosdem presentation on LLD performance. Studying ld.bfd and ld.gold source code to look for structural differences between them and LLD. - Submitted presentation for next Linaro Connect - Review for comdat group and unused section elimination. - On buildbot duty.

6 years, 5 months

[ACTIVITY] report week ending 18 Jan

by Peter Maydell

Progress: * VIRT-65 [QEMU upstream maintainership] + some code review, and another arm pull-request (including RTH's pointer auth work) + sent patch fixing a bug in the gdbstub memory access path that meant it was always making accesses as NonSecure even if the guest CPU was currently Secure + sent patch fixing checkpatch to not wrongly complain about block comments starting "/**" * VIRT-268 [QEMU support for dual-core Cortex-M Musca board] + I have a model of the SSE-200 subsystem used by the Musca board, and a model of the MPS2 AN521 FPGA image which uses it. (Since it is basically "our existing MPS2 AN505 model, but with SSE-200 rather than IoTKit" it's a useful stepping stone to the Musca board.) There are still some bugs and missing features, but it seems to mostly be functional (it can run the ARM Trusted Firmware M test binary.) thanks -- PMM

6 years, 5 months

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