== Progress ==
* Out of office 1 day
* Buildbot monitoring
- Moved the buildbots to pull from github
* Trying to setup a build environment on ex40-01
- Gave up on the tcwg-sq-01/2 boards because they seemed too unstable
* Still no access to Morello docs
* Playing with lldb python scripting
- Got a script that intercepts all calls to
VectorType::getNumElements that don't come from a getElementCount
(since that likely means that they won't be preserving the 'scalable'
property)
- This should help figure out problems spotted by the fuzzer
- Likely needs a bit more refining
== Plan ==
* More of the same
* Out of office on Friday (1 November)
== Progress ==
* GCC:
- -mpure-code on v6m: no feedback yet
* FDPIC/GDB
- problems with the board I used, it hangs shortly after or during
boot. None of the workaround/fixes suggested to me worked. Having an
stm32 qemu config would help.
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
- sent 2 small qemu patches (fix vmrs support for m-profile, and add cortex-m7)
- confirmed that gcc LTO profiled bootstrap works on arm with recent
trunk, although it takes ages. Will need to try on a more powerful
board
== Next ==
* Holidays next week, back Nov 4th
* FDPIC: resume work on GDB: check the various qemu forks with stm32
board support.
Add FDPIC configuration in the GCC trunk validation.
* GCC: pure-code/v6m, handle feedback
* Binutils: support non-contiguous memory regions in linker
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ lots of wrangling of patches and pulls since I'm away
next week and it's also going to be softfreeze
+ preparation for KVM Forum next week
thanks
-- PMM
Progress:
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Updates for user-only.
Merge bug fixes from eugeni.stepanov(a)gmail.com.
[VIRT-349 # QEMU SVE2 Supprt ]
Convert neon pmul helpers to a form that will be usable for sve2.
[VIRT-327 # Richard's upstream QEMU work ]
Pull for tcg-next.
Review plugins v5.
Update for capstone submodule.
Started reviewing multi-phase reset v5.
[Kernel]
Hacked up a patch for ARMv8.5-RNG.
r~
# Progress #
o Ramp up
* Credentials, machine access and LDAP updates done.
o Qualcomm Landing Team sunsetting
* Returned Qualcomm's Laptop.
o Upstream GDB
* Ramping up on reviews.
* Gathering data on the current state of GDB on ARM.
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- Came up with a little hack/proof-of-concept to get this fixed.
Though ugly, it seems fixing this in the front-end may make more sense,
as the information i need (source line) is easily accessible in there.
- Discussion ongoing with gcc@. GDB clearly needs the compiler to
provide more information.
* Created JIRA cards for all known pending ARM tasks for GDB, based
on Alan's and Joey's input. TODO-ed all of them for the time being.
# Plan #
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- Continue pursuing a fix.
* Prioritize GDB JIRA cards and start work on them.
[Morello]
- Got static linking support to the point that I can successfully link
with LLD the coremark, dhrystone and EEMBC from the arran-toolchain.
Not got any outstanding failures to investigate.
- Altered LLD so a linker script is no longer necessary for newlib.
- Started the process of rebasing and adding tests for all the
fixes/hacks I needed to make to the linker work.
- Aligned the base and limit of capabilities according to the incoming
CHERI concentrate scheme. Interesting question of what should a linker
do when alignment requirements on the base and limit cross section
boundaries, and what are the responsibilities for an object producer
when creating a section when the length of the capability is known at
compile time.
Planned absences:
Holiday Thursday, Friday (24th, 25th October)
