Hi, Chris, and Linaro Toolchain team,
Recently I found an issue of SVE intrinsics (svld1_f64, svld1_vnum_f64)
when using gcc -O0 (gcc 10.0.1 debian nightly build, optimization level 0).
Would you please help me to reach out to people who can fix it?
svld1_f64() is a function defined in Arm intrinsics for SVE (scalable
vector extensions) [2].
Changing -O0 to -O1 makes the issue disappear.
svld1_vnum_f64() has the same problem.
To show the issue, I wrote this simple test program, see test1.c in [1]. A
full issue report and gcc version string can be found in the attached pdf
file.
[1] My test program:
https://github.com/docularxu/sve-code-test/tree/working-svld1_f64
[2] Arm SVE intrinsics: https://developer.arm.com/docs/100987/latest
Feel free to contact me if you need more details.
Best regards,
-Guodong Xu
[VIRT-349 # QEMU SVE2 Support ]
More progress on insn implementation; just about done with all of the indexed
multiply. Perhaps 10 insns remaining.
Assad mentioned on irc that he has fixed the Armie bug that prevented RISU from
running properly, so I hope to start doing some testing soon.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed Peter's decodetree conversion. Posted some extracts from my sve2
branch that may be relevant and helpful.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ rth's v3 patchset for 'sve load/store improvements'
+ Paolo's improvements to my run-coverity-scan script
- tagged QEMU 5.0 and pushed it out of the door; put together and
sent out the first target-arm pullreq for the 5.1 cycle
* VIRT-364 [QEMU support for ARMv8.1-M extensions]
- Neon decodetree progressing nicely (though it is a bigger
job than I had anticipated when I started it...) Sent out a
first part patchset that covers the v8.0-and-later extensions,
the loads-and-stores, and the 3-reg-same part of the dp insns.
NB: UK bank holiday next Friday...
thanks
-- PMM
Hi,
You are receiving this email because you are listed as the owner for at least one LLVM build slave on http://lab.llvm.org:8011/buildslaves <http://lab.llvm.org:8011/buildslaves>.
This message is a heads up concerning the upcoming upgrade of CMake discussed here: http://lists.llvm.org/pipermail/llvm-dev/2020-March/140349.html <http://lists.llvm.org/pipermail/llvm-dev/2020-March/140349.html>. As discussed on that thread, LLVM will require CMake 3.13.4 in order to build after the release branch for LLVM 11.0.0 is created. Using an older CMake will be an error.
In order to keep things running smoothly, we would greatly appreciate if you could upgrade CMake on your builder(s) to at least CMake 3.13.4 before the next release branch is created. Please reply privately to this email when you've done so -- this will allow keeping track of who has and has not upgraded.
Thank you and have a wonderful day,
Louis
Short week (4 days)
== Progress ==
* GCC upstream validation:
- reported a couple of failures/regressions
- still looking at improving MVE tests to avoid failures in several
non-supported configurations. No satisfactory solution so far (there
are always combinations of GCC configure option and validation-time
options that are incompatible and produce failures instead of
unsupported)
- maybe we should agree on a common way of running the testsuite
* GCC:
- PR94743 (IRQ handler and Neon registers): sent a patch to emit a
warning. More ambitious patches would be too intrusive for stage 4.
* FDPIC/GDB:
- no progress this week
* misc:
- infra fixes / troubleshooting / reviews
- started looking at cortex-m benchmarking harnesses
== Next ==
* FDPIC GDB
* GCC/cortex-M
* cortex-m benchmarking
== Progress ==
* Morello
- Finished capability formatting
- Got a couple cosmetic patches in review
- Also reviewing needed ptrace support
== Plan ==
* More Morello
[VIRT-349 # QEMU SVE2 Support ]
More progress on insn implementation.
More patches from Stephen Long merged.
More good review from Laurent Desnogues.
Down to perhaps 30 insns remaining, and then figuring out some miscomparisons
reported by Laurent, but not diagnosed.
[VIRT-344 # ARMv8.5-MemTag ]
Fixed an exception return bug vs PSTATE.TCO.
[VIRT-327 # Richard's upstream QEMU work ]
Posted some tcg patch sets for 5.1.
Worked on the sparc regression Alex reported vs TEMP_CONST. I've set that
aside for now; I need to come up with a new scheme to debug that one.
r~
Progress:
* VIRT-65 [QEMU upstream maintainership]
- We needed an rc4 (which I wasn't very surprised about), so more
release wrangling again.
- Noticed some bugs in how we set ID registers for the AArch64 'max' CPU;
sent patches (one of which seemed worth getting into rc4)
- There's been a long-standing problem where a linux-user QEMU running
on a 64-bit host and emulating a 32-bit guest can't deal with the
64-bit hash 'offsets' from ext4 getdents, which causes guests using
newer glibc to fail. Linus Walleij wrote a kernel patch which allows
QEMU to request that the kernel gives it hash values that will fit
into 32 bits. I wrote an RFC QEMU patch that would use this and tested
that this does indeed solve the problem. Discussion is continuing on
the kernel size about what the correct API for this is, but the
principle that the kernel should change seems to be accepted.
- A bug was raised that BKPT for arm linux-user wasn't causing SIGTRAP;
sent patches fixing that and some other issues I noticed in that
bit of the code while I was fixing it.
- code review:
+ a patch adding proper FIFO emulation to the PL011 UART model
+ rth's patchset improving codegen of neon integer-compare-vs-0 insns
+ xilinx patchset to disable unsupported FDT firmware nodes
+ patchset adding kaslr-seed properties to the virt board dtb
(mostly useful for OP-TEE)
* VIRT-364 [QEMU support for ARMv8.1-M extensions]
- Progress with neon decodetree conversion. I've now completed all
the 3-reg-same insn grouping, which is a large enough amount that
I'm planning to send out a patchset with what I have so far.
Need to refactor/tidy up some bits of the code first, now I can
see what the completed conversion looks like.
thanks
-- PMM
