Move all the type of frame handling within the dcmi_irq_thread handler and do not rely on dma_callback as previously.

This simplifies the code by having only a single path for both compressed and uncompressed data while also making the system more reactive since irq_handler have more chances to be called faster than the dma completion callback. Indeed, in case of the dma completion callback, this run as a tasklet created by the dma framework upon getting an interrupt from the dma and run at a lower priority level than other irq handlers.

Signed-off-by: Alain Volmat alain.volmat@foss.st.com --- drivers/media/platform/st/stm32/stm32-dcmi.c | 97 ++++++---------------------- 1 file changed, 18 insertions(+), 79 deletions(-)

diff --git a/drivers/media/platform/st/stm32/stm32-dcmi.c b/drivers/media/platform/st/stm32/stm32-dcmi.c index 2fec10d13913..66bb79038c54 100644 --- a/drivers/media/platform/st/stm32/stm32-dcmi.c +++ b/drivers/media/platform/st/stm32/stm32-dcmi.c @@ -227,8 +227,9 @@ static int dcmi_restart_capture(struct stm32_dcmi *dcmi) { struct dcmi_buf *buf;

+ /* Nothing to do if we are not running */ if (dcmi->state != RUNNING) - return -EINVAL; + return 0;

/* Restart a new DMA transfer with next buffer */ if (list_empty(&dcmi->buffers)) { @@ -242,52 +243,6 @@ static int dcmi_restart_capture(struct stm32_dcmi *dcmi) return dcmi_start_capture(dcmi, buf); }

-static void dcmi_dma_callback(void *param) -{ - struct stm32_dcmi *dcmi = (struct stm32_dcmi *)param; - struct dma_tx_state state; - enum dma_status status; - struct dcmi_buf *buf = dcmi->active; - - spin_lock_irq(&dcmi->irqlock); - - /* Check DMA status */ - status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); - - switch (status) { - case DMA_IN_PROGRESS: - dev_dbg(dcmi->dev, "%s: Received DMA_IN_PROGRESS\n", __func__); - break; - case DMA_PAUSED: - dev_err(dcmi->dev, "%s: Received DMA_PAUSED\n", __func__); - break; - case DMA_ERROR: - dev_err(dcmi->dev, "%s: Received DMA_ERROR\n", __func__); - - /* Return buffer to V4L2 in error state */ - dcmi_buffer_done(dcmi, buf, 0, -EIO); - break; - case DMA_COMPLETE: - dev_dbg(dcmi->dev, "%s: Received DMA_COMPLETE\n", __func__); - - /* Return buffer to V4L2 */ - dcmi_buffer_done(dcmi, buf, buf->size, 0); - - spin_unlock_irq(&dcmi->irqlock); - - /* Restart capture */ - if (dcmi_restart_capture(dcmi)) - dev_err(dcmi->dev, "%s: Cannot restart capture on DMA complete\n", - __func__); - return; - default: - dev_err(dcmi->dev, "%s: Received unknown status\n", __func__); - break; - } - - spin_unlock_irq(&dcmi->irqlock); -} - static int dcmi_start_dma(struct stm32_dcmi *dcmi, struct dcmi_buf *buf) { @@ -344,7 +299,7 @@ static void dcmi_set_crop(struct stm32_dcmi *dcmi) reg_set(dcmi->regs, DCMI_CR, CR_CROP); }

-static void dcmi_process_jpeg(struct stm32_dcmi *dcmi) +static void dcmi_process_frame(struct stm32_dcmi *dcmi) { struct dma_tx_state state; enum dma_status status; @@ -354,13 +309,11 @@ static void dcmi_process_jpeg(struct stm32_dcmi *dcmi) return;

/* - * Because of variable JPEG buffer size sent by sensor, - * DMA transfer never completes due to transfer size never reached. - * In order to ensure that all the JPEG data are transferred - * in active buffer memory, DMA is drained. - * Then DMA tx status gives the amount of data transferred - * to memory, which is then returned to V4L2 through the active - * buffer payload. + * At the time FRAME interrupt is received, all dma req have been sent to the DMA, + * however DMA might still be transferring data hence first synchronize prior to + * getting the status of the DMA transfer. + * Then DMA tx status gives the amount of data transferred to memory, which is then + * returned to V4L2 through the active buffer payload. */

spin_unlock_irq(&dcmi->irqlock); @@ -368,16 +321,16 @@ static void dcmi_process_jpeg(struct stm32_dcmi *dcmi) dmaengine_synchronize(dcmi->dma_chan); spin_lock_irq(&dcmi->irqlock);

- /* Get DMA residue to get JPEG size */ + /* Get DMA status and residue size */ status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); if (status != DMA_ERROR && state.residue < buf->size) { - /* Return JPEG buffer to V4L2 with received JPEG buffer size */ + /* Return buffer to V4L2 with received data size */ dcmi_buffer_done(dcmi, buf, buf->size - state.residue, 0); } else { dcmi->errors_count++; - dev_err(dcmi->dev, "%s: Cannot get JPEG size from DMA\n", - __func__); - /* Return JPEG buffer to V4L2 in ERROR state */ + dev_err(dcmi->dev, "%s: DMA error. status: 0x%x, residue: %d\n", + __func__, status, state.residue); + /* Return buffer to V4L2 in ERROR state */ dcmi_buffer_done(dcmi, buf, 0, -EIO); }

@@ -385,11 +338,6 @@ static void dcmi_process_jpeg(struct stm32_dcmi *dcmi) /* Abort DMA operation */ dmaengine_terminate_sync(dcmi->dma_chan); spin_lock_irq(&dcmi->irqlock); - - /* Restart capture */ - if (dcmi_restart_capture(dcmi)) - dev_err(dcmi->dev, "%s: Cannot restart capture on JPEG received\n", - __func__); }

static irqreturn_t dcmi_irq_thread(int irq, void *arg) @@ -420,12 +368,10 @@ static irqreturn_t dcmi_irq_thread(int irq, void *arg) if (dcmi->misr & IT_ERR) dcmi->errors_count++;

- if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG && - dcmi->misr & IT_FRAME) { - /* JPEG received */ - dcmi_process_jpeg(dcmi); - spin_unlock_irq(&dcmi->irqlock); - return IRQ_HANDLED; + if (dcmi->misr & IT_FRAME) { + dcmi_process_frame(dcmi); + if (dcmi_restart_capture(dcmi)) + dev_err(dcmi->dev, "%s: Cannot restart capture\n", __func__); }

spin_unlock_irq(&dcmi->irqlock); @@ -542,10 +488,6 @@ static int dcmi_buf_prepare(struct vb2_buffer *vb) return -EIO; }

- /* Set completion callback routine for notification */ - buf->dma_desc->callback = dcmi_dma_callback; - buf->dma_desc->callback_param = dcmi; - /* Mark the descriptor as reusable to avoid having to prepare it */ ret = dmaengine_desc_set_reuse(buf->dma_desc); if (ret) { @@ -818,10 +760,7 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count) }

/* Enable interruptions */ - if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG) - reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR); - else - reg_set(dcmi->regs, DCMI_IER, IT_OVR | IT_ERR); + reg_set(dcmi->regs, DCMI_IER, IT_FRAME | IT_OVR | IT_ERR);

spin_unlock_irq(&dcmi->irqlock);

Overall cleanup done allows to now have the JPEG handling done in the same way as other formats in continuous mode, allowing to achieve a faster framerate in all resolutions.

Signed-off-by: Alain Volmat alain.volmat@foss.st.com --- drivers/media/platform/st/stm32/stm32-dcmi.c | 4 ---- 1 file changed, 4 deletions(-)

diff --git a/drivers/media/platform/st/stm32/stm32-dcmi.c b/drivers/media/platform/st/stm32/stm32-dcmi.c index 6ca0ffcd97a3..97683daf179d 100644 --- a/drivers/media/platform/st/stm32/stm32-dcmi.c +++ b/drivers/media/platform/st/stm32/stm32-dcmi.c @@ -717,10 +717,6 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count) if (dcmi->do_crop) dcmi_set_crop(dcmi);

- /* Enable jpeg capture */ - if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG) - reg_set(dcmi->regs, DCMI_CR, CR_CM);/* Snapshot mode */ - /* Enable dcmi */ reg_set(dcmi->regs, DCMI_CR, CR_ENABLE);

Add properties update and new sram property necessary in order to enable the DMA-MDMA chaining.

Signed-off-by: Alain Volmat alain.volmat@foss.st.com

--- Change in v2: - correct typo (phandles -> phandle) - remove explanation about generic binding sram.yaml --- Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index 34147127192f..979360e9099e 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -27,11 +27,14 @@ properties: - const: mclk

dmas: - maxItems: 1 + minItems: 1 + maxItems: 2

dma-names: items: - const: tx + - const: mdma_tx + minItems: 1

resets: maxItems: 1 @@ -40,6 +43,12 @@ properties: minItems: 1 maxItems: 2

+ sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to a reserved SRAM region which is used as temporary + storage memory between DMA and MDMA engines. + port: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false

Perform the dma channel configuration at probe time right after the channel allocation since this is fixed for the whole lifetime of the driver.

Signed-off-by: Alain Volmat alain.volmat@foss.st.com --- drivers/media/platform/st/stm32/stm32-dcmi.c | 32 +++++++++++++--------------- 1 file changed, 15 insertions(+), 17 deletions(-)

diff --git a/drivers/media/platform/st/stm32/stm32-dcmi.c b/drivers/media/platform/st/stm32/stm32-dcmi.c index 619b0d981211..787c5d778db2 100644 --- a/drivers/media/platform/st/stm32/stm32-dcmi.c +++ b/drivers/media/platform/st/stm32/stm32-dcmi.c @@ -301,23 +301,6 @@ static int dcmi_start_dma(struct stm32_dcmi *dcmi, struct dcmi_buf *buf) { struct dma_async_tx_descriptor *desc = NULL; - struct dma_slave_config config; - int ret; - - memset(&config, 0, sizeof(config)); - - config.src_addr = (dma_addr_t)dcmi->res->start + DCMI_DR; - config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; - config.dst_maxburst = 4; - - /* Configure DMA channel */ - ret = dmaengine_slave_config(dcmi->dma_chan, &config); - if (ret < 0) { - dev_err(dcmi->dev, "%s: DMA channel config failed (%d)\n", - __func__, ret); - return ret; - }

/* * Avoid call of dmaengine_terminate_sync() between @@ -1888,6 +1871,7 @@ static int dcmi_probe(struct platform_device *pdev) struct vb2_queue *q; struct dma_chan *chan; struct dma_slave_caps caps; + struct dma_slave_config dma_config; struct clk *mclk; int ret = 0;

@@ -1954,6 +1938,19 @@ static int dcmi_probe(struct platform_device *pdev) if (!ret && caps.max_sg_burst) dcmi->dma_max_burst = caps.max_sg_burst * DMA_SLAVE_BUSWIDTH_4_BYTES;

+ memset(&dma_config, 0, sizeof(dma_config)); + + dma_config.src_addr = (dma_addr_t)dcmi->res->start + DCMI_DR; + dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + + /* Configure DMA channel */ + ret = dmaengine_slave_config(chan, &dma_config); + if (ret < 0) { + dev_err(dcmi->dev, "%s: DMA channel config failed (%d)\n", + __func__, ret); + goto err_dma_slave_config; + } + spin_lock_init(&dcmi->irqlock); mutex_init(&dcmi->lock); mutex_init(&dcmi->dma_lock); @@ -2072,6 +2069,7 @@ static int dcmi_probe(struct platform_device *pdev) v4l2_device_unregister(&dcmi->v4l2_dev); err_media_device_cleanup: media_device_cleanup(&dcmi->mdev); +err_dma_slave_config: dma_release_channel(dcmi->dma_chan);

return ret;

Rework of the spin_lock calls in preparation of the rework of the data handling of the driver. Keep it straight forward with basically spin_lock protection around everything except dmaengine calls that might sleep (ex: synchronize / terminate)

Signed-off-by: Alain Volmat alain.volmat@foss.st.com --- drivers/media/platform/st/stm32/stm32-dcmi.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/drivers/media/platform/st/stm32/stm32-dcmi.c b/drivers/media/platform/st/stm32/stm32-dcmi.c index 20f5b9ab6a1c..2fec10d13913 100644 --- a/drivers/media/platform/st/stm32/stm32-dcmi.c +++ b/drivers/media/platform/st/stm32/stm32-dcmi.c @@ -227,25 +227,18 @@ static int dcmi_restart_capture(struct stm32_dcmi *dcmi) { struct dcmi_buf *buf;

- spin_lock_irq(&dcmi->irqlock); - - if (dcmi->state != RUNNING) { - spin_unlock_irq(&dcmi->irqlock); + if (dcmi->state != RUNNING) return -EINVAL; - }

/* Restart a new DMA transfer with next buffer */ if (list_empty(&dcmi->buffers)) { dev_dbg(dcmi->dev, "Capture restart is deferred to next buffer queueing\n"); dcmi->state = WAIT_FOR_BUFFER; - spin_unlock_irq(&dcmi->irqlock); return 0; } buf = list_entry(dcmi->buffers.next, struct dcmi_buf, list); dcmi->active = buf;

- spin_unlock_irq(&dcmi->irqlock); - return dcmi_start_capture(dcmi, buf); }

@@ -370,8 +363,10 @@ static void dcmi_process_jpeg(struct stm32_dcmi *dcmi) * buffer payload. */

+ spin_unlock_irq(&dcmi->irqlock); /* Drain DMA */ dmaengine_synchronize(dcmi->dma_chan); + spin_lock_irq(&dcmi->irqlock);

/* Get DMA residue to get JPEG size */ status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); @@ -386,8 +381,10 @@ static void dcmi_process_jpeg(struct stm32_dcmi *dcmi) dcmi_buffer_done(dcmi, buf, 0, -EIO); }

+ spin_unlock_irq(&dcmi->irqlock); /* Abort DMA operation */ dmaengine_terminate_sync(dcmi->dma_chan); + spin_lock_irq(&dcmi->irqlock);

/* Restart capture */ if (dcmi_restart_capture(dcmi)) @@ -413,8 +410,10 @@ static irqreturn_t dcmi_irq_thread(int irq, void *arg) spin_unlock_irq(&dcmi->irqlock); dmaengine_terminate_sync(dcmi->dma_chan);

+ spin_lock_irq(&dcmi->irqlock); if (dcmi_restart_capture(dcmi)) dev_err(dcmi->dev, "%s: Cannot restart capture\n", __func__); + spin_unlock_irq(&dcmi->irqlock);

return IRQ_HANDLED; } @@ -424,8 +423,8 @@ static irqreturn_t dcmi_irq_thread(int irq, void *arg) if (dcmi->sd_format->fourcc == V4L2_PIX_FMT_JPEG && dcmi->misr & IT_FRAME) { /* JPEG received */ - spin_unlock_irq(&dcmi->irqlock); dcmi_process_jpeg(dcmi); + spin_unlock_irq(&dcmi->irqlock); return IRQ_HANDLED; }

@@ -599,11 +598,9 @@ static void dcmi_buf_queue(struct vb2_buffer *vb) dev_dbg(dcmi->dev, "Starting capture on buffer[%d] queued\n", buf->vb.vb2_buf.index);

- spin_unlock_irq(&dcmi->irqlock); if (dcmi_start_capture(dcmi, buf)) dev_err(dcmi->dev, "%s: Cannot restart capture on overflow or error\n", __func__); - return; }

spin_unlock_irq(&dcmi->irqlock); @@ -812,11 +809,11 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count)

dev_dbg(dcmi->dev, "Start streaming, starting capture\n");

- spin_unlock_irq(&dcmi->irqlock); ret = dcmi_start_capture(dcmi, buf); if (ret) { dev_err(dcmi->dev, "%s: Start streaming failed, cannot start capture\n", __func__); + spin_unlock_irq(&dcmi->irqlock); goto err_pipeline_stop; }

@@ -826,6 +823,8 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count) else reg_set(dcmi->regs, DCMI_IER, IT_OVR | IT_ERR);

+ spin_unlock_irq(&dcmi->irqlock); + return 0;

err_pipeline_stop:

Add possibility to rely on an additional MDMA channel and chain the DMA and MDMA channels allowing to achieve faster capture. Indeed, on the MP15 platform, the MDMA engine has an higher bandwidth to the DDR than the DMA engine. Relying on that it is possible to capture frames from the DCMI IP into the DDR by using two channels as follow:

DCMI -> (DMA) -> SRAM -> (MDMA) -> DDR

The DMA is able by himself to trigger a MDMA request hence, once properly configured, the DCMI IP can simply trigger the DMA in order to have the data pushed up to the DDR (via the SRAM and a MDMA channel).

This behavior is detailed in the document Documentation/arch/arm/stm32/stm32-dma-mdma-chaining.rst

Signed-off-by: Alain Volmat alain.volmat@foss.st.com --- drivers/media/platform/st/stm32/stm32-dcmi.c | 250 +++++++++++++++++++++++---- 1 file changed, 220 insertions(+), 30 deletions(-)

diff --git a/drivers/media/platform/st/stm32/stm32-dcmi.c b/drivers/media/platform/st/stm32/stm32-dcmi.c index 97683daf179d..e5663fbe6422 100644 --- a/drivers/media/platform/st/stm32/stm32-dcmi.c +++ b/drivers/media/platform/st/stm32/stm32-dcmi.c @@ -15,6 +15,7 @@ #include <linux/completion.h> #include <linux/delay.h> #include <linux/dmaengine.h> +#include <linux/genalloc.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/kernel.h> @@ -113,7 +114,9 @@ struct dcmi_buf { struct vb2_v4l2_buffer vb; bool prepared; struct sg_table sgt; + struct sg_table sgt_mdma; struct dma_async_tx_descriptor *dma_desc; + struct dma_async_tx_descriptor *mdma_desc; size_t size; struct list_head list; }; @@ -159,6 +162,15 @@ struct stm32_dcmi { struct dma_chan *dma_chan; dma_cookie_t dma_cookie; u32 dma_max_burst; + + /* Elements for the MDMA - DMA chaining */ + struct gen_pool *sram_pool; + struct dma_chan *mdma_chan; + void *sram_buf; + u32 sram_buf_size; + dma_addr_t sram_dma_buf; + dma_cookie_t mdma_cookie; + u32 misr; int errors_count; int overrun_count; @@ -247,12 +259,22 @@ static int dcmi_start_dma(struct stm32_dcmi *dcmi, struct dcmi_buf *buf) { /* Push current DMA transaction in the pending queue */ + if (dcmi->mdma_chan) { + dcmi->mdma_cookie = dmaengine_submit(buf->mdma_desc); + if (dma_submit_error(dcmi->mdma_cookie)) { + dev_err(dcmi->dev, "%s: MDMA submission failed\n", __func__); + return -ENXIO; + } + } + dcmi->dma_cookie = dmaengine_submit(buf->dma_desc); if (dma_submit_error(dcmi->dma_cookie)) { dev_err(dcmi->dev, "%s: DMA submission failed\n", __func__); return -ENXIO; }

+ if (dcmi->mdma_chan) + dma_async_issue_pending(dcmi->mdma_chan); dma_async_issue_pending(dcmi->dma_chan);

return 0; @@ -301,7 +323,9 @@ static void dcmi_set_crop(struct stm32_dcmi *dcmi)

static void dcmi_process_frame(struct stm32_dcmi *dcmi) { - struct dma_tx_state state; + struct dma_tx_state state, state_dma; + size_t bytes_used; + enum dma_status status; struct dcmi_buf *buf = dcmi->active;

@@ -309,23 +333,36 @@ static void dcmi_process_frame(struct stm32_dcmi *dcmi) return;

/* - * At the time FRAME interrupt is received, all dma req have been sent to the DMA, - * however DMA might still be transferring data hence first synchronize prior to - * getting the status of the DMA transfer. - * Then DMA tx status gives the amount of data transferred to memory, which is then - * returned to V4L2 through the active buffer payload. + * Pause the DMA transfer, leading to trigger of the MDMA channel read while + * keeping a valid residue value on the dma channel */ + if (dcmi->mdma_chan) { + spin_unlock_irq(&dcmi->irqlock); + dmaengine_pause(dcmi->dma_chan); + spin_lock_irq(&dcmi->irqlock); + + do { + status = dmaengine_tx_status(dcmi->mdma_chan, dcmi->mdma_cookie, &state); + cpu_relax(); + } while (status != DMA_ERROR && status != DMA_COMPLETE && + state.residue && state.in_flight_bytes); + } else { + status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); + }

- spin_unlock_irq(&dcmi->irqlock); - /* Drain DMA */ - dmaengine_synchronize(dcmi->dma_chan); - spin_lock_irq(&dcmi->irqlock); - - /* Get DMA status and residue size */ - status = dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state); if (status != DMA_ERROR && state.residue < buf->size) { + bytes_used = buf->size - state.residue; + + if (state.residue && dcmi->mdma_chan) { + dmaengine_tx_status(dcmi->dma_chan, dcmi->dma_cookie, &state_dma); + /* Getting full size residue equal to no residue */ + if (state_dma.residue == dcmi->sram_buf_size) + state_dma.residue = 0; + bytes_used -= state_dma.residue; + } + /* Return buffer to V4L2 with received data size */ - dcmi_buffer_done(dcmi, buf, buf->size - state.residue, 0); + dcmi_buffer_done(dcmi, buf, bytes_used, 0); } else { dcmi->errors_count++; dev_err(dcmi->dev, "%s: DMA error. status: 0x%x, residue: %d\n", @@ -336,6 +373,8 @@ static void dcmi_process_frame(struct stm32_dcmi *dcmi)

/* Abort DMA operation */ dmaengine_terminate_async(dcmi->dma_chan); + if (dcmi->mdma_chan) + dmaengine_terminate_async(dcmi->mdma_chan); }

static irqreturn_t dcmi_irq_thread(int irq, void *arg) @@ -354,13 +393,15 @@ static irqreturn_t dcmi_irq_thread(int irq, void *arg) dcmi->errors_count++;

dmaengine_terminate_async(dcmi->dma_chan); + if (dcmi->mdma_chan) + dmaengine_terminate_async(dcmi->mdma_chan);

if (dcmi_restart_capture(dcmi)) dev_err(dcmi->dev, "%s: Cannot restart capture\n", __func__); spin_unlock_irq(&dcmi->irqlock); - return IRQ_HANDLED; } + if (dcmi->misr & IT_ERR) dcmi->errors_count++;

@@ -447,28 +488,70 @@ static int dcmi_buf_prepare(struct vb2_buffer *vb) vb2_set_plane_payload(vb, 0, size);

if (!buf->prepared) { + u32 max_size = dcmi->dma_max_burst; + unsigned int dma_nents; + /* Get memory addresses */ buf->size = vb2_plane_size(&buf->vb.vb2_buf, 0); - if (buf->size > dcmi->dma_max_burst) - num_sgs = DIV_ROUND_UP(buf->size, dcmi->dma_max_burst); + if (dcmi->mdma_chan) + max_size = dcmi->sram_buf_size / 2;

- ret = sg_alloc_table(&buf->sgt, num_sgs, GFP_ATOMIC); + if (buf->size > max_size) + num_sgs = DIV_ROUND_UP(buf->size, max_size); + + /* + * If we use MDMA chaining, DMA is used in cyclic mode and the scatterlist + * maximum size is thus 2 + */ + dma_nents = num_sgs; + if (dcmi->mdma_chan) + dma_nents = min_t(unsigned int, num_sgs, 2); + + ret = sg_alloc_table(&buf->sgt, dma_nents, GFP_ATOMIC); if (ret) { - dev_err(dcmi->dev, "sg table alloc failed\n"); + dev_err(dcmi->dev, "sg table alloc failed for DMA\n"); return ret; }

+ if (dcmi->mdma_chan) { + ret = sg_alloc_table(&buf->sgt_mdma, num_sgs, GFP_ATOMIC); + if (ret) { + dev_err(dcmi->dev, "sg table alloc failed for MDMA\n"); + return ret; + } + } + dma_buf = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);

dev_dbg(dcmi->dev, "buffer[%d] phy=%pad size=%zu\n", vb->index, &dma_buf, buf->size);

- for_each_sg(buf->sgt.sgl, sg, num_sgs, i) { - size_t bytes = min_t(size_t, size, dcmi->dma_max_burst); + for_each_sg(buf->sgt.sgl, sg, dma_nents, i) { + size_t bytes = min_t(size_t, size, max_size); + + if (!dcmi->mdma_chan) { + sg_dma_address(sg) = dma_buf; + dma_buf += bytes; + } else { + /* Targets the beginning = first half of the sram_buf */ + sg_dma_address(sg) = dcmi->sram_dma_buf; + /* + * Targets the second half of the sram_bubf + * for odd indexes of the item of the sg_list + */ + if (i & 1) + sg->dma_address += (dcmi->sram_buf_size / 2); + } + /* + * In case of DMA-MDMA chaining, since the DMA is working in cyclic mode, + * we need to provide two linked-list node of same size in order to have + * a correct residue value computed. + */ + if (!dcmi->mdma_chan) + sg_dma_len(sg) = bytes; + else + sg_dma_len(sg) = dcmi->sram_buf_size / 2;

- sg_dma_address(sg) = dma_buf; - sg_dma_len(sg) = bytes; - dma_buf += bytes; size -= bytes; }

@@ -480,6 +563,8 @@ static int dcmi_buf_prepare(struct vb2_buffer *vb) DMA_PREP_INTERRUPT); if (!buf->dma_desc) { dev_err(dcmi->dev, "%s: DMA dmaengine_prep_slave_sg failed\n", __func__); + if (dcmi->mdma_chan) + sg_free_table(&buf->sgt_mdma); sg_free_table(&buf->sgt); return -EIO; } @@ -489,10 +574,48 @@ static int dcmi_buf_prepare(struct vb2_buffer *vb) if (ret) { dev_err(dcmi->dev, "%s: DMA dmaengine_desc_set_reuse failed\n", __func__); dmaengine_desc_free(buf->dma_desc); + if (dcmi->mdma_chan) + sg_free_table(&buf->sgt_mdma); sg_free_table(&buf->sgt); return -EIO; }

+ if (dcmi->mdma_chan) { + size = dcmi->fmt.fmt.pix.sizeimage; + for_each_sg(buf->sgt_mdma.sgl, sg, num_sgs, i) { + size_t bytes = min_t(size_t, size, max_size); + + sg_dma_address(sg) = dma_buf; + sg_dma_len(sg) = bytes; + dma_buf += bytes; + size -= bytes; + } + + buf->mdma_desc = dmaengine_prep_slave_sg(dcmi->mdma_chan, buf->sgt_mdma.sgl, + buf->sgt_mdma.nents, + DMA_DEV_TO_MEM, + DMA_PREP_INTERRUPT); + if (!buf->mdma_desc) { + dev_err(dcmi->dev, "%s: failed dmaengine_prep_slave_sg for MDMA\n", + __func__); + dmaengine_desc_free(buf->dma_desc); + sg_free_table(&buf->sgt_mdma); + sg_free_table(&buf->sgt); + return -EIO; + } + + ret = dmaengine_desc_set_reuse(buf->mdma_desc); + if (ret) { + dev_err(dcmi->dev, "%s: failed to set reuse for mdma desc\n", + __func__); + dmaengine_desc_free(buf->mdma_desc); + dmaengine_desc_free(buf->dma_desc); + sg_free_table(&buf->sgt_mdma); + sg_free_table(&buf->sgt); + return -EIO; + } + } + buf->prepared = true;

vb2_set_plane_payload(&buf->vb.vb2_buf, 0, buf->size); @@ -511,6 +634,14 @@ static void dcmi_buf_cleanup(struct vb2_buffer *vb) if (!buf->prepared) return;

+ if (dcmi->mdma_chan) { + ret = dmaengine_desc_free(buf->mdma_desc); + if (ret) + dev_err(dcmi->dev, "%s: Failed to free the mdma descriptor (0x%x)\n", + __func__, ret); + sg_free_table(&buf->sgt_mdma); + } + ret = dmaengine_desc_free(buf->dma_desc); if (ret) dev_err(dcmi->dev, "%s: Failed to free the mdma descriptor (0x%x)\n", @@ -816,6 +947,8 @@ static void dcmi_stop_streaming(struct vb2_queue *vq)

/* Stop all pending DMA operations */ dmaengine_terminate_sync(dcmi->dma_chan); + if (dcmi->mdma_chan) + dmaengine_terminate_sync(dcmi->mdma_chan);

pm_runtime_put(dcmi->dev);

@@ -1824,9 +1957,9 @@ static int dcmi_probe(struct platform_device *pdev) struct v4l2_fwnode_endpoint ep = { .bus_type = 0 }; struct stm32_dcmi *dcmi; struct vb2_queue *q; - struct dma_chan *chan; + struct dma_chan *chan, *mdma_chan; struct dma_slave_caps caps; - struct dma_slave_config dma_config; + struct dma_slave_config dma_config, mdma_config; struct clk *mclk; int ret = 0;

@@ -1888,15 +2021,21 @@ static int dcmi_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(chan), "Failed to request DMA channel\n");

- dcmi->dma_max_burst = UINT_MAX; - ret = dma_get_slave_caps(chan, &caps); - if (!ret && caps.max_sg_burst) - dcmi->dma_max_burst = caps.max_sg_burst * DMA_SLAVE_BUSWIDTH_4_BYTES; + mdma_chan = dma_request_chan(&pdev->dev, "mdma_tx"); + if (IS_ERR(mdma_chan)) { + ret = PTR_ERR(mdma_chan); + if (ret != -ENODEV) + return dev_err_probe(&pdev->dev, ret, "Failed to request MDMA channel\n"); + mdma_chan = NULL; + }

+ /* Configure the DMA channel */ memset(&dma_config, 0, sizeof(dma_config));

dma_config.src_addr = (dma_addr_t)dcmi->res->start + DCMI_DR; dma_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + if (mdma_chan) + dma_config.peripheral_size = 1; /* Indicates chaining */

/* Configure DMA channel */ ret = dmaengine_slave_config(chan, &dma_config); @@ -1906,6 +2045,47 @@ static int dcmi_probe(struct platform_device *pdev) goto err_dma_slave_config; }

+ /* If we want MDMA, we also need a sram pool */ + if (mdma_chan) { + dcmi->sram_pool = of_gen_pool_get(pdev->dev.of_node, "sram", 0); + if (!dcmi->sram_pool) { + dev_info(&pdev->dev, "No SRAM pool, can't use MDMA chaining\n"); + goto err_dma_slave_config; + } + + dev_info(&pdev->dev, "SRAM pool: %zu KiB for DMA/MDMA chaining\n", + gen_pool_size(dcmi->sram_pool) / 1024); + + dcmi->sram_buf_size = gen_pool_size(dcmi->sram_pool); + dcmi->sram_buf = gen_pool_dma_zalloc(dcmi->sram_pool, dcmi->sram_buf_size, + &dcmi->sram_dma_buf); + if (!dcmi->sram_buf) { + dev_err(dcmi->dev, "Failed to allocate from SRAM\n"); + goto err_dma_slave_config; + } + + /* Configure the MDMA Channel */ + memset(&mdma_config, 0, sizeof(mdma_config)); + mdma_config.direction = DMA_DEV_TO_MEM; + mdma_config.src_addr = dcmi->sram_dma_buf; + mdma_config.peripheral_size = dma_config.peripheral_size; + mdma_config.peripheral_config = dma_config.peripheral_config; + ret = dmaengine_slave_config(mdma_chan, &mdma_config); + if (ret < 0) { + dev_err(dcmi->dev, "%s: MDMA channel config failed (%d)\n", + __func__, ret); + goto err_mdma_slave_config; + } + } + + dcmi->dma_max_burst = UINT_MAX; + /* In case of using DMA-MDMA chaining we consider the maximum infini */ + if (!mdma_chan) { + ret = dma_get_slave_caps(chan, &caps); + if (!ret && caps.max_sg_burst) + dcmi->dma_max_burst = caps.max_sg_burst * DMA_SLAVE_BUSWIDTH_4_BYTES; + } + spin_lock_init(&dcmi->irqlock); mutex_init(&dcmi->lock); init_completion(&dcmi->complete); @@ -1915,6 +2095,7 @@ static int dcmi_probe(struct platform_device *pdev) dcmi->mclk = mclk; dcmi->state = STOPPED; dcmi->dma_chan = chan; + dcmi->mdma_chan = mdma_chan;

q = &dcmi->queue;

@@ -2023,8 +2204,13 @@ static int dcmi_probe(struct platform_device *pdev) v4l2_device_unregister(&dcmi->v4l2_dev); err_media_device_cleanup: media_device_cleanup(&dcmi->mdev); +err_mdma_slave_config: + if (dcmi->mdma_chan) + gen_pool_free(dcmi->sram_pool, (unsigned long)dcmi->sram_buf, dcmi->sram_buf_size); err_dma_slave_config: dma_release_channel(dcmi->dma_chan); + if (dcmi->mdma_chan) + dma_release_channel(mdma_chan);

return ret; } @@ -2042,6 +2228,10 @@ static void dcmi_remove(struct platform_device *pdev) media_device_cleanup(&dcmi->mdev);

dma_release_channel(dcmi->dma_chan); + if (dcmi->mdma_chan) { + gen_pool_free(dcmi->sram_pool, (unsigned long)dcmi->sram_buf, dcmi->sram_buf_size); + dma_release_channel(dcmi->mdma_chan); + } }

static int dcmi_runtime_suspend(struct device *dev)