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FYI: misc: visconti: Toshiba Visconti Pyramid accelerator driver sample

by Yuji Ishikawa

Hi Odded This is a sample (wip) driver for a Pyramid accelerator found on Toshiba Visconti SoC. This accelerator accepts a image (and table for scaling filter), then yields 4 differently scaled output images at a time. Therefore (image-in, image-out), they say this driver should be classified to media driver category. Actually, it is not easy to adapt it to v4l2 framework, because the supported image format is different from ones commonly used in V4L2 drivers. There're almost no hint for handling planar RGB images nor handling multiple images with different resolution. I hope this post (as well as DSPIF posted last week) will help your case-study. Regards Yuji Ishikawa ==== misc: visconti: Add Toshiba Visconti Pyramid image processing accelerator Add support to Pyramid image processing accelerator on Toshiba Visconti ARM SoCs. The accelerator takes an image and yields up to 4 resized images with different parameter. Input / Output images can be either color / grayscale images. The color channel format of the color image is planar-format (a plane for each color), unlike interleaved format which is often seen in V4L2 RGB pixel format. The visconti5 SoC has 1 unit of the accelerator. Scaling (shrink) ratio can be x1 - x1/4. Userland can provide the coefficients of window functions as well as using equipped linear filter. The imprementation has two C sources: * pyramid.c The user interface layer. It receives resize task description from userland library, manages lifecycle of DMA-BUF instances holding images, manages interrupt requests and updates device file status. Memory blocks are specified with fds + offsets of DMA-BUF instances. * hwd_pyramid.c The hardware layer. It configures hardware registers following a request from pyramid.c This layer writes configuration to hardware registers (with 32bit word access), then kicks the hardware. Memory blocks are specified with 32bit-truncated phisical address. Future plan: * power management operations will be added, once the visconti clock framework driver supports the Pyramid hardware. * When the Visconti IOMMU driver (currently under review) is accepted, the hardware layer will use 32bit IO virtual address mapped by the dedicated IOMMU. dt-bindings: soc: visconti: Add Toshiba Visconti PYRAMID image processing accelerator bindings This commit adds the Device Tree binding documentation that allows to describe the PYRAMID image processing accelerator found in Toshiba Visconti SoCs. Signed-off-by: Yuji Ishikawa <yuji2.ishikawa(a)toshiba.co.jp> --- .../visconti/toshiba,visconti-pyramid.yaml | 52 ++ drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/visconti/Kconfig | 8 + drivers/misc/visconti/Makefile | 6 + drivers/misc/visconti/pyramid/Makefile | 8 + drivers/misc/visconti/pyramid/hwd_pyramid.c | 334 +++++++++++ drivers/misc/visconti/pyramid/hwd_pyramid.h | 129 +++++ drivers/misc/visconti/pyramid/pyramid.c | 532 ++++++++++++++++++ include/uapi/linux/visconti-ipa.h | 87 +++ include/uapi/linux/visconti-pyramid.h | 120 ++++ 11 files changed, 1278 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/visconti/toshiba,visconti-pyramid.yaml create mode 100644 drivers/misc/visconti/Kconfig create mode 100644 drivers/misc/visconti/Makefile create mode 100644 drivers/misc/visconti/pyramid/Makefile create mode 100644 drivers/misc/visconti/pyramid/hwd_pyramid.c create mode 100644 drivers/misc/visconti/pyramid/hwd_pyramid.h create mode 100644 drivers/misc/visconti/pyramid/pyramid.c create mode 100644 include/uapi/linux/visconti-ipa.h create mode 100644 include/uapi/linux/visconti-pyramid.h diff --git a/Documentation/devicetree/bindings/misc/visconti/toshiba,visconti-pyramid.yaml b/Documentation/devicetree/bindings/misc/visconti/toshiba,visconti-pyramid.yaml new file mode 100644 index 000000000..be0168a6a --- /dev/null +++ b/Documentation/devicetree/bindings/misc/visconti/toshiba,visconti-pyramid.yaml @@ -0,0 +1,52 @@ +# SPDX-LIcense-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/visconti/toshiba,visconti-pyramid.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti PYRAMID image processing accelerator + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu(a)toshiba.co.jp> + +description: | + Toshiba Visconti PYRAMID image processing accelerator accepts a picture with up to 3 planes + and yields up to 4 pictures with different scaling parameters. + +properties: + compatible: + items: + - const: toshiba,visconti-pyramid + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + index: + const: 0 + +required: + - compatible + - reg + - interrupts + - index + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + pyramid0: pyramid@14160000 { + compatible = "toshiba,visconti-pyramid"; + reg = <0 0x14160000 0 0x2000>; + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; + index = <0>; + }; + }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0f5a49fc7..4da73fd4c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -487,4 +487,5 @@ source "drivers/misc/cardreader/Kconfig" source "drivers/misc/habanalabs/Kconfig" source "drivers/misc/uacce/Kconfig" source "drivers/misc/pvpanic/Kconfig" +source "drivers/misc/visconti/Kconfig" endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index a086197af..946c6f961 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_UACCE) += uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o +obj-$(CONFIG_ARCH_VISCONTI) += visconti/ diff --git a/drivers/misc/visconti/Kconfig b/drivers/misc/visconti/Kconfig new file mode 100644 index 000000000..ed5a45552 --- /dev/null +++ b/drivers/misc/visconti/Kconfig @@ -0,0 +1,8 @@ +if ARCH_VISCONTI + +config VISCONTI_PYRAMID + tristate "Visconti Pyramid driver" + help + This option enable support for the Toshiba Visconti Pyramid accelerator driver. + +endif diff --git a/drivers/misc/visconti/Makefile b/drivers/misc/visconti/Makefile new file mode 100644 index 000000000..6cdf5a28a --- /dev/null +++ b/drivers/misc/visconti/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Visconti specific device drivers. +# + +obj-$(CONFIG_VISCONTI_PYRAMID) += pyramid/ diff --git a/drivers/misc/visconti/pyramid/Makefile b/drivers/misc/visconti/pyramid/Makefile new file mode 100644 index 000000000..46aac8ce6 --- /dev/null +++ b/drivers/misc/visconti/pyramid/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Visconti PYRAMID driver +# + +visconti-pyramid-objs = pyramid.o hwd_pyramid.o + +obj-$(CONFIG_VISCONTI_PYRAMID) += visconti-pyramid.o diff --git a/drivers/misc/visconti/pyramid/hwd_pyramid.c b/drivers/misc/visconti/pyramid/hwd_pyramid.c new file mode 100644 index 000000000..421448975 --- /dev/null +++ b/drivers/misc/visconti/pyramid/hwd_pyramid.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +/* Toshiba Visconti Affine Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/types.h> + +#include "hwd_pyramid.h" + +/* REGISTER DEFINITIONS */ +#define PYM_CFG 0x001C +#define PYM_INT_MASK 0x0020 +#define PYM_R_ENABLE 0x0030 +#define PYM_W_ENABLE 0x0034 +#define PYM_T_ENABLE 0x0038 +#define PYM_T00_CFG 0x0040 +#define PYM_T00_SRAM_BASE 0x0044 +#define PYM_T00_SRAM_SIZE 0x0048 +/* table transfer: tt 00 - 15 */ +#define PYM_DMAC_TTT_BASE(tt) (0x0100 + 0x08 * (tt)) +#define PYM_DMAC_TTT_STADR(tt) (PYM_DMAC_TTT_BASE(tt)) +#define PYM_DMAC_TTT_SIZE(tt) (PYM_DMAC_TTT_BASE(tt) + 0x04) +/* read image: rr 00 - 02 */ +#define PYM_DMAC_RRR_BASE(rr) (0x200 + 0x40 * (rr)) +#define PYM_DMAC_RRR_STADR(rr) (PYM_DMAC_RRR_BASE(rr)) +#define PYM_DMAC_RRR_ENDADR(rr) (PYM_DMAC_RRR_BASE(rr) + 0x04) +#define PYM_DMAC_RRR_HEIGHT(rr) (PYM_DMAC_RRR_BASE(rr) + 0x08) +#define PYM_DMAC_RRR_PITCH(rr) (PYM_DMAC_RRR_BASE(rr) + 0x0C) +#define PYM_DMAC_RRR_CFG0(rr) (PYM_DMAC_RRR_BASE(rr) + 0x10) +#define PYM_DMAC_RRR_SRAM_BASE(rr) (PYM_DMAC_RRR_BASE(rr) + 0x18) +#define PYM_DMAC_RRR_SRAM_SIZE(rr) (PYM_DMAC_RRR_BASE(rr) + 0x1C) +/* write image: ww 00 - 11 */ +#define PYM_DMAC_WWW_BASE(ww) (0x300 + 0x40 * (ww)) +#define PYM_DMAC_WWW_STADR(ww) (PYM_DMAC_WWW_BASE(ww)) +#define PYM_DMAC_WWW_ENDADR(ww) (PYM_DMAC_WWW_BASE(ww) + 0x04) +#define PYM_DMAC_WWW_HEIGHT(ww) (PYM_DMAC_WWW_BASE(ww) + 0x08) +#define PYM_DMAC_WWW_PITCH(ww) (PYM_DMAC_WWW_BASE(ww) + 0x0C) +#define PYM_DMAC_WWW_CFG0(ww) (PYM_DMAC_WWW_BASE(ww) + 0x10) +#define PYM_DMAC_WWW_SRAM_BASE(ww) (PYM_DMAC_WWW_BASE(ww) + 0x18) +#define PYM_DMAC_WWW_SRAM_SIZE(ww) (PYM_DMAC_WWW_BASE(ww) + 0x1C) +#define PYM_INT_STATUS 0x0E04 + +#define PYM_RSCALER_CS_START 0x1000 +#define PYM_RSCALER_CS_MODE1 0x1008 +#define PYM_RSCALER_CS_MODE2 0x100C +#define PYM_RSCALER_SIZE_IN_Y 0x1010 +#define PYM_RSCALER_SIZE_IN_C 0x1014 +#define PYM_RSCALER_SIZE_OUT_Y(id) (0x1018 + 0x08 * (id)) +#define PYM_RSCALER_SIZE_OUT_C(id) (0x101C + 0x08 * (id)) +#define PYM_RSCALER_OAINSET 0x1040 +#define PYM_RSCALER_OAINSET_M 0x1044 +#define PYM_RSCALER_OAOUTSET(id) (0x1050 + 0x04 * (id)) +#define PYM_RSCALER_OAOUTSET_M(id) (0x1060 + 0x04 * (id)) +/* scaler route registers id 0-3, ch YH=0, YV, CH, CV=3 */ +#define PYM_RSCALER_XX_BASE(id, ch) (0x1080 + 0x80 * (id) + 0x20 * (ch)) +#define PYM_RSCALER_XX_FILMODE(ch) (PYM_RSCALER_XX_BASE((0), (ch))) +#define PYM_RSCALER_XX_FILPSMODE(ch) (PYM_RSCALER_XX_BASE((0), (ch)) + 0x04) +#define PYM_RSCALER_XX_POS(ch) (PYM_RSCALER_XX_BASE((0), (ch)) + 0x08) +#define PYM_RSCALER_XX_FILBASE(id, ch) (PYM_RSCALER_XX_BASE((id), (ch)) + 0x0C) +#define PYM_RSCALER_XX_OAOUTSET(id, ch) (PYM_RSCALER_XX_BASE((id), (ch)) + 0x10) + +#define HWD_PYRAMID_Y (0U) +#define HWD_PYRAMID_CB (1U) +#define HWD_PYRAMID_DMAC_T00_SRAM_BASE (0U) +#define HWD_PYRAMID_COEF_SIZE (0x40U) +#define HWD_PYRAMID_REGISTER_START (1U) +#define HWD_PYRAMID_REGISTER_IN_C_SIZE_NULL (0U) +#define HWD_PYRAMID_REGISTER_OUT_C_SIZE_NULL (0U) +#define HWD_PYRAMID_MAX_SCALER_NUM (4U) +#define HWD_PYRAMID_REGISTER_DUMMY_PITCH (2U) +#define HWD_PYRAMID_REGISTER_INT_DONE BIT(0) +#define HWD_PYRAMID_REG_CLEAR_INT BIT(0) +#define HWD_PYRAMID_FIXED_R_CFG_VALUE (0x00070701U) +#define HWD_PYRAMID_FIXED_T00_CFG_VALUE (0x00000210U) + +/** + * struct hwd_pyramid_resources - HWD driver internal resource structure + * + * @base: hardware register base address + * @clk_id: clock_id + */ +struct hwd_pyramid_resources { + void __iomem *base; +}; + +/* HWD driver internal resource */ +static struct hwd_pyramid_resources hwd_pyramid_resources[HWD_PYRAMID_DEVICE_MAX] = {}; + +/** + * hwd_pyramid_reset() - Reset Pyramid accelerator + * + * @index: Index of Pyramid accelerator + * Reset the specified pyramid module + */ +static void hwd_pyramid_reset(u32 index) +{ + const struct hwd_pyramid_resources *res = &hwd_pyramid_resources[index]; + void __iomem *base = res->base; + + /* setting fixed value */ + writel(HWD_PYRAMID_FIXED_R_CFG_VALUE, base + PYM_CFG); + writel(HWD_PYRAMID_FIXED_T00_CFG_VALUE, base + PYM_T00_CFG); + writel(HWD_PYRAMID_DMAC_T00_SRAM_BASE, base + PYM_T00_SRAM_BASE); +} + +/** + * hwd_pyramid_config_rvdmac() - Configure RVDMAC settings of PYRAMID to the registers + * + * @base: hardware register base address + * @desc: Pointer to descriptor structure + */ +static void hwd_pyramid_config_rvdmac(void __iomem *base, const struct hwd_pyramid_descriptor *desc) +{ + u32 r_enable, t_enable, w_enable; + u32 scaler; + u32 color; + u32 i; + + /* loading TAP settings */ + t_enable = FIELD_GET(BIT(16), desc->port_enable); + writel(t_enable, base + PYM_T_ENABLE); + writel(desc->t00_sram_size, base + PYM_T00_SRAM_SIZE); + for (i = 0; i < HWD_PYRAMID_TAP_ELEMENT; i++) { + if (desc->tap_addr[i] != 0U) + writel(HWD_PYRAMID_COEF_SIZE, base + PYM_DMAC_TTT_SIZE(i)); + else + writel(0U, base + PYM_DMAC_TTT_SIZE(i)); + writel(desc->tap_addr[i] & GENMASK(31, 0), base + PYM_DMAC_TTT_STADR(i)); + } + + /* loading read port settings */ + r_enable = FIELD_GET(GENMASK(15, 13), desc->port_enable); + writel(r_enable, base + PYM_R_ENABLE); + for (i = 0; i < HWD_PYRAMID_DMA_READ_PORT; i++) { + writel((u32)(desc->r_stadr[i] & GENMASK(31, 0)), base + PYM_DMAC_RRR_STADR(i)); + writel((u32)(desc->r_endadr[i] & GENMASK(31, 0)), base + PYM_DMAC_RRR_ENDADR(i)); + writel(desc->r_dmac_height[i], base + PYM_DMAC_RRR_HEIGHT(i)); + if (desc->r_stadr[i] != 0U) { + if (i == HWD_PYRAMID_Y) + writel(desc->r_y_pitch, base + PYM_DMAC_RRR_PITCH(i)); + else + writel(desc->r_c_pitch, base + PYM_DMAC_RRR_PITCH(i)); + } else { + writel(HWD_PYRAMID_REGISTER_DUMMY_PITCH, base + PYM_DMAC_RRR_PITCH(i)); + } + + writel(desc->r_sram_base[i], base + PYM_DMAC_RRR_SRAM_BASE(i)); + writel(desc->r_sram_size[i], base + PYM_DMAC_RRR_SRAM_SIZE(i)); + } + writel(desc->r_cfg0, base + PYM_DMAC_RRR_CFG0(0)); + + /* loading write port settings */ + w_enable = desc->port_enable & GENMASK(11, 0); + writel(w_enable, base + PYM_W_ENABLE); + for (i = 0; i < HWD_PYRAMID_DMA_WRITE_PORT; i++) { + scaler = i % HWD_PYRAMID_MAX_SCALER_NUM; + color = i / HWD_PYRAMID_MAX_SCALER_NUM; + writel((u32)(desc->w_stadr[i] & GENMASK(31, 0)), base + PYM_DMAC_WWW_STADR(i)); + writel((u32)(desc->w_endadr[i] & GENMASK(31, 0)), base + PYM_DMAC_WWW_ENDADR(i)); + writel(desc->w_dmac_height[i], base + PYM_DMAC_WWW_HEIGHT(i)); + if (desc->w_stadr[i] != 0U) { + if (color == HWD_PYRAMID_Y) { + writel(desc->w_cfg0[i], base + PYM_DMAC_WWW_CFG0(i)); + writel(desc->w_y_pitch[scaler], base + PYM_DMAC_WWW_PITCH(i)); + } else { + writel(desc->w_c_pitch[scaler], base + PYM_DMAC_WWW_PITCH(i)); + } + } else { + writel(HWD_PYRAMID_REGISTER_DUMMY_PITCH, base + PYM_DMAC_WWW_PITCH(i)); + } + writel(desc->w_sram_base[i], base + PYM_DMAC_WWW_SRAM_BASE(i)); + writel(desc->w_sram_size[i], base + PYM_DMAC_WWW_SRAM_SIZE(i)); + } +} + +/** + * hwd_pyramid_config_scaler() - Configure SCALER settings of PYRAMID to the registers + * + * @base: hardware register base address + * @desc: Pointer to descriptor structure + */ +static void hwd_pyramid_config_scaler(void __iomem *base, const struct hwd_pyramid_descriptor *desc) +{ + u32 scaler_sel; + u32 i; + + writel(desc->mode1, base + PYM_RSCALER_CS_MODE1); + writel(desc->mode2, base + PYM_RSCALER_CS_MODE2); + + /* set r_size */ + writel(desc->r_size, base + PYM_RSCALER_SIZE_IN_Y); + if (desc->r_stadr[HWD_PYRAMID_CB] == 0U) + writel(HWD_PYRAMID_REGISTER_IN_C_SIZE_NULL, base + PYM_RSCALER_SIZE_IN_C); + else + writel(desc->r_size, base + PYM_RSCALER_SIZE_IN_C); + + /* set out_size */ + for (scaler_sel = 0; scaler_sel < HWD_PYRAMID_SCALER_ROUTE; scaler_sel++) { + writel(desc->w_size[scaler_sel], base + PYM_RSCALER_SIZE_OUT_Y(scaler_sel)); + if (desc->w_stadr[scaler_sel + HWD_PYRAMID_SCALER_ROUTE] == 0U) { + writel(HWD_PYRAMID_REGISTER_OUT_C_SIZE_NULL, + base + PYM_RSCALER_SIZE_OUT_C(scaler_sel)); + } else { + writel(desc->w_size[scaler_sel], base + PYM_RSCALER_SIZE_OUT_C(scaler_sel)); + } + } + + /* set boundary processing register */ + writel(desc->oainset, base + PYM_RSCALER_OAINSET); + writel(desc->oainset_m, base + PYM_RSCALER_OAINSET_M); + + /* set filter output fixed value embedded register */ + for (scaler_sel = 0; scaler_sel < HWD_PYRAMID_SCALER_ROUTE; scaler_sel++) { + writel(desc->oaoutset[scaler_sel], base + PYM_RSCALER_OAOUTSET(scaler_sel)); + writel(desc->oaoutset_m[scaler_sel], base + PYM_RSCALER_OAOUTSET_M(scaler_sel)); + writel(desc->h_oaoutset[scaler_sel], + base + PYM_RSCALER_XX_OAOUTSET(scaler_sel, HWD_PYRAMID_YH)); + writel(desc->v_oaoutset[scaler_sel], + base + PYM_RSCALER_XX_OAOUTSET(scaler_sel, HWD_PYRAMID_YV)); + } + + /* set common register */ + for (i = HWD_PYRAMID_YH; i <= HWD_PYRAMID_CV; i++) { + writel(desc->scl_filmode[i], base + PYM_RSCALER_XX_FILMODE(i)); + if (i == HWD_PYRAMID_YH || i == HWD_PYRAMID_CH) { + /* Y and C Horizontal Components */ + writel(desc->scl_h_crop_mode, base + PYM_RSCALER_XX_FILPSMODE(i)); + writel(desc->scl_h_crop_pos, base + PYM_RSCALER_XX_POS(i)); + } else { + /* Y and C Vertical Components */ + writel(desc->scl_v_crop_mode, base + PYM_RSCALER_XX_FILPSMODE(i)); + writel(desc->scl_v_crop_pos, base + PYM_RSCALER_XX_POS(i)); + } + } + + for (scaler_sel = 0; scaler_sel < HWD_PYRAMID_SCALER_ROUTE; scaler_sel++) { + writel(desc->width_ratio[scaler_sel], + base + PYM_RSCALER_XX_FILBASE(scaler_sel, HWD_PYRAMID_YH)); + writel(desc->width_ratio[scaler_sel], + base + PYM_RSCALER_XX_FILBASE(scaler_sel, HWD_PYRAMID_CH)); + writel(desc->height_ratio[scaler_sel], + base + PYM_RSCALER_XX_FILBASE(scaler_sel, HWD_PYRAMID_YV)); + writel(desc->height_ratio[scaler_sel], + base + PYM_RSCALER_XX_FILBASE(scaler_sel, HWD_PYRAMID_CV)); + } +} + +/** + * hwd_pyramid_initialize() - Initialize PYRAMID device + * + * @module_id: @ref hwd_pyramid_device "id" of the h/w module + * @vaddr: register base virtual address + * Return: 0 operation completed successfully + */ +void hwd_pyramid_initialize(u32 module_id, void __iomem *vaddr) +{ + struct hwd_pyramid_resources *res = &hwd_pyramid_resources[module_id]; + + res->base = vaddr; +} + +/** + * hwd_pyramid_uninitialize() - Uninitialize PYRAMID device + * + * @module_id: @ref hwd_pyramid_device "id" of the h/w module + */ +void hwd_pyramid_uninitialize(u32 module_id) +{ + struct hwd_pyramid_resources *res = &hwd_pyramid_resources[module_id]; + + res->base = NULL; +} + +/** + * hwd_pyramid_start() - Start PYRAMID device + * + * @module_id: @ref hwd_pyramid_device "id" of the h/w module + * @desc: Pointer to descriptor structure + */ +void hwd_pyramid_start(u32 module_id, const struct hwd_pyramid_descriptor *desc) +{ + const struct hwd_pyramid_resources *res = &hwd_pyramid_resources[module_id]; + void __iomem *base = res->base; + + hwd_pyramid_reset(module_id); + + /* Clear Interrupts */ + writel(HWD_PYRAMID_REG_CLEAR_INT, base + PYM_INT_STATUS); + + hwd_pyramid_config_rvdmac(base, desc); + hwd_pyramid_config_scaler(base, desc); + dsb(st); + + /* Kick Pyramid */ + writel(HWD_PYRAMID_REGISTER_START, base + PYM_RSCALER_CS_START); +} + +/** + * hwd_pyramid_stop() - Stop PYRAMID device. + * + * @module_id: @ref hwd_pyramid_device "id" of the h/w module + * + */ +void hwd_pyramid_stop(u32 module_id) +{ +} + +/** + * hwd_pyramid_irq_handler() - HWD PYRAMID interrupt handler + * + * @@param[in]: module_id @ref hwd_pyramid_device "id" of the h/w module + * Return: event @ref hwd_pyramid_events "event" returned by HWD irq handler + */ +u32 hwd_pyramid_irq_handler(u32 module_id) +{ + const struct hwd_pyramid_resources *res = &hwd_pyramid_resources[module_id]; + void __iomem *base = res->base; + u32 event = 0; + u32 cause; + + /* Read and Clear the interrupt causes */ + cause = readl(base + PYM_INT_STATUS); + writel(cause, base + PYM_INT_STATUS); + + if (FIELD_GET(HWD_PYRAMID_REGISTER_INT_DONE, cause)) + event |= HWD_PYRAMID_EVENT_DONE; + + return event; +} diff --git a/drivers/misc/visconti/pyramid/hwd_pyramid.h b/drivers/misc/visconti/pyramid/hwd_pyramid.h new file mode 100644 index 000000000..d4de67a41 --- /dev/null +++ b/drivers/misc/visconti/pyramid/hwd_pyramid.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* Toshiba Visconti Affine Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#ifndef HWD_PYRAMID_H +#define HWD_PYRAMID_H + +#include <linux/errno.h> +#include <linux/types.h> + +/** + * enum hwd_pyramid_module_id - ID for each PYRAMID device + */ +enum hwd_pyramid_module_id { HWD_PYRAMID_DEVICE_0 = 0, HWD_PYRAMID_DEVICE_MAX = 1 }; + +/** + * enum hwd_pyramid_component + * @HWD_PYRAMID_YH: Horizontal Y Component + * @HWD_PYRAMID_YV: Vertical Y Component + * @HWD_PYRAMID_CH: Horizontal C Component + * @HWD_PYRAMID_CV: Vertical C Component + * @HWD_PYRAMID_YCHV: Total [YC][HV] Combinations + */ +enum hwd_pyramid_component { + HWD_PYRAMID_YH = 0, + HWD_PYRAMID_YV = 1, + HWD_PYRAMID_CH = 2, + HWD_PYRAMID_CV = 3, + HWD_PYRAMID_YCHV = 4, +}; + +/* Process completed successfully */ +#define HWD_PYRAMID_EVENT_DONE (0x01U) + +#define HWD_PYRAMID_TAP_ELEMENT (16U) /**< YH1, YV1, CH1, CV1, YH2, ... , CV4 */ +#define HWD_PYRAMID_DMA_READ_PORT (3U) /**< Y, Cb, Cr */ +#define HWD_PYRAMID_DMA_WRITE_PORT (12U) /**< Y1, Y2, Y3, Y4, Cb1, Cb2, ... , Cr4 */ +#define HWD_PYRAMID_SCALER_ROUTE (4U) /**< Scaler 0-3 */ + +/** + * struct hwd_pyramid_descriptor - HWD PYRAMID Descriptor + * @port_enable: Read, Write and TAP Port enable/disable + * @t00_sram_size: Table Port 00 SRAM FIFO size + * @config_done: Status of the config APIs called + * @tap_addr: Table ID00 to 15 Transfer Start Address Register + * @r_stadr: Y, Cb, Cr data start address of input data + * @r_endadr: Y, Cb, Cr data end address of input data + * @r_size: Input width and height + * @mode2: Scaler mode setting register 2 + * @r_y_pitch: The lines pitch of y on input image + * @r_c_pitch: The lines pitch of y on input image + * @r_dmac_height: Number of line rectangle data + * @r_cfg0: Read port configuration register 0 + * @r_sram_base: Internal read port sram base address + * @r_sram_size: Internal read port sram size + * @w_stadr: Y, Cb, and Cr data address of Scaler0-3 + * @w_endadr: Y, Cb, and Cr data address of Scaler0-3 + * @w_size: Output width and height of Scaler0-3 + * @w_cfg0: Write port configuration register 0 + * @w_y_pitch: The lines pitch of y output image from Scaler0-3 + * @w_c_pitch: The lines pitch of c output image from Scaler0-3 + * @w_dmac_height: Number of line rectangle data + * @w_sram_base: Internal write port sram base address + * @w_sram_size: Internal write port sram size + * @mode1: Scaler mode setting register 1 + * @scl_filmode: Filter mode setting of Scaler (common to Scaler0-3) + * @oainset: Filter input effective pixel outside boundary processing + * @oainset_m: Filter input effective pixel outside boundary processing + * @oaoutset: Fixed data setting of filter output + * @oaoutset_m: Fixed data setting of filter output + * @scl_h_crop_mode: Cropping setting of horizontal (common to Scaler0-3) + * @scl_v_crop_mode: Cropping setting of vertical (common to Scaler0-3) + * @scl_h_crop_pos: Starting position of horizontal cropping(common to Scaler0-3) + * @scl_v_crop_pos: Starting position of vertical cropping(common to Scaler0-3) + * @width_ratio: Width reduction/expansion rate of Scaler0 to 3 + * @height_ratio: Height reduction/expansion rate of Scaler0 to 3 + * @h_oaoutset: Left and right position for fixed data setting of filter output + * @v_oaoutset: Upper and lower position for fixed data setting of filter output + */ +struct hwd_pyramid_descriptor { + u32 port_enable; + u16 t00_sram_size; + u16 config_done; + u32 tap_addr[HWD_PYRAMID_TAP_ELEMENT]; + u32 r_stadr[HWD_PYRAMID_DMA_READ_PORT]; + u32 r_endadr[HWD_PYRAMID_DMA_READ_PORT]; + u32 r_size; + u32 mode2; + u32 r_y_pitch; + u32 r_c_pitch; + u16 r_dmac_height[HWD_PYRAMID_DMA_READ_PORT]; + u16 r_cfg0; + u16 r_sram_base[HWD_PYRAMID_DMA_READ_PORT]; + u16 r_sram_size[HWD_PYRAMID_DMA_READ_PORT]; + u32 w_stadr[HWD_PYRAMID_DMA_WRITE_PORT]; + u32 w_endadr[HWD_PYRAMID_DMA_WRITE_PORT]; + u32 w_size[HWD_PYRAMID_SCALER_ROUTE]; + u16 w_cfg0[HWD_PYRAMID_DMA_WRITE_PORT]; + u32 w_y_pitch[HWD_PYRAMID_SCALER_ROUTE]; + u32 w_c_pitch[HWD_PYRAMID_SCALER_ROUTE]; + u16 w_dmac_height[HWD_PYRAMID_DMA_WRITE_PORT]; + u16 w_sram_base[HWD_PYRAMID_DMA_WRITE_PORT]; + u16 w_sram_size[HWD_PYRAMID_DMA_WRITE_PORT]; + u32 mode1; + u8 scl_filmode[HWD_PYRAMID_YCHV]; + u32 oainset; + u32 oainset_m; + u32 oaoutset[HWD_PYRAMID_SCALER_ROUTE]; + u32 oaoutset_m[HWD_PYRAMID_SCALER_ROUTE]; + u32 scl_h_crop_mode; + u32 scl_v_crop_mode; + u32 scl_h_crop_pos; + u32 scl_v_crop_pos; + u32 width_ratio[HWD_PYRAMID_SCALER_ROUTE]; + u32 height_ratio[HWD_PYRAMID_SCALER_ROUTE]; + u32 h_oaoutset[HWD_PYRAMID_SCALER_ROUTE]; + u32 v_oaoutset[HWD_PYRAMID_SCALER_ROUTE]; +}; + +void hwd_pyramid_initialize(u32 module_id, void __iomem *vaddr); +void hwd_pyramid_uninitialize(u32 module_id); +void hwd_pyramid_start(u32 module_id, const struct hwd_pyramid_descriptor *desc); +void hwd_pyramid_stop(u32 module_id); +u32 hwd_pyramid_irq_handler(u32 module_id); + +#endif /* HWD_PYRAMID_H */ diff --git a/drivers/misc/visconti/pyramid/pyramid.c b/drivers/misc/visconti/pyramid/pyramid.c new file mode 100644 index 000000000..11feb33e8 --- /dev/null +++ b/drivers/misc/visconti/pyramid/pyramid.c @@ -0,0 +1,532 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +/* Toshiba Visconti Affine Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/dma-buf.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/miscdevice.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/poll.h> +#include <linux/visconti-pyramid.h> +#include <linux/wait.h> + +#include "hwd_pyramid.h" + +#define DRV_PYRAMID_DUMMY_END_ADDR (0xFFFFFFFFU) + +#define IPA_POLL_EVENT_NONE (0) +#define IPA_POLL_EVENT_DONE (1) +#define IPA_POLL_EVENT_ERROR (2) +#define IPA_WAKEUP_RETRY_DELAY (300 * 1000) /*usec*/ + +int ipa_attach_dmabuf(struct device *dev, int fd, struct dma_buf_attachment **a, + struct sg_table **s, dma_addr_t *addr, enum dma_data_direction dma_dir) +{ + struct dma_buf_attachment *attachment; + struct dma_buf *dmabuf; + struct sg_table *sgt; + int ret; + + dmabuf = dma_buf_get(fd); + if (IS_ERR(dmabuf)) { + dev_err(dev, "Invalid dmabuf FD\n"); + return PTR_ERR(dmabuf); + } + attachment = dma_buf_attach(dmabuf, dev); + + if (IS_ERR(attachment)) { + dev_err(dev, "Failed to attach dmabuf\n"); + ret = PTR_ERR(attachment); + goto err_put; + } + sgt = dma_buf_map_attachment(attachment, dma_dir); + if (IS_ERR(sgt)) { + dev_err(dev, "Failed to get dmabufs sg_table\n"); + ret = PTR_ERR(sgt); + goto err_detach; + } + if (sgt->nents != 1) { + dev_err(dev, "Sparse DMA region is unsupported\n"); + ret = -EINVAL; + goto err_unmap; + } + + *addr = sg_dma_address(sgt->sgl); + *a = attachment; + *s = sgt; + + return 0; + +err_unmap: + dma_buf_unmap_attachment(attachment, sgt, dma_dir); +err_detach: + dma_buf_detach(dmabuf, attachment); +err_put: + dma_buf_put(dmabuf); + return ret; +} + +struct pyramid_priv { + struct device *dev; + struct miscdevice miscdev; + struct mutex lock; /* only 1 user context execute an API at a time */ + void __iomem *regs; + int irq; + wait_queue_head_t waitq; + enum drv_ipa_state status; + unsigned int hwd_event; + unsigned int poll_event; + int id; + char name[16]; + + struct dma_buf_attachment *dba[IPA_BUFFER_INDEX_MAX]; + struct sg_table *sgt[IPA_BUFFER_INDEX_MAX]; + enum dma_data_direction dma_dir[IPA_BUFFER_INDEX_MAX]; + unsigned int dma_count; + + dma_addr_t buffer_iova[IPA_BUFFER_INDEX_MAX]; +}; + +static u32 pyramid_ipa_addr_to_iova(struct pyramid_priv *priv, struct drv_ipa_addr addr) +{ + u32 iova = 0; + + if (addr.buffer_index < priv->dma_count && + addr.offset < priv->dba[addr.buffer_index]->dmabuf->size) + iova = priv->buffer_iova[addr.buffer_index] + addr.offset; + return iova; +} + +static int pyramid_attach_dma_buf(struct pyramid_priv *priv, unsigned int buffer_index, + struct drv_ipa_buffer_info *buffer_info) +{ + dma_addr_t addr; + int ret = 0; + + if (buffer_index >= IPA_BUFFER_INDEX_MAX) { + dev_err(priv->dev, "Buffer index invalid: index=%d\n", buffer_index); + return -EINVAL; + } + + switch (buffer_info[buffer_index].direction) { + case DRV_IPA_DIR_NONE: + priv->dma_dir[priv->dma_count] = DMA_NONE; + break; + case DRV_IPA_DIR_TO_DEVICE: + priv->dma_dir[priv->dma_count] = DMA_TO_DEVICE; + break; + case DRV_IPA_DIR_FROM_DEVICE: + priv->dma_dir[priv->dma_count] = DMA_FROM_DEVICE; + break; + case DRV_IPA_DIR_BIDIRECTION: + priv->dma_dir[priv->dma_count] = DMA_BIDIRECTIONAL; + break; + default: + dev_err(priv->dev, "DMA direction invalid: index=%d dir=%d\n", buffer_index, + buffer_info[buffer_index].direction); + return -EINVAL; + } + + ret = ipa_attach_dmabuf(priv->dev, buffer_info[buffer_index].fd, + &priv->dba[priv->dma_count], &priv->sgt[priv->dma_count], &addr, + priv->dma_dir[priv->dma_count]); + if (ret == 0) { + priv->dma_count++; + priv->buffer_iova[buffer_index] = addr; + } + + return ret; +} + +static void pyramid_detach_dma_buf(struct pyramid_priv *priv) +{ + struct dma_buf *dmabuf; + int i; + + for (i = 0; i < priv->dma_count; i++) { + dmabuf = priv->dba[i]->dmabuf; + dma_buf_unmap_attachment(priv->dba[i], priv->sgt[i], priv->dma_dir[i]); + dma_buf_detach(dmabuf, priv->dba[i]); + dma_buf_put(dmabuf); + } +} + +static irqreturn_t pyramid_irq(int irq, void *dev_id) +{ + struct pyramid_priv *priv = dev_id; + + priv->hwd_event = hwd_pyramid_irq_handler(priv->id); + + disable_irq_nosync(priv->irq); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t pyramid_irq_thread(int irq, void *dev_id) +{ + struct pyramid_priv *priv = dev_id; + unsigned long delay = 1; + + mutex_lock(&priv->lock); + pyramid_detach_dma_buf(priv); + + priv->status = DRV_IPA_STATE_IDLE; + + /* status should be updated before poll_event so that + * when poll() returns, user context must observe state as idle + */ + smp_wmb(); + + WARN_ON(priv->hwd_event != HWD_PYRAMID_EVENT_DONE); + priv->poll_event = IPA_POLL_EVENT_DONE; + + /* General barrier to avoid re-ordering of priv->poll_event=N and + * waitqueue_active() + */ + smp_mb(); + + /* Threads going to sleep in poll() can miss wakeup, when wakeup is done + * between event check in ipa_poll() and sleeping. Wakeup repeatedly. + */ + while (waitqueue_active(&priv->waitq)) { + wake_up_interruptible(&priv->waitq); + + WARN_ON(delay > IPA_WAKEUP_RETRY_DELAY); + usleep_range(delay, delay + 1); + delay += delay; + } + + mutex_unlock(&priv->lock); + + return IRQ_HANDLED; +} + +static void pyramid_start(struct pyramid_priv *priv, struct hwd_pyramid_descriptor *desc) +{ + hwd_pyramid_start(priv->id, desc); +} + +static int pyramid_ioctl_start(struct pyramid_priv *priv, unsigned long arg) +{ + struct hwd_pyramid_descriptor hwd_desc; + struct drv_pyramid_descriptor desc; + int ret = 0; + int i; + + ret = mutex_lock_interruptible(&priv->lock); + if (ret) + return ret; + + if (priv->status == DRV_IPA_STATE_BUSY) { + dev_dbg(priv->dev, "busy: %d\n", priv->status); + mutex_unlock(&priv->lock); + return -EBUSY; + } + + if (copy_from_user(&desc, (void __user *)arg, sizeof(struct drv_pyramid_descriptor))) { + dev_err(priv->dev, "Descriptor memory access error\n"); + ret = -EFAULT; + goto err1; + } + + if (!FIELD_GET(DRV_PYRAMID_BIT_CONFIG_DESC_FINAL, desc.config_done)) { + dev_err(priv->dev, "Descriptor configuration not complete\n"); + ret = -EINVAL; + goto err1; + } + + priv->dma_count = 0; + + /* setup buffer */ + for (i = 0; i < desc.buffer_info_num; i++) { + ret = pyramid_attach_dma_buf(priv, i, desc.buffer_info); + if (ret) { + dev_err(priv->dev, "dma buf attach error: index=%d\n", i); + goto err2; + } + } + + hwd_desc.port_enable = desc.port_enable; + hwd_desc.t00_sram_size = desc.t00_sram_size; + hwd_desc.config_done = desc.config_done; + hwd_desc.r_size = desc.r_size; + hwd_desc.mode2 = desc.mode2; + hwd_desc.r_y_pitch = desc.r_y_pitch; + hwd_desc.r_c_pitch = desc.r_c_pitch; + memcpy(hwd_desc.r_dmac_height, desc.r_dmac_height, sizeof(hwd_desc.r_dmac_height)); + hwd_desc.r_cfg0 = desc.r_cfg0; + memcpy(hwd_desc.r_sram_base, desc.r_sram_base, sizeof(hwd_desc.r_sram_base)); + memcpy(hwd_desc.r_sram_size, desc.r_sram_size, sizeof(hwd_desc.r_sram_size)); + memcpy(hwd_desc.w_size, desc.w_size, sizeof(hwd_desc.w_size)); + memcpy(hwd_desc.w_cfg0, desc.w_cfg0, sizeof(hwd_desc.w_cfg0)); + memcpy(hwd_desc.w_y_pitch, desc.w_y_pitch, sizeof(hwd_desc.w_y_pitch)); + memcpy(hwd_desc.w_c_pitch, desc.w_c_pitch, sizeof(hwd_desc.w_c_pitch)); + memcpy(hwd_desc.w_dmac_height, desc.w_dmac_height, sizeof(hwd_desc.w_dmac_height)); + memcpy(hwd_desc.w_sram_base, desc.w_sram_base, sizeof(hwd_desc.w_sram_base)); + memcpy(hwd_desc.w_sram_size, desc.w_sram_size, sizeof(hwd_desc.w_sram_size)); + hwd_desc.mode1 = desc.mode1; + memcpy(hwd_desc.scl_filmode, desc.scl_filmode, sizeof(hwd_desc.scl_filmode)); + hwd_desc.oainset = desc.oainset; + hwd_desc.oainset_m = desc.oainset_m; + memcpy(hwd_desc.oaoutset, desc.oaoutset, sizeof(hwd_desc.oaoutset)); + memcpy(hwd_desc.oaoutset_m, desc.oaoutset_m, sizeof(hwd_desc.oaoutset)); + hwd_desc.scl_h_crop_mode = desc.scl_h_crop_mode; + hwd_desc.scl_v_crop_mode = desc.scl_v_crop_mode; + hwd_desc.scl_h_crop_pos = desc.scl_h_crop_pos; + hwd_desc.scl_v_crop_pos = desc.scl_v_crop_pos; + memcpy(hwd_desc.width_ratio, desc.width_ratio, sizeof(hwd_desc.width_ratio)); + memcpy(hwd_desc.height_ratio, desc.height_ratio, sizeof(hwd_desc.height_ratio)); + memcpy(hwd_desc.h_oaoutset, desc.h_oaoutset, sizeof(hwd_desc.h_oaoutset)); + memcpy(hwd_desc.v_oaoutset, desc.v_oaoutset, sizeof(hwd_desc.v_oaoutset)); + + for (i = 0; i < HWD_PYRAMID_TAP_ELEMENT; i++) { + hwd_desc.tap_addr[i] = 0; + if (!drv_ipa_is_invalid_addr(desc.tap_addr[i])) { + hwd_desc.tap_addr[i] = pyramid_ipa_addr_to_iova(priv, desc.tap_addr[i]); + if (hwd_desc.tap_addr[i] == 0) { + dev_err(priv->dev, + "IPA address to iova conversion error: tap_addr %s: %d\n", + __func__, __LINE__); + ret = -EINVAL; + goto err2; + } + } + } + + for (i = 0; i < HWD_PYRAMID_DMA_READ_PORT; i++) { + hwd_desc.r_stadr[i] = 0; + if (!drv_ipa_is_invalid_addr(desc.r_stadr[i])) { + hwd_desc.r_stadr[i] = pyramid_ipa_addr_to_iova(priv, desc.r_stadr[i]); + if (hwd_desc.r_stadr[i] == 0) { + dev_err(priv->dev, + "IPA address to iova conversion error: r_stadr %s: %d\n", + __func__, __LINE__); + ret = -EINVAL; + goto err2; + } + } + } + + for (i = 0; i < HWD_PYRAMID_DMA_READ_PORT; i++) { + hwd_desc.r_endadr[i] = DRV_PYRAMID_DUMMY_END_ADDR; + if (!drv_ipa_is_invalid_addr(desc.r_endadr[i])) { + hwd_desc.r_endadr[i] = pyramid_ipa_addr_to_iova(priv, desc.r_endadr[i]); + if (hwd_desc.r_endadr[i] == 0) { + dev_err(priv->dev, + "IPA address to iova conversion error: r_endadr %s: %d\n", + __func__, __LINE__); + ret = -EINVAL; + goto err2; + } + } + } + + for (i = 0; i < HWD_PYRAMID_DMA_WRITE_PORT; i++) { + hwd_desc.w_stadr[i] = 0; + if (!drv_ipa_is_invalid_addr(desc.w_stadr[i])) { + hwd_desc.w_stadr[i] = pyramid_ipa_addr_to_iova(priv, desc.w_stadr[i]); + if (hwd_desc.w_stadr[i] == 0) { + dev_err(priv->dev, + "IPA address to iova conversion error: w_stadr %s: %d\n", + __func__, __LINE__); + ret = -EINVAL; + goto err2; + } + } + } + + for (i = 0; i < HWD_PYRAMID_DMA_WRITE_PORT; i++) { + hwd_desc.w_endadr[i] = DRV_PYRAMID_DUMMY_END_ADDR; + if (!drv_ipa_is_invalid_addr(desc.w_endadr[i])) { + hwd_desc.w_endadr[i] = pyramid_ipa_addr_to_iova(priv, desc.w_endadr[i]); + if (hwd_desc.w_endadr[i] == 0) { + dev_err(priv->dev, + "IPA address to iova conversion error: w_endadr %s: %d\n", + __func__, __LINE__); + ret = -EINVAL; + goto err2; + } + } + } + + pyramid_start(priv, &hwd_desc); + + priv->poll_event = IPA_POLL_EVENT_NONE; + priv->hwd_event = 0; + priv->status = DRV_IPA_STATE_BUSY; + /* Barrier to prevent pyramid_irq() from setting priv->hwd_event + * before it is reset above + */ + smp_wmb(); + enable_irq(priv->irq); + + mutex_unlock(&priv->lock); + + return ret; + +err2: + pyramid_detach_dma_buf(priv); +err1: + mutex_unlock(&priv->lock); + return ret; +} + +static int pyramid_ioctl_get_status(struct pyramid_priv *priv, unsigned long arg) +{ + struct drv_pyramid_status status; + int ret = 0; + + status.state = priv->status; + if (copy_to_user((void __user *)arg, &status, sizeof(struct drv_pyramid_status))) { + dev_err(priv->dev, "status memory access error\n"); + ret = -EFAULT; + } + + return ret; +} + +static long pyramid_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + struct pyramid_priv *priv = container_of(fp->private_data, struct pyramid_priv, miscdev); + int ret = 0; + + switch (cmd) { + case IOC_IPA_START: + ret = pyramid_ioctl_start(priv, arg); + break; + case IOC_IPA_GET_STATUS: + ret = pyramid_ioctl_get_status(priv, arg); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +static __poll_t pyramid_poll(struct file *fp, poll_table *wait) +{ + struct pyramid_priv *priv = container_of(fp->private_data, struct pyramid_priv, miscdev); + __poll_t mask = 0; + + poll_wait(fp, &priv->waitq, wait); + + /* Barrier to avoid re-ordering of poll_wait() and event load + * Read barrier here and release barrier in poll_wait() together will + * prevent re-ordering + */ + smp_rmb(); + if (priv->poll_event != IPA_POLL_EVENT_NONE) + mask = EPOLLIN | EPOLLRDNORM; + return mask; +} + +static const struct file_operations pyramid_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = pyramid_ioctl, + .poll = pyramid_poll, +}; + +static int pyramid_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pyramid_priv *priv; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->lock); + + /* update DMA mask */ + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); + if (ret) + return ret; + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) + return priv->irq; + + ret = devm_request_threaded_irq(dev, priv->irq, pyramid_irq, pyramid_irq_thread, 0, + "pyramid", priv); + if (ret) { + dev_err(dev, "irq request failed\n"); + return ret; + } + disable_irq(priv->irq); + + ret = of_property_read_u32(dev->of_node, "index", &priv->id); + if (ret) { + dev_err(dev, "failed to acquire irq resource\n"); + return ret; + } + + hwd_pyramid_initialize(priv->id, priv->regs); + + snprintf(priv->name, sizeof(priv->name), "pyramid%d", priv->id); + priv->miscdev.minor = MISC_DYNAMIC_MINOR; + priv->miscdev.name = priv->name; + priv->miscdev.fops = &pyramid_fops; + ret = misc_register(&priv->miscdev); + if (ret) { + dev_err(dev, "misc registration failed\n"); + hwd_pyramid_uninitialize(priv->id); + return ret; + } + + priv->dev = dev; + platform_set_drvdata(pdev, priv); + + init_waitqueue_head(&priv->waitq); + + priv->status = DRV_IPA_STATE_IDLE; + return 0; +} + +static int pyramid_remove(struct platform_device *pdev) +{ + struct pyramid_priv *priv = platform_get_drvdata(pdev); + + misc_deregister(&priv->miscdev); + hwd_pyramid_uninitialize(priv->id); + return 0; +} + +static const struct of_device_id pyramid_of_match[] = { + { + .compatible = "toshiba,visconti-pyramid", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, pyramid_of_match); + +static struct platform_driver pyramid_driver = { + .probe = pyramid_probe, + .remove = pyramid_remove, + .driver = { + .name = "visconti_pyramid", + .of_match_table = of_match_ptr(pyramid_of_match), + }, +}; +module_platform_driver(pyramid_driver); + +MODULE_AUTHOR("Yuji Ishikawa <yuji2.ishikawa(a)toshiba.co.jp>"); +MODULE_DESCRIPTION("Toshiba Visconti pyramid driver"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_IMPORT_NS(DMA_BUF); diff --git a/include/uapi/linux/visconti-ipa.h b/include/uapi/linux/visconti-ipa.h new file mode 100644 index 000000000..6a90ea5f9 --- /dev/null +++ b/include/uapi/linux/visconti-ipa.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* Toshiba Visconti Image Processing Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#ifndef _UAPI_LINUX_IPA_H +#define _UAPI_LINUX_IPA_H + +#include <linux/types.h> + +/** + * enum drv_ipa_state - state of Visconti IPA driver + * + * @DRV_IPA_STATE_IDLE: driver is idle + * @DRV_IPA_STATE_BUSY: device is busy + */ +enum drv_ipa_state { DRV_IPA_STATE_IDLE = 0, DRV_IPA_STATE_BUSY }; + +/** + * enum drv_ipa_buffer_direction - usage of buffer + * + * @DRV_IPA_DIR_BIDIRECTION: cpu writes/reads data + * @DRV_IPA_DIR_TO_DEVICE: cpu writes data + * @DRV_IPA_DIR_FROM_DEVICE: cpu reads data + * @DRV_IPA_DIR_NONE: cpu not access or non-coherent + */ +enum drv_ipa_buffer_direction { + DRV_IPA_DIR_BIDIRECTION = 0, + DRV_IPA_DIR_TO_DEVICE, + DRV_IPA_DIR_FROM_DEVICE, + DRV_IPA_DIR_NONE +}; + +/** + * struct drv_ipa_buffer_info - buffer information for Visconti IPA drivers + * + * @fd: file descriptor of a dma-buf heap instance + * @flags: optional flags for attributes of the buffer + * @direction: A &enum drv_ipa_buffer_direction value + * for buffer direction (to/from device) + */ +struct drv_ipa_buffer_info { + __u32 fd; + __u32 flags; + __u32 direction; +}; + +/** + * struct drv_ipa_addr - address structure for Visconti IPA drivers + * + * @buffer_index: array index of &struct drv_ipa_buffer_info + * @offset: offset from the top of the heap instance + */ +struct drv_ipa_addr { + __u32 buffer_index; + __u32 offset; +}; + +#define IPA_BUFFER_INDEX_MAX (16) +#define IPA_INVALID_ADDR \ + { \ + .buffer_index = 0xffffffffu, .offset = 0xffffffffu \ + } + +static inline struct drv_ipa_addr drv_ipa_invalid_addr(void) +{ + struct drv_ipa_addr invalid_addr = IPA_INVALID_ADDR; + return invalid_addr; +} + +static inline bool drv_ipa_is_invalid_addr(struct drv_ipa_addr addr) +{ + struct drv_ipa_addr invalid_addr = IPA_INVALID_ADDR; + + if (addr.buffer_index == invalid_addr.buffer_index && addr.offset == invalid_addr.offset) + return true; + + return false; +} + +#define IOC_IPA_MAGIC 'I' +#define IOC_IPA_START _IO(IOC_IPA_MAGIC, 0) +#define IOC_IPA_GET_STATUS _IO(IOC_IPA_MAGIC, 1) + +#endif /* _UAPI_LINUX_IPA_H */ diff --git a/include/uapi/linux/visconti-pyramid.h b/include/uapi/linux/visconti-pyramid.h new file mode 100644 index 000000000..b2987b2d2 --- /dev/null +++ b/include/uapi/linux/visconti-pyramid.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* Toshiba Visconti Affine Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#ifndef _UAPI_LINUX_PYRAMID_H +#define _UAPI_LINUX_PYRAMID_H + +#include <linux/const.h> +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/visconti-ipa.h> + +#define DRV_PYRAMID_BIT_CONFIG_DESC_FINAL _BITUL(15) + +#define DRV_PYRAMID_YH (0U) /* Horizontal Y Component */ +#define DRV_PYRAMID_YV (1U) /* Vertical Y Component */ +#define DRV_PYRAMID_CH (2U) /* Horizontal C Component */ +#define DRV_PYRAMID_CV (3U) /* Vertical C Component */ +#define DRV_PYRAMID_YCHV (4U) /* Total [YC][HV] Combinations */ +#define DRV_PYRAMID_TAP_ELEMENT (16U) /* YH1, YV1, CH1, CV1, YH2, ... , CV4 */ +#define DRV_PYRAMID_DMA_READ_PORT (3U) /* Y, Cb, Cr */ +#define DRV_PYRAMID_DMA_WRITE_PORT (12U) /* Y1, Y2, Y3, Y4, Cb1, Cb2, ... , Cr4 */ +#define DRV_PYRAMID_SCALER_ROUTE (4U) /* Scaler 0-3 */ + +/** + * struct drv_pyramid_status - PYRAMID IPA status for IOC_IPA_GET_STATUS + * @state: A &enum drv_ipa_state value for the state of the driver + */ +struct drv_pyramid_status { + __u32 state; +}; + +/** + * struct drv_pyramid_descriptor - PYRAMID IPA descriptor for IOC_IPA_START + * @port_enable: Read, Write and TAP Port enable/disable + * @t00_sram_size: Table Port 00 SRAM FIFO size + * @config_done: Status of the config APIs called + * @tap_addr: Table ID00 to 15 Transfer Start Address Register + * @r_stadr: Y, Cb, Cr data start address of input data + * @r_endadr: Y, Cb, Cr data end address of input data + * @r_size: Input width and height + * @mode2: Scaler mode setting register 2 + * @r_y_pitch: The lines pitch of y on input image + * @r_c_pitch: The lines pitch of y on input image + * @r_dmac_height: Read port configuration register 0 + * @r_cfg0: Line pitch of the table used in the table conversion mode + * @r_sram_base: Internal read port sram base address + * @r_sram_size: Internal read port sram size + * @w_stadr: Y, Cb, and Cr data address of Scaler0-3 + * @w_endadr: Y, Cb, and Cr data address of Scaler0-3 + * @w_size: Output width and height of Scaler0-3 + * @w_cfg0: Write port configuration register 0 + * @w_y_pitch: The lines pitch of y output image from Scaler0-3 + * @w_c_pitch: The lines pitch of c output image from Scaler0-3 + * @w_dmac_height: Number of line rectangle data + * @w_sram_base: Internal write port sram base address + * @w_sram_size: Internal write port sram size + * @mode1: Scaler mode setting register 1 + * @scl_filmode: Filter mode setting of Scaler (common to Scaler0-3) + * @oainset: Filter input effective pixel outside boundary processing + * @oainset_m: Filter input effective pixel outside boundary processing + * @oaoutset: Fixed data setting of filter output + * @oaoutset_m: Fixed data setting of filter output + * @scl_h_crop_mode: Cropping setting of horizontal (common to Scaler0-3) + * @scl_v_crop_mode: Cropping setting of vertical (common to Scaler0-3) + * @scl_h_crop_pos: Starting position of horizontal cropping(common to Scaler0-3) + * @scl_v_crop_pos: Starting position of vertical cropping(common to Scaler0-3) + * @width_ratio: Width reduction/expansion rate of Scaler0 to 3 + * @height_ratio: Height reduction/expansion rate of Scaler0 to 3 + * @h_oaoutset: Left and right position for fixed data setting of filter output + * @v_oaoutset: Upper and lower position for fixed data setting of filter output + * @buffer_info: Table of buffer information + * @buffer_info_num: Number of buffer_info + */ +struct drv_pyramid_descriptor { + __u32 port_enable; + __u16 t00_sram_size; + __u16 config_done; + struct drv_ipa_addr tap_addr[DRV_PYRAMID_TAP_ELEMENT]; + struct drv_ipa_addr r_stadr[DRV_PYRAMID_DMA_READ_PORT]; + struct drv_ipa_addr r_endadr[DRV_PYRAMID_DMA_READ_PORT]; + __u32 r_size; + __u32 mode2; + __u32 r_y_pitch; + __u32 r_c_pitch; + __u16 r_dmac_height[DRV_PYRAMID_DMA_READ_PORT]; + __u16 r_cfg0; + __u16 r_sram_base[DRV_PYRAMID_DMA_READ_PORT]; + __u16 r_sram_size[DRV_PYRAMID_DMA_READ_PORT]; + struct drv_ipa_addr w_stadr[DRV_PYRAMID_DMA_WRITE_PORT]; + struct drv_ipa_addr w_endadr[DRV_PYRAMID_DMA_WRITE_PORT]; + __u32 w_size[DRV_PYRAMID_SCALER_ROUTE]; + __u16 w_cfg0[DRV_PYRAMID_DMA_WRITE_PORT]; + __u32 w_y_pitch[DRV_PYRAMID_SCALER_ROUTE]; + __u32 w_c_pitch[DRV_PYRAMID_SCALER_ROUTE]; + __u16 w_dmac_height[DRV_PYRAMID_DMA_WRITE_PORT]; + __u16 w_sram_base[DRV_PYRAMID_DMA_WRITE_PORT]; + __u16 w_sram_size[DRV_PYRAMID_DMA_WRITE_PORT]; + __u32 mode1; + __u8 scl_filmode[DRV_PYRAMID_YCHV]; + __u32 oainset; + __u32 oainset_m; + __u32 oaoutset[DRV_PYRAMID_SCALER_ROUTE]; + __u32 oaoutset_m[DRV_PYRAMID_SCALER_ROUTE]; + __u32 scl_h_crop_mode; + __u32 scl_v_crop_mode; + __u32 scl_h_crop_pos; + __u32 scl_v_crop_pos; + __u32 width_ratio[DRV_PYRAMID_SCALER_ROUTE]; + __u32 height_ratio[DRV_PYRAMID_SCALER_ROUTE]; + __u32 h_oaoutset[DRV_PYRAMID_SCALER_ROUTE]; + __u32 v_oaoutset[DRV_PYRAMID_SCALER_ROUTE]; + struct drv_ipa_buffer_info buffer_info[IPA_BUFFER_INDEX_MAX]; + __s32 buffer_info_num; +}; + +#endif /* _UAPI_LINUX_PYRAMID_H */ -- 2.17.1

2 years, 5 months

FYI: misc: visconti: Toshiba Visconti DSP accelerator driver sample

by Yuji Ishikawa

Hello Odded This is a sample (wip) driver for a DSP found on Toshiba Visconti SoC. The DSP typically accepts some images, apply an algorithm on them and yields resulting one. Therefore (image-in, image-out), they say this driver should be classified to media driver category. However, it can handle various data format (wider than v4l2 officially supports) if userland provide firmware (=algorithm) for its own. Yes, this rough implementation is the first step only our staff could go. I'm not for sure whether we could carry out experiments earlier if we chose to use existing frameworks, instead of writing our own routine for handling DMA-BUFs and interrupts. I hope this post will help your case-study. Regards Yuji Ishikawa ==== misc: visconti: Add Toshiba Visconti DSPIF image processing accelerator Add support to DSPIF image processing accelerator on Toshiba Visconti ARM SoCs. The accelerator accepts a task description and a firmware, provides various filter / image processing algorithm. Currently, DSP firmware is fixed one loaded by bootloader. And the phisical address of the firmware is specified from userland, not hard-coded nor loaded from device tree. CPU and DSP share following communication media to manage tasks. * DSP registers: 32bit word access registers to specify DSP firmware address and several parameters. * shared mem: a part of DRAM to pass task description (struct hwd_dspif_msg). The DSP busmaster interface is little endian. * interrupt controller (DCOMM): to notify start event (CPU->DSP) and finish event (DSP->CPU). The implementation has two C sources: * dspif.c The user interface. It receives inference task description from userlan library. manages lifecycle of DMA-BUF instances holding input/output data, managegs interrupt requests and updates device file status. Memory blocks are specified with fds + offsets of DMA-BUF instances. * hwd_dspif.c The hardware layer. It configures hardware registers following a request from dspif.c. This layer communicate with DSP hardware via registers, shared memory and dedicated interrupt controller. Memory blocks are specified with 32bit-truncated phisical address Future plan: * Power management operations will be added, once the visconti clock framework driver supports the DSP hardware. * When the visconti IOMMU driver (currently under review) is accepted, the hardware layer will use 32bit IO virutal address mapped by the dedicated IOMMU. * Better way to load / specify DSP firmware. dt-bindings: misc: visconti: Add Toshiba Visconti DSPIF image processing accelerator bindings Also, here's a Device Tree binding documentation that allows to describe the DSPIF image processing accelerator found in Toshiba Visconti SoCs. Signed-off-by: Yuji Ishikawa <yuji2.ishikawa(a)toshiba.co.jp> --- .../misc/visconti/toshiba,visconti-dspif.yaml | 61 ++ drivers/misc/Kconfig | 1 + drivers/misc/Makefile | 1 + drivers/misc/visconti/Kconfig | 8 + drivers/misc/visconti/Makefile | 7 + drivers/misc/visconti/dspif/Makefile | 8 + drivers/misc/visconti/dspif/dspif.c | 547 ++++++++++++++++++ drivers/misc/visconti/dspif/hwd_dspif.c | 275 +++++++++ drivers/misc/visconti/dspif/hwd_dspif.h | 100 ++++ include/uapi/linux/visconti-dspif.h | 85 +++ include/uapi/linux/visconti-ipa.h | 87 +++ 11 files changed, 1180 insertions(+) create mode 100644 Documentation/devicetree/bindings/misc/visconti/toshiba,visconti-dspif.yaml create mode 100644 drivers/misc/visconti/Kconfig create mode 100644 drivers/misc/visconti/Makefile create mode 100644 drivers/misc/visconti/dspif/Makefile create mode 100644 drivers/misc/visconti/dspif/dspif.c create mode 100644 drivers/misc/visconti/dspif/hwd_dspif.c create mode 100644 drivers/misc/visconti/dspif/hwd_dspif.h create mode 100644 include/uapi/linux/visconti-dspif.h create mode 100644 include/uapi/linux/visconti-ipa.h diff --git a/Documentation/devicetree/bindings/misc/visconti/toshiba,visconti-dspif.yaml b/Documentation/devicetree/bindings/misc/visconti/toshiba,visconti-dspif.yaml new file mode 100644 index 000000000..7c10e28dc --- /dev/null +++ b/Documentation/devicetree/bindings/misc/visconti/toshiba,visconti-dspif.yaml @@ -0,0 +1,61 @@ +# SPDX-LIcense-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/visconti/toshiba,visconti-dspif.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Toshiba Visconti DSPIF image processing accerelator + +maintainers: + - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu(a)toshiba.co.jp> + +description: | + Toshiba Visconti DSPIF image processing accelerator provides various operation on images. + Visconti5 have up to 4 DSP units. + +properties: + compatible: + items: + - const: toshiba,visconti-dspif + + reg: + items: + - description: DSP control register + - description: DCOMM interrupt controller register + + interrupts: + maxItems: 1 + + index: + enum: [0, 1, 2, 3] + + comm_base: + $ref: /schemas/types.yaml#/definitions/uint64 + description: shared memory address for communication between CPU and DSP + +required: + - compatible + - reg + - interrupts + - index + - comm_base + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + dsp0: dsp@30000000 { + compatible = "toshiba,visconti-dspif"; + reg = <0 0x30000000 0 0x01ffe000>, <0 0x24050000 0 0x10000>; + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; + index = <0>; + comm_base = /bits/ 64 <0x81e00000>; + status = "disabled"; + }; + }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 0f5a49fc7..4da73fd4c 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -487,4 +487,5 @@ source "drivers/misc/cardreader/Kconfig" source "drivers/misc/habanalabs/Kconfig" source "drivers/misc/uacce/Kconfig" source "drivers/misc/pvpanic/Kconfig" +source "drivers/misc/visconti/Kconfig" endmenu diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index a086197af..946c6f961 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -59,3 +59,4 @@ obj-$(CONFIG_UACCE) += uacce/ obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o obj-$(CONFIG_HISI_HIKEY_USB) += hisi_hikey_usb.o obj-$(CONFIG_HI6421V600_IRQ) += hi6421v600-irq.o +obj-$(CONFIG_ARCH_VISCONTI) += visconti/ diff --git a/drivers/misc/visconti/Kconfig b/drivers/misc/visconti/Kconfig new file mode 100644 index 000000000..1b68e9cf3 --- /dev/null +++ b/drivers/misc/visconti/Kconfig @@ -0,0 +1,8 @@ +if ARCH_VISCONTI + +config VISCONTI_DSPIF + tristate "Visconti DSPIF driver" + help + This option enable support for the Toshiba Visconti DSPIF accelerator driver. + +endif diff --git a/drivers/misc/visconti/Makefile b/drivers/misc/visconti/Makefile new file mode 100644 index 000000000..b52a9344a --- /dev/null +++ b/drivers/misc/visconti/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Visconti specific device drivers. +# + +obj-$(CONFIG_VISCONTI_DSPIF) += dspif/ + diff --git a/drivers/misc/visconti/dspif/Makefile b/drivers/misc/visconti/dspif/Makefile new file mode 100644 index 000000000..290c6a53b --- /dev/null +++ b/drivers/misc/visconti/dspif/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Makefile for the Visconti DSPIF driver +# + +visconti-dspif-objs = dspif.o hwd_dspif.o + +obj-$(CONFIG_VISCONTI_DSPIF) += visconti-dspif.o diff --git a/drivers/misc/visconti/dspif/dspif.c b/drivers/misc/visconti/dspif/dspif.c new file mode 100644 index 000000000..7e0931f0e --- /dev/null +++ b/drivers/misc/visconti/dspif/dspif.c @@ -0,0 +1,547 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +/* Toshiba Visconti DSPIF Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#include <linux/delay.h> +#include <linux/dma-mapping.h> +#include <linux/dma-buf.h> +#include <linux/io.h> +#include <linux/init.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/miscdevice.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/poll.h> +#include <linux/visconti-dspif.h> +#include <linux/wait.h> + +#include "hwd_dspif.h" + +#define IPA_POLL_EVENT_NONE (0) +#define IPA_POLL_EVENT_DONE (1) +#define IPA_POLL_EVENT_ERROR (2) +#define IPA_WAKEUP_RETRY_DELAY (300 * 1000) /*usec*/ + +#define DRV_DSPIF_FW_ADDR_MASK 0x3ff +#define DRV_DSPIF_COMM_IOVA_END (0x81E0A000U) + +struct dspif_priv { + struct device *dev; + struct miscdevice miscdev; + struct mutex lock; /* only 1 user context execute an API at a time */ + void __iomem *regs; + void __iomem *dcomm_regs; + void __iomem *comm_base; + u64 comm_paddr; + u32 comm_size; + int irq; + wait_queue_head_t waitq; + enum drv_ipa_state status; + unsigned int hwd_event; + unsigned int poll_event; + int id; + char name[16]; + struct hwd_dspif_status hwd_status; + + struct dma_buf_attachment *dba[DRV_DSPIF_BUFFER_INDEX_MAX]; + struct sg_table *sgt[DRV_DSPIF_BUFFER_INDEX_MAX]; + enum dma_data_direction dma_dir[DRV_DSPIF_BUFFER_INDEX_MAX]; + unsigned int dma_count; + + dma_addr_t buffer_iova[DRV_DSPIF_BUFFER_INDEX_MAX]; +}; + +static int ipa_attach_dmabuf(struct device *dev, int fd, struct dma_buf_attachment **a, + struct sg_table **s, dma_addr_t *addr, enum dma_data_direction dma_dir) +{ + struct dma_buf_attachment *attachment; + struct dma_buf *dmabuf; + struct sg_table *sgt; + int ret; + + dmabuf = dma_buf_get(fd); + if (IS_ERR(dmabuf)) { + dev_err(dev, "Invalid dmabuf FD\n"); + return PTR_ERR(dmabuf); + } + attachment = dma_buf_attach(dmabuf, dev); + + if (IS_ERR(attachment)) { + dev_err(dev, "Failed to attach dmabuf\n"); + ret = PTR_ERR(attachment); + goto err_put; + } + sgt = dma_buf_map_attachment(attachment, dma_dir); + if (IS_ERR(sgt)) { + dev_err(dev, "Failed to get dmabufs sg_table\n"); + ret = PTR_ERR(sgt); + goto err_detach; + } + if (sgt->nents != 1) { + dev_err(dev, "Sparse DMA region is unsupported\n"); + ret = -EINVAL; + goto err_unmap; + } + + *addr = sg_dma_address(sgt->sgl); + *a = attachment; + *s = sgt; + + return 0; + +err_unmap: + dma_buf_unmap_attachment(attachment, sgt, dma_dir); +err_detach: + dma_buf_detach(dmabuf, attachment); +err_put: + dma_buf_put(dmabuf); + return ret; +} + +static u32 dspif_ipa_addr_to_iova(struct dspif_priv *priv, struct drv_ipa_addr addr) +{ + u32 iova = 0; + + if (addr.buffer_index < priv->dma_count && + addr.offset < priv->dba[addr.buffer_index]->dmabuf->size) + iova = priv->buffer_iova[addr.buffer_index] + addr.offset; + return iova; +} + +static int dspif_attach_dma_buf(struct dspif_priv *priv, unsigned int buffer_index, + struct drv_ipa_buffer_info buffer_info[DRV_DSPIF_BUFFER_INDEX_MAX]) +{ + dma_addr_t addr; + int ret = 0; + + if (buffer_index >= DRV_DSPIF_BUFFER_INDEX_MAX) { + dev_err(priv->dev, "Buffer index invalid: index=%d\n", buffer_index); + return -EINVAL; + } + + switch (buffer_info[buffer_index].direction) { + case DRV_IPA_DIR_NONE: + priv->dma_dir[priv->dma_count] = DMA_NONE; + break; + case DRV_IPA_DIR_TO_DEVICE: + priv->dma_dir[priv->dma_count] = DMA_TO_DEVICE; + break; + case DRV_IPA_DIR_FROM_DEVICE: + priv->dma_dir[priv->dma_count] = DMA_FROM_DEVICE; + break; + case DRV_IPA_DIR_BIDIRECTION: + priv->dma_dir[priv->dma_count] = DMA_BIDIRECTIONAL; + break; + default: + dev_err(priv->dev, "DMA direction invalid: index=%d dir=%d\n", buffer_index, + buffer_info[buffer_index].direction); + return -EINVAL; + } + + ret = ipa_attach_dmabuf(priv->dev, buffer_info[buffer_index].fd, + &priv->dba[priv->dma_count], &priv->sgt[priv->dma_count], &addr, + priv->dma_dir[priv->dma_count]); + if (ret == 0) { + priv->dma_count++; + priv->buffer_iova[buffer_index] = addr; + } + + return ret; +} + +static void dspif_detach_dma_buf(struct dspif_priv *priv) +{ + struct dma_buf *dmabuf; + int i; + + for (i = 0; i < priv->dma_count; i++) { + dmabuf = priv->dba[i]->dmabuf; + dma_buf_unmap_attachment(priv->dba[i], priv->sgt[i], priv->dma_dir[i]); + dma_buf_detach(dmabuf, priv->dba[i]); + dma_buf_put(dmabuf); + } +} + +static int dspif_validate_address(struct dspif_priv *priv, u32 fw_addr, u64 comm_paddr) +{ + int i; + + for (i = 0; i < priv->dma_count; i++) { + if (priv->buffer_iova[i] < DRV_DSPIF_COMM_IOVA_END) + return -ENOSPC; + } + + return 0; +} + +static irqreturn_t dspif_irq(int irq, void *dev_id) +{ + struct dspif_priv *priv = dev_id; + + priv->hwd_event = hwd_dspif_irq_handler(priv->id); + + disable_irq_nosync(priv->irq); + + return IRQ_WAKE_THREAD; +} + +static irqreturn_t dspif_irq_thread(int irq, void *dev_id) +{ + struct dspif_priv *priv = dev_id; + unsigned long delay = 1; + + mutex_lock(&priv->lock); + dspif_detach_dma_buf(priv); + + hwd_dspif_stop(priv->id); + + hwd_dspif_get_status(priv->id, &priv->hwd_status); + + priv->status = DRV_IPA_STATE_IDLE; + + /* status should be updated before poll_event so that + * when poll() returns, user context must observe state as idle + */ + smp_wmb(); + + if (priv->hwd_event == HWD_DSPIF_EVENT_DONE) + priv->poll_event = IPA_POLL_EVENT_DONE; + else + priv->poll_event = IPA_POLL_EVENT_ERROR; + + /* General barrier to avoid re-ordering of priv->poll_event=N and + * waitqueue_active() + */ + smp_mb(); + + /* Threads going to sleep in poll() can miss wakeup, when wakeup is done + * between event check in ipa_poll() and sleeping. Wakeup repeatedly. + */ + while (waitqueue_active(&priv->waitq)) { + wake_up_interruptible(&priv->waitq); + + WARN_ON(delay > IPA_WAKEUP_RETRY_DELAY); + usleep_range(delay, delay + 1); + delay += delay; + } + + mutex_unlock(&priv->lock); + + return IRQ_HANDLED; +} + +static void dspif_start(struct dspif_priv *priv, struct hwd_dspif_descriptor *desc) +{ + hwd_dspif_start(priv->id, desc); +} + +static int dspif_ioctl_start(struct dspif_priv *priv, unsigned long arg) +{ + struct hwd_dspif_descriptor hwd_desc; + struct drv_dspif_descriptor desc; + unsigned int i; + int ret = 0; + + ret = mutex_lock_interruptible(&priv->lock); + if (ret) + return ret; + + if (priv->status == DRV_IPA_STATE_BUSY) { + dev_dbg(priv->dev, "busy: %d\n", priv->status); + mutex_unlock(&priv->lock); + return -EBUSY; + } + + if (copy_from_user(&desc, (void __user *)arg, sizeof(struct drv_dspif_descriptor))) { + dev_err(priv->dev, "Descriptor memory access error\n"); + ret = -EFAULT; + goto err1; + } + + if ((desc.fw_addr & DRV_DSPIF_FW_ADDR_MASK) != 0U) { + dev_err(priv->dev, "Invalid Firmware address\n"); + ret = -EINVAL; + goto err1; + } + + priv->dma_count = 0; + + /* setup buffer */ + for (i = 0; i < desc.buffer_info_num; i++) { + ret = dspif_attach_dma_buf(priv, i, desc.buffer_info); + if (ret) { + dev_err(priv->dev, "dma buf attach error: index=%d\n", i); + goto err2; + } + } + + /* setup descriptor */ + hwd_desc.fw_addr = desc.fw_addr; + hwd_desc.msg.id = cpu_to_le32(desc.msg.id); + hwd_desc.msg.error = cpu_to_le32(desc.msg.error); + + for (i = 0; i < HWD_DSPIF_NUM_ARG_IMM; i++) + hwd_desc.msg.imm[i].value = cpu_to_le64(desc.msg.imm[i].value); + + for (i = 0; i < DRV_DSPIF_NUM_ARG_REF; i++) { + u64 iova; + + if (drv_ipa_is_invalid_addr(desc.msg.ref[i].address)) + continue; + + iova = dspif_ipa_addr_to_iova(priv, desc.msg.ref[i].address); + if (iova == 0) { + dev_err(priv->dev, "IPA address to iova conversion error: ref %s: %d\n", + __func__, __LINE__); + ret = -EINVAL; + goto err2; + } + hwd_desc.msg.ref[i].address = cpu_to_le64(iova); + hwd_desc.msg.ref[i].size = cpu_to_le64(desc.msg.ref[i].size); + } + + for (i = 0; i < DRV_DSPIF_NUM_ARG_IMG; i++) { + u64 iova; + + if (drv_ipa_is_invalid_addr(desc.msg.img[i].address)) + continue; + + iova = dspif_ipa_addr_to_iova(priv, desc.msg.img[i].address); + if (iova == 0) { + dev_err(priv->dev, "IPA address to iova conversion error: ref %s: %d\n", + __func__, __LINE__); + ret = -EINVAL; + goto err2; + } + + hwd_desc.msg.img[i].address = cpu_to_le64(iova); + hwd_desc.msg.img[i].width = cpu_to_le32(desc.msg.img[i].width); + hwd_desc.msg.img[i].height = cpu_to_le32(desc.msg.img[i].height); + hwd_desc.msg.img[i].pitch = cpu_to_le32(desc.msg.img[i].pitch); + hwd_desc.msg.img[i].type = cpu_to_le32(desc.msg.img[i].type); + } + + ret = dspif_validate_address(priv, desc.fw_addr, priv->comm_paddr); + if (ret) { + dev_err(priv->dev, "no space left in dspif\n"); + goto err2; + } + + dspif_start(priv, &hwd_desc); + + priv->poll_event = IPA_POLL_EVENT_NONE; + priv->hwd_event = 0; + priv->status = DRV_IPA_STATE_BUSY; + /* Barrier to prevent dspif_irq() from setting priv->hwd_event + * before it is reset above + */ + smp_wmb(); + enable_irq(priv->irq); + + mutex_unlock(&priv->lock); + + return ret; + +err2: + dspif_detach_dma_buf(priv); +err1: + mutex_unlock(&priv->lock); + return ret; +} + +static int dspif_ioctl_get_status(struct dspif_priv *priv, unsigned long arg) +{ + struct hwd_dspif_status hwd_status; + struct drv_dspif_status status; + int ret = 0; + + ret = mutex_lock_interruptible(&priv->lock); + if (ret) + return ret; + + if (priv->status == DRV_IPA_STATE_BUSY) + hwd_dspif_get_status(priv->id, &hwd_status); + else + hwd_status = priv->hwd_status; + + status.state = priv->status; + mutex_unlock(&priv->lock); + + status.error = hwd_status.error; + if (copy_to_user((void __user *)arg, &status, sizeof(struct drv_dspif_status))) { + dev_err(priv->dev, "status memory access error\n"); + ret = -EFAULT; + } + + return ret; +} + +static long dspif_ioctl(struct file *fp, unsigned int cmd, unsigned long arg) +{ + struct dspif_priv *priv = container_of(fp->private_data, struct dspif_priv, miscdev); + int ret = 0; + + switch (cmd) { + case IOC_IPA_START: + ret = dspif_ioctl_start(priv, arg); + break; + case IOC_IPA_GET_STATUS: + ret = dspif_ioctl_get_status(priv, arg); + break; + default: + ret = -ENOIOCTLCMD; + break; + } + + return ret; +} + +static __poll_t dspif_poll(struct file *fp, poll_table *wait) +{ + struct dspif_priv *priv = container_of(fp->private_data, struct dspif_priv, miscdev); + unsigned int poll_event; + __poll_t mask = 0; + + poll_wait(fp, &priv->waitq, wait); + + /* Barrier to avoid re-ordering of poll_wait() and event load + * Read barrier here and release barrier in poll_wait() together will + * prevent re-ordering + */ + smp_rmb(); + poll_event = priv->poll_event; + if (poll_event != IPA_POLL_EVENT_NONE) { + if (poll_event == IPA_POLL_EVENT_DONE) + mask = EPOLLIN | EPOLLRDNORM; + else + mask = EPOLLERR; + } + return mask; +} + +static const struct file_operations dspif_fops = { + .owner = THIS_MODULE, + .unlocked_ioctl = dspif_ioctl, + .poll = dspif_poll, +}; + +static int dspif_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct dspif_priv *priv; + struct resource *res; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->lock); + + /* update DMA mask */ + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36)); + if (ret) + return ret; + + priv->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->regs)) + return PTR_ERR(priv->regs); + + /* + * devm_platform_ioremap_resource() failes for multiple requests + * because the DCOMM region is shared up to 4 instances of this driver. + */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + priv->dcomm_regs = devm_ioremap(dev, res->start, resource_size(res)); + if (IS_ERR(priv->dcomm_regs)) + return PTR_ERR(priv->dcomm_regs); + + priv->irq = platform_get_irq(pdev, 0); + if (priv->irq < 0) + return priv->irq; + + ret = devm_request_threaded_irq(dev, priv->irq, dspif_irq, dspif_irq_thread, 0, "dspif", + priv); + if (ret) { + dev_err(dev, "irq request failed\n"); + return ret; + } + disable_irq(priv->irq); + + ret = of_property_read_u32(dev->of_node, "index", &priv->id); + if (ret) { + dev_err(dev, "failed to acquire index\n"); + return ret; + } + + ret = of_property_read_u64(dev->of_node, "comm_base", &priv->comm_paddr); + if (ret) { + dev_err(dev, "failed to acquire comm base resource\n"); + return ret; + } + priv->comm_size = 0x1000; + priv->comm_base = ioremap(priv->comm_paddr, priv->comm_size); + if (IS_ERR(priv->comm_base)) + return PTR_ERR(priv->comm_base); + + hwd_dspif_initialize(priv->id, priv->dcomm_regs, priv->regs, priv->comm_base); + + snprintf(priv->name, sizeof(priv->name), "dspif%d", priv->id); + priv->miscdev.minor = MISC_DYNAMIC_MINOR; + priv->miscdev.name = priv->name; + priv->miscdev.fops = &dspif_fops; + ret = misc_register(&priv->miscdev); + if (ret) { + dev_err(dev, "misc registration failed\n"); + hwd_dspif_uninitialize(priv->id); + return ret; + } + + dev_info(dev, "com_base=0x%llx\n", priv->comm_paddr); + + priv->dev = dev; + platform_set_drvdata(pdev, priv); + + init_waitqueue_head(&priv->waitq); + + priv->status = DRV_IPA_STATE_IDLE; + return 0; +} + +static int dspif_remove(struct platform_device *pdev) +{ + struct dspif_priv *priv = platform_get_drvdata(pdev); + + misc_deregister(&priv->miscdev); + hwd_dspif_uninitialize(priv->id); + return 0; +} + +static const struct of_device_id dspif_of_match[] = { + { + .compatible = "toshiba,visconti-dspif", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, dspif_of_match); + +static struct platform_driver dspif_driver = { + .probe = dspif_probe, + .remove = dspif_remove, + .driver = { + .name = "visconti_dspif", + .of_match_table = of_match_ptr(dspif_of_match), + }, +}; +module_platform_driver(dspif_driver); + +MODULE_AUTHOR("Yuji Ishikawa <yuji2.ishikawa(a)toshiba.co.jp>"); +MODULE_DESCRIPTION("Toshiba Visconti dspif driver"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_IMPORT_NS(DMA_BUF); diff --git a/drivers/misc/visconti/dspif/hwd_dspif.c b/drivers/misc/visconti/dspif/hwd_dspif.c new file mode 100644 index 000000000..38ae6545e --- /dev/null +++ b/drivers/misc/visconti/dspif/hwd_dspif.c @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +/* Toshiba Visconti DSPIF Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#include <linux/delay.h> +#include <linux/errno.h> +#include <linux/io.h> +#include <linux/types.h> + +#include "hwd_dspif.h" + +/* DCOMM registers */ +#define DCOMM_DEST_ENABLE 0x0010 +#define DCOMM_ERR_SET_DSP 0x0100 +#define DCOMM_ERR_CLR_DSP 0x0200 +#define DCOMM_ERR_STATUS_DSP 0x0300 + +/* + * rr, dd: 0x00 - 0x03 + */ +#define ROFF(rr) ((rr) * 0x80) +#define DOFF(dd) ((dd) * 0x04) + +#define DCOMM_INT_SET_RRR_D16(rr) (0x1000 + ROFF(rr) + DOFF(16)) +#define DCOMM_INT_SET_R04_DDD(dd) (0x1200 + DOFF(dd)) +#define DCOMM_INT_MSK_RRR_D16(rr) (0x2000 + ROFF(rr) + DOFF(16)) +#define DCOMM_INT_MSK_R04_DDD(dd) (0x2200 + DOFF(dd)) +#define DCOMM_INT_CLR_RRR_D16(rr) (0x3000 + ROFF(rr) + DOFF(16)) +#define DCOMM_INT_CLR_R04_DDD(dd) (0x3200 + DOFF(dd)) + +/* DSP control registers */ +#define DSP_RESET_VECTOR 0x0000 +#define DSP_ARB_XTS_PRIORITY 0xD008 +#define DSP_ARB_DMA_PRIORITY 0xD088 + +/* COMM between DSP and CPU */ +#define COMM_DSPIF_MSG_ERROR (offsetof(struct hwd_dspif_msg, error)) + +/* Arbitration register values */ +#define HWD_DSP_ARB_XTS (0x00000101U) +#define HWD_DSP_ARB_DMA (0x00000000U) + +#define HWD_DSPIF_DCOMM_SEND_BIT BIT(0) +#define HWD_DSPIF_DCOMM_UNMASK_SHIFT 16 +#define HWD_DSPIF_DCOMM_UNMASK_SEND BIT(0 + HWD_DSPIF_DCOMM_UNMASK_SHIFT) +#define HWD_DSPIF_DCOMM_MASK_SEND (HWD_DSPIF_DCOMM_SEND_BIT) + +/** + * struct hwd_dspif_resources - HWD driver internal resource structure + * + * @dcomm_base: Pointer for register of PIDCOMM + * @dsp_base: Pointer for register of DSP + * @comm_base: Pointer for communication register + * @status: information of DSP + * @target_bit: bit pattern for DSP channel + * @clear_bit: bit pattern for clearing INT_MASK + */ +struct hwd_dspif_resources { + void __iomem *dcomm_base; + void __iomem *dsp_base; + void __iomem *comm_base; + struct hwd_dspif_status status; + u32 target_bit; + u32 clear_bit; +}; + +/* HWD driver internal resource */ +static struct hwd_dspif_resources hwd_dspif_resources[HWD_DSPIF_DEVICE_MAX] = { + /* Device 0 */ + { + .target_bit = BIT(0), + .clear_bit = BIT(0 + HWD_DSPIF_DCOMM_UNMASK_SHIFT), + }, + /* Device 1 */ + { + .target_bit = BIT(1), + .clear_bit = BIT(1 + HWD_DSPIF_DCOMM_UNMASK_SHIFT), + }, + /* Device 2 */ + { + .target_bit = BIT(2), + .clear_bit = BIT(2 + HWD_DSPIF_DCOMM_UNMASK_SHIFT), + }, + /* Device 3 */ + { + .target_bit = BIT(3), + .clear_bit = BIT(3 + HWD_DSPIF_DCOMM_UNMASK_SHIFT), + }, +}; + +/** + * hwd_dspif_descriptor_copy() - Copy Descriptor + * + * @comm_base: destination area of msg + * @src: msg in descriptor + */ +static void hwd_dspif_descriptor_copy(void __iomem *comm_base, const struct hwd_dspif_msg *src) +{ + /* copy message area */ + memcpy_toio(comm_base, src, sizeof(*src)); + + /* Initialize area of response from DSP */ + writel(0, comm_base + COMM_DSPIF_MSG_ERROR); +} + +/** + * hwd_dspif_initialize() - Initialize DSP device + * + * @module_id: id of the h/w module + * @dcomm_reg_vaddr: PIDCOMM register base address (virtual address) + * @dsp_reg_vaddr: DSP register base address (virtual address) + * @comm_vaddr: communication area address (virtual address) + */ +void hwd_dspif_initialize(u32 module_id, void __iomem *dcomm_reg_vaddr, void __iomem *dsp_reg_vaddr, + void __iomem *comm_vaddr) +{ + struct hwd_dspif_resources *res; + + res = &hwd_dspif_resources[module_id]; + res->dcomm_base = dcomm_reg_vaddr; + res->dsp_base = dsp_reg_vaddr; + res->comm_base = comm_vaddr; +} + +/** + * hwd_dspif_uninitialize() - Uninitialize DSP device + * + * @module_id: id of the h/w module + */ +void hwd_dspif_uninitialize(u32 module_id) +{ + struct hwd_dspif_resources *res; + + res = &hwd_dspif_resources[module_id]; + res->dcomm_base = NULL; + res->dsp_base = NULL; + res->comm_base = NULL; +} + +/** + * hwd_dspif_start() - Start DSP device + * + * @module_id: id of the h/w module + * @desc: Pointer to descriptor structure + * + * Host processor (CA53) and DSPs are connected + * via an interrupt controller (DCOMM) + * + * usage of DCOMM: + * + * * DCOMM_INT_CLR_RRR_D16(id): id=0,1,2,3 + * * register to clear interrupt to CA53 from DSP(id) + * * bit0-7; set 1 to clear interrupt from DSP; bit0 from DSP0, bit1 from DSP1, ... + * * DCOMM_INT_CLR_R04_DDD(id): id=0,1,2,3 + * * register to clear interrupt to DSP(id) from CA53 + * * bit0: set 1 to clear interrupt to DSP + * * bit1-7: (reserved) + * * DCOMM_INT_MSK_RRR_D16(id): id=0,1,2,3 + * * register to mask interrupt to CA53 from DSP(id) + * * bit0-7: set 1 to mask interrupt; bit0 from DSP0, bit1 from DSP1, ... + * * bit16-23: set 1 to UNMASK interrupt; bit16 from DSP0, bit17 from DSP1, ... + * * DCOMM_INT_MSK_R04_DDD(id): id=0,1,2,3 + * * register to mask interrupt to DSP(id) from CA53 + * * bit0: set 1 to mask interrupt + * * bit16: set 1 to UNMASK interrupt + * * DCOMM_INT_SET_RRR_D16(id): id=0,1,2,3 + * * FYI: register to issue interrupt to CA53 from DSP(id) + * * FYI: bit0: set by DSP0; set 1 to issue interrupt GIC_SPI 180 + * * FYI: bit1: set by DSP1; set 1 to issue interrupt GIC_SPI 181 + * * FYI: bit2: set by DSP2; set 1 to issue interrupt GIC_SPI 182 + * * FYI: bit3: set by DSP3; set 1 to issue interrupt GIC_SPI 183 + * * DCOMM_INT_SET_R04_DDD(id): id=0,1,2,3 + * * register to issue interrupt to DSP(id) from CA53 + * * bit0: issue interrupt to DSP + * * bit1-7: (reserved) + * + */ +void hwd_dspif_start(u32 module_id, const struct hwd_dspif_descriptor *desc) +{ + struct hwd_dspif_resources *res; + void __iomem *dcomm_base; + void __iomem *dsp_base; + + res = &hwd_dspif_resources[module_id]; + dcomm_base = res->dcomm_base; + dsp_base = res->dsp_base; + + /* Initialize error code from DSP */ + res->status.error = 0; + + /* Copy to communication area with user provided values */ + hwd_dspif_descriptor_copy(res->comm_base, &desc->msg); + + /* Select firmware */ + writel(desc->fw_addr, dsp_base + DSP_RESET_VECTOR); + + /* Set arbitration parameter */ + writel(HWD_DSP_ARB_XTS, dsp_base + DSP_ARB_XTS_PRIORITY); + writel(HWD_DSP_ARB_DMA, dsp_base + DSP_ARB_DMA_PRIORITY); + + /* Clear interrupt causes */ + writel(res->target_bit, dcomm_base + DCOMM_INT_CLR_RRR_D16(module_id)); + writel(HWD_DSPIF_DCOMM_SEND_BIT, dcomm_base + DCOMM_INT_CLR_R04_DDD(module_id)); + + /* UNMASK interrupt */ + writel(res->clear_bit, dcomm_base + DCOMM_INT_MSK_RRR_D16(module_id)); + writel(HWD_DSPIF_DCOMM_UNMASK_SEND, dcomm_base + DCOMM_INT_MSK_R04_DDD(module_id)); + + dsb(st); + + /* Signal to DSP by DCOMM */ + writel(HWD_DSPIF_DCOMM_SEND_BIT, dcomm_base + DCOMM_INT_SET_R04_DDD(module_id)); +} + +/** + * hwd_dspif_stop() - Stop DSP device + * + * @module_id: id of the h/w module + */ +void hwd_dspif_stop(u32 module_id) +{ + const struct hwd_dspif_resources *res = &hwd_dspif_resources[module_id]; + void __iomem *dcomm_base = res->dcomm_base; + + /* Mask Interrupt from/to DSP */ + writel(res->target_bit, dcomm_base + DCOMM_INT_MSK_RRR_D16(module_id)); + writel(HWD_DSPIF_DCOMM_MASK_SEND, dcomm_base + DCOMM_INT_MSK_R04_DDD(module_id)); +} + +/** + * hwd_dspif_irq_handler() - HWD DSPIF interrupt handler + * + * @module_id: id of the h/w module + * Return: HWD_DSPIF_EVENT_DONE DSP processing is completed + * Return: HWD_DSPIF_EVENT_ERROR DSP processing is failed + */ +u32 hwd_dspif_irq_handler(u32 module_id) +{ + struct hwd_dspif_resources *res = &hwd_dspif_resources[module_id]; + void __iomem *dcomm_base = res->dcomm_base; + u32 event; + s32 error; + + /* Clear interrupt causes */ + writel(res->target_bit, dcomm_base + DCOMM_INT_CLR_RRR_D16(module_id)); + + /* This error field is written by DSP */ + /* this addr has __iommmu and __le32 attributes */ + error = (s32)le32_to_cpu((__force __le32)readl(res->comm_base + COMM_DSPIF_MSG_ERROR)); + + /* if error is zero, event is DONE else ERROR */ + event = (error == 0) ? HWD_DSPIF_EVENT_DONE : HWD_DSPIF_EVENT_ERROR; + + /* save error value */ + res->status.error = error; + + return event; +} + +/** + * hwd_dspif_get_status() - HWD DSPIF Get Status + * + * @module_id: number of the h/w module + * @status: Pointer to status structure + */ +void hwd_dspif_get_status(u32 module_id, struct hwd_dspif_status *status) +{ + const struct hwd_dspif_resources *res = &hwd_dspif_resources[module_id]; + + /* return saved status */ + status->error = res->status.error; +} diff --git a/drivers/misc/visconti/dspif/hwd_dspif.h b/drivers/misc/visconti/dspif/hwd_dspif.h new file mode 100644 index 000000000..ac252786f --- /dev/null +++ b/drivers/misc/visconti/dspif/hwd_dspif.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +/* Toshiba Visconti DSPIF Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#ifndef HWD_DSPIF_H +#define HWD_DSPIF_H + +#include <linux/errno.h> +#include <linux/types.h> + +enum hwd_power_ctrl { HWD_POWER_OFF = 0, HWD_POWER_ON = 1 }; + +#define HWD_DSPIF_EVENT_DONE BIT(0) +#define HWD_DSPIF_EVENT_ERROR BIT(1) + +#define HWD_DSPIF_NUM_ARG_IMM (8) +#define HWD_DSPIF_NUM_ARG_REF (4) +#define HWD_DSPIF_NUM_ARG_IMG (6) + +/** + * enum hwd_dspif_module_id - ID for each DSPIF device + */ +enum hwd_dspif_module_id { + HWD_DSPIF_DEVICE_0 = 0, + HWD_DSPIF_DEVICE_1 = 1, + HWD_DSPIF_DEVICE_2 = 2, + HWD_DSPIF_DEVICE_3 = 3, + HWD_DSPIF_DEVICE_MAX = 4 +}; + +/** + * struct hwd_dspif_status - DSPIF HWD Driver Status + * @error: Return value from DSP F/W + */ +struct hwd_dspif_status { + s32 error; +}; + +/** + * struct hwd_dspif_msg - DSP message structure + * + * The hwd_dspif_msg instance is passed to DSP via memory block on DRAM. + * Therefore, each integer members should be cared their endianess. + * + * @id: u32 le. Function ID, Defined by DSP FW + * @error: s32 le. Reserved area for return value of DSP FW + * @imm: Argument for immediate value + * @imm.value: s64 le. Immediate value + * @ref: Argument for reference address + * @ref.address: u64 le. Address + * @ref.size: u64 le. Size of area specified by address + * @img: Image information + * @img.address: u64 le. Address of image data + * @img.width: s32 le. Width of image data + * @img.height: s32 le. Height of image data + * @img.pitch: s32 le. Pitch of image data + * @img.type: u32 le. Type format of image data [0x01, 0x02, 0x81, 0x82, 0x04, 0x84, 0x08, 0x88] + */ +struct hwd_dspif_msg { + __le32 id; + __le32 error; + struct { + __le64 value; + } imm[HWD_DSPIF_NUM_ARG_IMM]; + struct { + __le64 address; + __le64 size; + } ref[HWD_DSPIF_NUM_ARG_REF]; + struct { + __le64 address; + __le32 width; + __le32 height; + __le32 pitch; + __le32 type; + } img[HWD_DSPIF_NUM_ARG_IMG]; +}; + +/** + * struct hwd_dspif_descriptor - HWD DSPIF Descriptor + * + * @msg: Message structure to DSP + * @fw_addr: Firmware address + */ +struct hwd_dspif_descriptor { + struct hwd_dspif_msg msg; + u32 fw_addr; +}; + +void hwd_dspif_initialize(u32 module_id, void __iomem *dcomm_reg_vaddr, void __iomem *dsp_reg_vaddr, + void __iomem *comm_vaddr); +void hwd_dspif_uninitialize(u32 module_id); +void hwd_dspif_start(u32 module_id, const struct hwd_dspif_descriptor *desc); +void hwd_dspif_stop(u32 module_id); +u32 hwd_dspif_irq_handler(u32 module_id); +void hwd_dspif_get_status(u32 module_id, struct hwd_dspif_status *status); + +#endif /* HWD_DSPIF_H */ diff --git a/include/uapi/linux/visconti-dspif.h b/include/uapi/linux/visconti-dspif.h new file mode 100644 index 000000000..1de51b8f6 --- /dev/null +++ b/include/uapi/linux/visconti-dspif.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* Toshiba Visconti DSPIF Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#ifndef _UAPI_LINUX_DSPIF_H +#define _UAPI_LINUX_DSPIF_H + +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/visconti-ipa.h> + +#define DRV_DSPIF_BUFFER_INDEX_MAX (15) + +#define DRV_DSPIF_EVENT_DONE (1U) +#define DRV_DSPIF_EVENT_ERROR (2U) +#define DRV_DSPIF_EVENT_HW_ERROR (3U) + +#define DRV_DSPIF_NUM_ARG_IMM (8) +#define DRV_DSPIF_NUM_ARG_REF (4) +#define DRV_DSPIF_NUM_ARG_IMG (6) + +/** + * struct drv_dspif_status - DSPIF IPA descriptor for IOC_IPA_START + * @state: A &enum drv_ipa_state value for the state of driver + * @error: Return value from DSP firmware + */ +struct drv_dspif_status { + __u32 state; + __s32 error; +}; + +/** + * struct drv_dspif_msg - Message structure + * @id: Function ID, Defined by DSP FW + * @error: Reserved area for return value of DSP FW + * @imm: Argument for immediate value + * @imm.value: Immediate value + * @ref: Argument for reference address + * @ref.address: Address + * @ref.size: Size of area specified by address + * @img: Image information + * @img.address: Address of image data + * @img.width: Width of image data + * @img.height: Height of image data + * @img.pitch: Pitch of image data + * @img.type: Type format of image data; + * U8(0x01), S8(0x81), U16(0x02), S16(0x82), U32(0x04), S32(0x84), S64(0x88) + */ +struct drv_dspif_msg { + __u32 id; + __s32 error; + struct { + __s64 value; + } imm[DRV_DSPIF_NUM_ARG_IMM]; + struct { + struct drv_ipa_addr address; + __u64 size; + } ref[DRV_DSPIF_NUM_ARG_REF]; + struct { + struct drv_ipa_addr address; + __s32 width; + __s32 height; + __s32 pitch; + __u32 type; + } img[DRV_DSPIF_NUM_ARG_IMG]; +}; + +/** + * struct drv_dspif_descriptor - DSPIF IPA descriptor for IOC_IPA_START + * @msg: Message structure to DSP + * @fw_addr: Firmware address + * @buffer_info: Table of buffer information + * @buffer_info_num: Number of buffer_info + */ +struct drv_dspif_descriptor { + struct drv_dspif_msg msg; + __u32 fw_addr; + struct drv_ipa_buffer_info buffer_info[DRV_DSPIF_BUFFER_INDEX_MAX]; + __u32 buffer_info_num; +}; + +#endif /* _UAPI_LINUX_DSPIF_H */ diff --git a/include/uapi/linux/visconti-ipa.h b/include/uapi/linux/visconti-ipa.h new file mode 100644 index 000000000..f233d8302 --- /dev/null +++ b/include/uapi/linux/visconti-ipa.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ +/* Toshiba Visconti Image Processing Accelerator Support + * + * (C) Copyright 2022 TOSHIBA CORPORATION + * (C) Copyright 2022 Toshiba Electronic Devices & Storage Corporation + */ + +#ifndef _UAPI_LINUX_IPA_H +#define _UAPI_LINUX_IPA_H + +#include <linux/types.h> + +/** + * enum drv_ipa_state - state of Visconti IPA driver + * + * @DRV_IPA_STATE_IDLE: driver is idle + * @DRV_IPA_STATE_BUSY: device is busy + */ +enum drv_ipa_state { DRV_IPA_STATE_IDLE = 0, DRV_IPA_STATE_BUSY }; + +/** + * enum drv_ipa_buffer_direction - usage of buffer + * + * @DRV_IPA_DIR_BIDIRECTION: cpu writes/reads data + * @DRV_IPA_DIR_TO_DEVICE: cpu writes data + * @DRV_IPA_DIR_FROM_DEVICE: cpu reads data + * @DRV_IPA_DIR_NONE: cpu not access or non-coherent + */ +enum drv_ipa_buffer_direction { + DRV_IPA_DIR_BIDIRECTION = 0, + DRV_IPA_DIR_TO_DEVICE, + DRV_IPA_DIR_FROM_DEVICE, + DRV_IPA_DIR_NONE +}; + +/** + * struct drv_ipa_buffer_info - buffer information for Visconti IPA drivers + * + * @fd: file descriptor of a dma-buf heap instance + * @flags: optional flags for attributes of the buffer + * @direction: A &enum drv_ipa_buffer_direction value + * for buffer direction (to/from device) + */ +struct drv_ipa_buffer_info { + __u32 fd; + __u32 flags; + __u32 direction; +}; + +/** + * struct drv_ipa_addr - address structure for Visconti IPA drivers + * + * @buffer_index: array index of &struct drv_ipa_buffer_info + * @offset: offset from the top of the heap instance + */ +struct drv_ipa_addr { + __u32 buffer_index; + __u32 offset; +}; + +#define IPA_BUFFER_INDEX_MAX (16) +#define IPA_INVALID_ADDR \ + { \ + .buffer_index = 0xffffffffu, .offset = 0xffffffffu \ + } + +static inline struct drv_ipa_addr drv_ipa_invalid_addr(void) +{ + struct drv_ipa_addr invalid_addr = IPA_INVALID_ADDR; + return invalid_addr; +} + +static inline bool drv_ipa_is_invalid_addr(struct drv_ipa_addr addr) +{ + struct drv_ipa_addr invalid_addr = IPA_INVALID_ADDR; + + if (addr.buffer_index == invalid_addr.buffer_index && addr.offset == invalid_addr.offset) { + return true; + } + return false; +} + +#define IOC_IPA_MAGIC 'I' +#define IOC_IPA_START _IO(IOC_IPA_MAGIC, 0) +#define IOC_IPA_GET_STATUS _IO(IOC_IPA_MAGIC, 1) + +#endif /* _UAPI_LINUX_IPA_H */ -- 2.17.1

2 years, 5 months

[PATCH] dma-buf: heaps: Fix comment typo

by Jason Wang

The double `by' is duplicated in the comment, remove one. Signed-off-by: Jason Wang <wangborong(a)cdjrlc.com> --- drivers/dma-buf/heaps/cma_heap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma-buf/heaps/cma_heap.c b/drivers/dma-buf/heaps/cma_heap.c index 28fb04eccdd0..cd386ce639f3 100644 --- a/drivers/dma-buf/heaps/cma_heap.c +++ b/drivers/dma-buf/heaps/cma_heap.c @@ -316,7 +316,7 @@ static struct dma_buf *cma_heap_allocate(struct dma_heap *heap, kunmap_atomic(vaddr); /* * Avoid wasting time zeroing memory if the process - * has been killed by by SIGKILL + * has been killed by SIGKILL */ if (fatal_signal_pending(current)) goto free_cma; -- 2.35.1

2 years, 5 months

[PATCH] [Draft]: media: videobuf2-dma-heap: add a vendor defined memory runtine

by ayaka＠soulik.info

From: Randy Li <ayaka(a)soulik.info> This module is still at a early stage, I wrote this for showing what APIs we need here. Let me explain why we need such a module here. If you won't allocate buffers from a V4L2 M2M device, this module may not be very useful. I am sure the most of users won't know a device would require them allocate buffers from a DMA-Heap then import those buffers into a V4L2's queue. Then the question goes back to why DMA-Heap. From the Android's description, we know it is about the copyright's DRM. When we allocate a buffer in a DMA-Heap, it may register that buffer in the trusted execution environment so the firmware which is running or could only be acccesed from there could use that buffer later. The answer above leads to another thing which is not done in this version, the DMA mapping. Although in some platforms, a DMA-Heap responses a IOMMU device as well. For the genernal purpose, we would be better assuming the device mapping should be done for each device itself. The problem here we only know alloc_devs in those DMAbuf methods, which are DMA-heaps in my design, the device from the queue is not enough, a plane may requests another IOMMU device or table for mapping. Signed-off-by: Randy Li <ayaka(a)soulik.info> --- drivers/media/common/videobuf2/Kconfig | 6 + drivers/media/common/videobuf2/Makefile | 1 + .../common/videobuf2/videobuf2-dma-heap.c | 350 ++++++++++++++++++ include/media/videobuf2-dma-heap.h | 30 ++ 4 files changed, 387 insertions(+) create mode 100644 drivers/media/common/videobuf2/videobuf2-dma-heap.c create mode 100644 include/media/videobuf2-dma-heap.h diff --git a/drivers/media/common/videobuf2/Kconfig b/drivers/media/common/videobuf2/Kconfig index d2223a12c95f..02235077f07e 100644 --- a/drivers/media/common/videobuf2/Kconfig +++ b/drivers/media/common/videobuf2/Kconfig @@ -30,3 +30,9 @@ config VIDEOBUF2_DMA_SG config VIDEOBUF2_DVB tristate select VIDEOBUF2_CORE + +config VIDEOBUF2_DMA_HEAP + tristate + select VIDEOBUF2_CORE + select VIDEOBUF2_MEMOPS + select DMABUF_HEAPS diff --git a/drivers/media/common/videobuf2/Makefile b/drivers/media/common/videobuf2/Makefile index a6fe3f304685..7fe65f93117f 100644 --- a/drivers/media/common/videobuf2/Makefile +++ b/drivers/media/common/videobuf2/Makefile @@ -10,6 +10,7 @@ endif # (e. g. LC_ALL=C sort Makefile) obj-$(CONFIG_VIDEOBUF2_CORE) += videobuf2-common.o obj-$(CONFIG_VIDEOBUF2_DMA_CONTIG) += videobuf2-dma-contig.o +obj-$(CONFIG_VIDEOBUF2_DMA_HEAP) += videobuf2-dma-heap.o obj-$(CONFIG_VIDEOBUF2_DMA_SG) += videobuf2-dma-sg.o obj-$(CONFIG_VIDEOBUF2_DVB) += videobuf2-dvb.o obj-$(CONFIG_VIDEOBUF2_MEMOPS) += videobuf2-memops.o diff --git a/drivers/media/common/videobuf2/videobuf2-dma-heap.c b/drivers/media/common/videobuf2/videobuf2-dma-heap.c new file mode 100644 index 000000000000..377b82ab8f5a --- /dev/null +++ b/drivers/media/common/videobuf2/videobuf2-dma-heap.c @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2022 Randy Li <ayaka(a)soulik.info> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/dma-buf.h> +#include <linux/dma-heap.h> +#include <linux/refcount.h> +#include <linux/scatterlist.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/dma-mapping.h> + +#include <media/videobuf2-v4l2.h> +#include <media/videobuf2-memops.h> +#include <media/videobuf2-dma-heap.h> + +struct vb2_dmaheap_buf { + struct device *dev; + void *vaddr; + unsigned long size; + struct dma_buf *dmabuf; + dma_addr_t dma_addr; + unsigned long attrs; + enum dma_data_direction dma_dir; + struct sg_table *dma_sgt; + + /* MMAP related */ + struct vb2_vmarea_handler handler; + refcount_t refcount; + + /* DMABUF related */ + struct dma_buf_attachment *db_attach; +}; + +/*********************************************/ +/* callbacks for all buffers */ +/*********************************************/ + +void *vb2_dmaheap_cookie(struct vb2_buffer *vb, void *buf_priv) +{ + struct vb2_dmaheap_buf *buf = buf_priv; + + return &buf->dma_addr; +} + +static void *vb2_dmaheap_vaddr(struct vb2_buffer *vb, void *buf_priv) +{ + struct vb2_dmaheap_buf *buf = buf_priv; + struct iosys_map map; + + if (buf->vaddr) + return buf->vaddr; + + if (buf->db_attach) { + if (!dma_buf_vmap(buf->db_attach->dmabuf, &map)) + buf->vaddr = map.vaddr; + } + + return buf->vaddr; +} + +static unsigned int vb2_dmaheap_num_users(void *buf_priv) +{ + struct vb2_dmaheap_buf *buf = buf_priv; + + return refcount_read(&buf->refcount); +} + +static void vb2_dmaheap_prepare(void *buf_priv) +{ + struct vb2_dmaheap_buf *buf = buf_priv; + + /* TODO: DMABUF exporter will flush the cache for us */ + if (buf->db_attach) + return; + + dma_buf_end_cpu_access(buf->dmabuf, buf->dma_dir); +} + +static void vb2_dmaheap_finish(void *buf_priv) +{ + struct vb2_dmaheap_buf *buf = buf_priv; + + /* TODO: DMABUF exporter will flush the cache for us */ + if (buf->db_attach) + return; + + dma_buf_begin_cpu_access(buf->dmabuf, buf->dma_dir); +} + +/*********************************************/ +/* callbacks for MMAP buffers */ +/*********************************************/ + +void vb2_dmaheap_put(void *buf_priv) +{ + struct vb2_dmaheap_buf *buf = buf_priv; + + if (!refcount_dec_and_test(&buf->refcount)) + return; + + dma_buf_put(buf->dmabuf); + + put_device(buf->dev); + kfree(buf); +} + +static void *vb2_dmaheap_alloc(struct vb2_buffer *vb, + struct device *dev, + unsigned long size) +{ + struct vb2_queue *q = vb->vb2_queue; + struct dma_heap *heap; + struct vb2_dmaheap_buf *buf; + const char *heap_name; + int ret; + + if (WARN_ON(!dev)) + return ERR_PTR(-EINVAL); + + heap_name = dev_name(dev); + if (!heap_name) + return ERR_PTR(-EINVAL); + + heap = dma_heap_find(heap_name); + if (!heap) { + dev_err(dev, "is not a DMA-heap device\n"); + return ERR_PTR(-EINVAL); + } + + buf = kzalloc(sizeof *buf, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + /* Prevent the device from being released while the buffer is used */ + buf->dev = get_device(dev); + buf->attrs = vb->vb2_queue->dma_attrs; + buf->dma_dir = vb->vb2_queue->dma_dir; + + /* TODO: heap flags */ + ret = dma_heap_buffer_alloc(heap, size, 0, 0); + if (ret < 0) { + dev_err(dev, "is not a DMA-heap device\n"); + put_device(buf->dev); + kfree(buf); + return ERR_PTR(ret); + } + buf->dmabuf = dma_buf_get(ret); + + /* FIXME */ + buf->dma_addr = 0; + + if ((q->dma_attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0) + buf->vaddr = buf->dmabuf; + + buf->handler.refcount = &buf->refcount; + buf->handler.put = vb2_dmaheap_put; + buf->handler.arg = buf; + + refcount_set(&buf->refcount, 1); + + return buf; +} + +static int vb2_dmaheap_mmap(void *buf_priv, struct vm_area_struct *vma) +{ + struct vb2_dmaheap_buf *buf = buf_priv; + int ret; + + if (!buf) { + printk(KERN_ERR "No buffer to map\n"); + return -EINVAL; + } + + vma->vm_flags &= ~VM_PFNMAP; + + ret = dma_buf_mmap(buf->dmabuf, vma, 0); + if (ret) { + pr_err("Remapping memory failed, error: %d\n", ret); + return ret; + } + vma->vm_flags |= VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_private_data = &buf->handler; + vma->vm_ops = &vb2_common_vm_ops; + + vma->vm_ops->open(vma); + + pr_debug("%s: mapped memid 0x%08lx at 0x%08lx, size %ld\n", + __func__, (unsigned long)buf->dma_addr, vma->vm_start, + buf->size); + + return 0; +} + +/*********************************************/ +/* DMABUF ops for exporters */ +/*********************************************/ + +static struct dma_buf *vb2_dmaheap_get_dmabuf(struct vb2_buffer *vb, + void *buf_priv, + unsigned long flags) +{ + struct vb2_dmaheap_buf *buf = buf_priv; + struct dma_buf *dbuf; + + dbuf = buf->dmabuf; + + return dbuf; +} + +/*********************************************/ +/* callbacks for DMABUF buffers */ +/*********************************************/ + +static int vb2_dmaheap_map_dmabuf(void *mem_priv) +{ + struct vb2_dmaheap_buf *buf = mem_priv; + struct sg_table *sgt; + + if (WARN_ON(!buf->db_attach)) { + pr_err("trying to pin a non attached buffer\n"); + return -EINVAL; + } + + if (WARN_ON(buf->dma_sgt)) { + pr_err("dmabuf buffer is already pinned\n"); + return 0; + } + + /* get the associated scatterlist for this buffer */ + sgt = dma_buf_map_attachment(buf->db_attach, buf->dma_dir); + if (IS_ERR(sgt)) { + pr_err("Error getting dmabuf scatterlist\n"); + return -EINVAL; + } + + buf->dma_addr = sg_dma_address(sgt->sgl); + buf->dma_sgt = sgt; + buf->vaddr = NULL; + + return 0; +} + +static void vb2_dmaheap_unmap_dmabuf(void *mem_priv) +{ + struct vb2_dmaheap_buf *buf = mem_priv; + struct sg_table *sgt = buf->dma_sgt; + struct iosys_map map = IOSYS_MAP_INIT_VADDR(buf->vaddr); + + if (WARN_ON(!buf->db_attach)) { + pr_err("trying to unpin a not attached buffer\n"); + return; + } + + if (WARN_ON(!sgt)) { + pr_err("dmabuf buffer is already unpinned\n"); + return; + } + + if (buf->vaddr) { + dma_buf_vunmap(buf->db_attach->dmabuf, &map); + buf->vaddr = NULL; + } + dma_buf_unmap_attachment(buf->db_attach, sgt, buf->dma_dir); + + buf->dma_addr = 0; + buf->dma_sgt = NULL; +} + +static void vb2_dmaheap_detach_dmabuf(void *mem_priv) +{ + struct vb2_dmaheap_buf *buf = mem_priv; + + /* if vb2 works correctly you should never detach mapped buffer */ + if (WARN_ON(buf->dma_addr)) + vb2_dmaheap_unmap_dmabuf(buf); + + /* detach this attachment */ + dma_buf_detach(buf->db_attach->dmabuf, buf->db_attach); + kfree(buf); +} + +static void *vb2_dmaheap_attach_dmabuf(struct vb2_buffer *vb, struct device *dev, + struct dma_buf *dbuf, unsigned long size) +{ + struct vb2_dmaheap_buf *buf; + struct dma_buf_attachment *dba; + + if (dbuf->size < size) + return ERR_PTR(-EFAULT); + + if (WARN_ON(!dev)) + return ERR_PTR(-EINVAL); + /* + * TODO: A better way to check whether the buffer is coming + * from this heap or this heap could accept this buffer + */ + if (strcmp(dbuf->exp_name, dev_name(dev))) + return ERR_PTR(-EINVAL); + + buf = kzalloc(sizeof(*buf), GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + buf->dev = dev; + /* create attachment for the dmabuf with the user device */ + dba = dma_buf_attach(dbuf, buf->dev); + if (IS_ERR(dba)) { + pr_err("failed to attach dmabuf\n"); + kfree(buf); + return dba; + } + + buf->dma_dir = vb->vb2_queue->dma_dir; + buf->size = size; + buf->db_attach = dba; + + return buf; +} + +const struct vb2_mem_ops vb2_dmaheap_memops = { + .alloc = vb2_dmaheap_alloc, + .put = vb2_dmaheap_put, + .get_dmabuf = vb2_dmaheap_get_dmabuf, + .cookie = vb2_dmaheap_cookie, + .vaddr = vb2_dmaheap_vaddr, + .prepare = vb2_dmaheap_prepare, + .finish = vb2_dmaheap_finish, + .map_dmabuf = vb2_dmaheap_map_dmabuf, + .unmap_dmabuf = vb2_dmaheap_unmap_dmabuf, + .attach_dmabuf = vb2_dmaheap_attach_dmabuf, + .detach_dmabuf = vb2_dmaheap_detach_dmabuf, + .num_users = vb2_dmaheap_num_users, + .mmap = vb2_dmaheap_mmap, +}; + +MODULE_DESCRIPTION("DMA-Heap memory handling routines for videobuf2"); +MODULE_AUTHOR("Randy Li <ayaka(a)soulik.info>"); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(DMA_BUF); diff --git a/include/media/videobuf2-dma-heap.h b/include/media/videobuf2-dma-heap.h new file mode 100644 index 000000000000..fa057f67d6e9 --- /dev/null +++ b/include/media/videobuf2-dma-heap.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2022 Randy Li <ayaka(a)soulik.info> + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MEDIA_VIDEOBUF2_DMA_HEAP_H +#define _MEDIA_VIDEOBUF2_DMA_HEAP_H + +#include <media/videobuf2-v4l2.h> +#include <linux/dma-mapping.h> + +static inline dma_addr_t +vb2_dmaheap_plane_dma_addr(struct vb2_buffer *vb, unsigned int plane_no) +{ + dma_addr_t *addr = vb2_plane_cookie(vb, plane_no); + + return *addr; +} + +extern const struct vb2_mem_ops vb2_dmaheap_memops; +#endif -- 2.17.1

2 years, 5 months

[PATCH v3 0/6] drm/i915: reduce TLB performance regressions

by Mauro Carvalho Chehab

Doing TLB invalidation cause performance regressions, like: [424.370996] i915 0000:00:02.0: [drm] *ERROR* rcs0 TLB invalidation did not complete in 4ms! As reported at: https://gitlab.freedesktop.org/drm/intel/-/issues/6424 as this is an expensive operation. So, reduce the need of it by: - checking if the engine is awake; - checking if the engine is not wedged; - batching operations. Additionally, add a workaround for a known hardware issue on some GPUs. In order to double-check that this series won't be introducing any regressions, I used this new IGT test: https://patchwork.freedesktop.org/patch/495684/?series=106757&rev=1 Checking the results for 3 different patchsets, on Broadwell: 1) On the top of drm-tip (2022y-07m-14d-08h-35m-36) - e. g. with TLB invalidation and serialization patches: $ sudo build/tests/gem_exec_tlb|grep Subtest Subtest close-clear: SUCCESS (10.490s) Subtest madv-clear: SUCCESS (10.484s) Subtest u-unmap-clear: SUCCESS (10.527s) Subtest u-shrink-clear: SUCCESS (10.506s) Subtest close-dumb: SUCCESS (10.165s) Subtest madv-dumb: SUCCESS (10.177s) Subtest u-unmap-dumb: SUCCESS (10.172s) Subtest u-shrink-dumb: SUCCESS (10.172s) 2) With the new version of the batch TLB invalidation patches from this series: $ sudo build/tests/gem_exec_tlb|grep Subtest Subtest close-clear: SUCCESS (10.483s) Subtest madv-clear: SUCCESS (10.495s) Subtest u-unmap-clear: SUCCESS (10.545s) Subtest u-shrink-clear: SUCCESS (10.508s) Subtest close-dumb: SUCCESS (10.172s) Subtest madv-dumb: SUCCESS (10.169s) Subtest u-unmap-dumb: SUCCESS (10.174s) Subtest u-shrink-dumb: SUCCESS (10.176s) 3) Changing the TLB invalidation routine to do nothing[1]: $ sudo ~/freedesktop-igt/build/tests/gem_exec_tlb|grep Subtest (gem_exec_tlb:1958) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1958) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1958) CRITICAL: Found deadbeef in a new (clear) buffer after 3 tries! (gem_exec_tlb:1956) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1956) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1956) CRITICAL: Found deadbeef in a new (clear) buffer after 89 tries! (gem_exec_tlb:1957) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1957) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1957) CRITICAL: Found deadbeef in a new (clear) buffer after 256 tries! (gem_exec_tlb:1960) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1960) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1960) CRITICAL: Found deadbeef in a new (clear) buffer after 845 tries! (gem_exec_tlb:1961) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1961) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1961) CRITICAL: Found deadbeef in a new (clear) buffer after 1138 tries! (gem_exec_tlb:1954) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1954) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1954) CRITICAL: Found deadbeef in a new (clear) buffer after 1359 tries! (gem_exec_tlb:1955) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1955) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1955) CRITICAL: Found deadbeef in a new (clear) buffer after 1794 tries! (gem_exec_tlb:1959) CRITICAL: Test assertion failure function check_bo, file ../tests/i915/gem_exec_tlb.c:384: (gem_exec_tlb:1959) CRITICAL: Failed assertion: !sq (gem_exec_tlb:1959) CRITICAL: Found deadbeef in a new (clear) buffer after 2139 tries! Dynamic subtest smem0 failed. **** DEBUG **** (gem_exec_tlb:1944) DEBUG: 2M hole:200000 contains poison:6b6b6b6b (gem_exec_tlb:1944) DEBUG: Running writer for 200000 at 300000 on bcs0 (gem_exec_tlb:1944) DEBUG: Closing hole:200000 on rcs0, sample:deadbeef (gem_exec_tlb:1944) DEBUG: Rechecking hole:200000, sample:6b6b6b6b **** END **** Subtest close-clear: FAIL (10.434s) Subtest madv-clear: SUCCESS (10.479s) Subtest u-unmap-clear: SUCCESS (10.512s) In summary, the test does properly detect fail when TLB cache invalidation doesn't happen, as shown at result (3). It also shows that both current drm-tip and drm-tip with this series applied don't have TLB invalidation cache issues. [1] I applied this patch on the top of drm-tip: diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 68c2b0d8f187..0aefcd7be5e9 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -930,0 +931,3 @@ void intel_gt_invalidate_tlbs(struct intel_gt *gt) + // HACK: don't do TLB invalidations!!! + return; + Regards, Mauro Chris Wilson (4): drm/i915/gt: Ignore TLB invalidations on idle engines drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations drm/i915/gt: Skip TLB invalidations once wedged drm/i915/gt: Batch TLB invalidations Mauro Carvalho Chehab (2): drm/i915/gt: document with_intel_gt_pm_if_awake() drm/i915/gt: describe the new tlb parameter at i915_vma_resource .../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 25 +++--- drivers/gpu/drm/i915/gt/intel_gt.c | 77 +++++++++++++++---- drivers/gpu/drm/i915/gt/intel_gt.h | 12 ++- drivers/gpu/drm/i915/gt/intel_gt_pm.h | 11 +++ drivers/gpu/drm/i915/gt/intel_gt_types.h | 18 ++++- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 8 +- drivers/gpu/drm/i915/i915_vma.c | 33 ++++++-- drivers/gpu/drm/i915/i915_vma.h | 1 + drivers/gpu/drm/i915/i915_vma_resource.c | 9 ++- drivers/gpu/drm/i915/i915_vma_resource.h | 6 +- 11 files changed, 163 insertions(+), 40 deletions(-) -- 2.36.1

2 years, 5 months

[PATCH v2 0/5] Add Toshiba Visconti DNN image processing accelerator driver

by Yuji Ishikawa

This series is the DNN image processing accelerator driver for Toshiba's ARM SoC, Visconti[0]. This provides DT binding documentation, device driver, MAINTAINER files and documents. Best regards, Yuji [0]: https://toshiba.semicon-storage.com/ap-en/semiconductor/product/image-recog… dt-bindings: soc: visconti: Add Toshiba Visconti DNN image processing accelerator bindings v1 -> v2: - No update soc: visconti: Add Toshiba Visconti image processing accelerator common source v1 -> v2: - checked with checkpatch.pl --strict soc: visconti: Add Toshiba Visconti DNN image processing accelerator v1 -> v2: - checked with checkpatch.pl --strict - removed unused code MAINTAINERS: Add entries for Toshiba Visconti DNN image processing v1 -> v2: - No update Documentation: driver-api: visconti: add a description of DNN driver. v1 -> v2: - newly added documents Yuji Ishikawa (5): dt-bindings: soc: visconti: Add Toshiba Visconti DNN image processing accelerator bindings soc: visconti: Add Toshiba Visconti image processing accelerator common source soc: visconti: Add Toshiba Visconti DNN image processing accelerator MAINTAINERS: Add entries for Toshiba Visconti DNN image processing accelerator Documentation: driver-api: visconti: add a description of DNN driver. .../soc/visconti/toshiba,visconti-dnn.yaml | 54 ++ Documentation/driver-api/visconti/common.rst | 115 ++++ Documentation/driver-api/visconti/dnn.rst | 394 +++++++++++++ MAINTAINERS | 2 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/visconti/Kconfig | 7 + drivers/soc/visconti/Makefile | 8 + drivers/soc/visconti/dnn/Makefile | 6 + drivers/soc/visconti/dnn/dnn.c | 523 ++++++++++++++++++ drivers/soc/visconti/dnn/hwd_dnn.c | 183 ++++++ drivers/soc/visconti/dnn/hwd_dnn.h | 68 +++ drivers/soc/visconti/dnn/hwd_dnn_reg.h | 228 ++++++++ drivers/soc/visconti/ipa_common.c | 55 ++ drivers/soc/visconti/ipa_common.h | 18 + drivers/soc/visconti/uapi/dnn.h | 77 +++ drivers/soc/visconti/uapi/ipa.h | 90 +++ 17 files changed, 1830 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/visconti/toshiba,visconti-dnn.yaml create mode 100644 Documentation/driver-api/visconti/common.rst create mode 100644 Documentation/driver-api/visconti/dnn.rst create mode 100644 drivers/soc/visconti/Kconfig create mode 100644 drivers/soc/visconti/Makefile create mode 100644 drivers/soc/visconti/dnn/Makefile create mode 100644 drivers/soc/visconti/dnn/dnn.c create mode 100644 drivers/soc/visconti/dnn/hwd_dnn.c create mode 100644 drivers/soc/visconti/dnn/hwd_dnn.h create mode 100644 drivers/soc/visconti/dnn/hwd_dnn_reg.h create mode 100644 drivers/soc/visconti/ipa_common.c create mode 100644 drivers/soc/visconti/ipa_common.h create mode 100644 drivers/soc/visconti/uapi/dnn.h create mode 100644 drivers/soc/visconti/uapi/ipa.h -- 2.17.1

2 years, 5 months

[PATCH v2 00/21] Fix performance regressions with TLB and add GuC support

by Mauro Carvalho Chehab

TLB invalidation is a slow operation. It should not be doing lightly, as it causes performance regressions, like this: [178.821002] i915 0000:00:02.0: [drm] *ERROR* rcs0 TLB invalidation did not complete in 4ms! This series contain 1) some patches that makes TLB invalidation to happen only on active, non-wedged engines, doing cache invalidation in batch and only when GT objects are exposed to userspace: drm/i915/gt: Ignore TLB invalidations on idle engines drm/i915/gt: Only invalidate TLBs exposed to user manipulation drm/i915/gt: Skip TLB invalidations once wedged drm/i915/gt: Batch TLB invalidations drm/i915/gt: Move TLB invalidation to its own file 2) It fixes two bugs, being the first a workaround: drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations drm/i915: Invalidate the TLBs on each GT drm/i915/guc: Introduce TLB_INVALIDATION_ALL action 3) It adds GuC support. Besides providing TLB invalidation on some additional hardware, this should also help serializing GuC operations with TLB invalidation: drm/i915/guc: Introduce TLB_INVALIDATION_ALL action drm/i915/guc: Define CTB based TLB invalidation routines drm/i915: Add platform macro for selective tlb flush drm/i915: Define GuC Based TLB invalidation routines drm/i915: Add generic interface for tlb invalidation for XeHP drm/i915: Use selective tlb invalidations where supported 4) It adds the corresponding kernel-doc markups for the kAPI used for TLB invalidation. While I could have split this into smaller pieces, I'm opting to send them altogether, in order for CI trybot to better verify what issues will be closed with this series. --- v2: - no changes. Just rebased on the top of drm-tip: 2022y-07m-14d-08h-35m-36s, as CI trybot was having troubles applying it. Hopefully, it will now work. Chris Wilson (7): drm/i915/gt: Ignore TLB invalidations on idle engines drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations drm/i915/gt: Only invalidate TLBs exposed to user manipulation drm/i915/gt: Skip TLB invalidations once wedged drm/i915/gt: Batch TLB invalidations drm/i915/gt: Move TLB invalidation to its own file drm/i915: Invalidate the TLBs on each GT Mauro Carvalho Chehab (8): drm/i915/gt: document with_intel_gt_pm_if_awake() drm/i915/gt: describe the new tlb parameter at i915_vma_resource drm/i915/guc: use kernel-doc for enum intel_guc_tlb_inval_mode drm/i915/guc: document the TLB invalidation struct members drm/i915: document tlb field at struct drm_i915_gem_object drm/i915/gt: document TLB cache invalidation functions drm/i915/guc: describe enum intel_guc_tlb_invalidation_type drm/i915/guc: document TLB cache invalidation functions Piotr Piórkowski (1): drm/i915/guc: Introduce TLB_INVALIDATION_ALL action Prathap Kumar Valsan (5): drm/i915/guc: Define CTB based TLB invalidation routines drm/i915: Add platform macro for selective tlb flush drm/i915: Define GuC Based TLB invalidation routines drm/i915: Add generic interface for tlb invalidation for XeHP drm/i915: Use selective tlb invalidations where supported drivers/gpu/drm/i915/Makefile | 1 + .../gpu/drm/i915/gem/i915_gem_object_types.h | 6 +- drivers/gpu/drm/i915/gem/i915_gem_pages.c | 28 +- drivers/gpu/drm/i915/gt/intel_engine.h | 1 + drivers/gpu/drm/i915/gt/intel_gt.c | 125 +------- drivers/gpu/drm/i915/gt/intel_gt.h | 2 - .../gpu/drm/i915/gt/intel_gt_buffer_pool.h | 3 +- drivers/gpu/drm/i915/gt/intel_gt_defines.h | 11 + drivers/gpu/drm/i915/gt/intel_gt_pm.h | 10 + drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 + drivers/gpu/drm/i915/gt/intel_gt_types.h | 22 +- drivers/gpu/drm/i915/gt/intel_ppgtt.c | 8 +- drivers/gpu/drm/i915/gt/intel_tlb.c | 295 ++++++++++++++++++ drivers/gpu/drm/i915/gt/intel_tlb.h | 30 ++ .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 54 ++++ drivers/gpu/drm/i915/gt/uc/intel_guc.c | 232 ++++++++++++++ drivers/gpu/drm/i915/gt/uc/intel_guc.h | 36 +++ drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 24 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 9 + .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 91 +++++- drivers/gpu/drm/i915/i915_drv.h | 4 +- drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/i915_vma.c | 46 ++- drivers/gpu/drm/i915/i915_vma.h | 2 + drivers/gpu/drm/i915/i915_vma_resource.c | 9 +- drivers/gpu/drm/i915/i915_vma_resource.h | 6 +- drivers/gpu/drm/i915/intel_device_info.h | 1 + 27 files changed, 910 insertions(+), 155 deletions(-) create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_defines.h create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.c create mode 100644 drivers/gpu/drm/i915/gt/intel_tlb.h -- 2.36.1

2 years, 5 months

Re: [Intel-gfx] [PATCH v2 06/21] drm/i915/gt: Batch TLB invalidations

by Tvrtko Ursulin

On 20/07/2022 08:13, Mauro Carvalho Chehab wrote: > On Mon, 18 Jul 2022 14:52:05 +0100 > Tvrtko Ursulin <tvrtko.ursulin(a)linux.intel.com> wrote: > >> >> On 14/07/2022 13:06, Mauro Carvalho Chehab wrote: >>> From: Chris Wilson <chris.p.wilson(a)intel.com> >>> >>> Invalidate TLB in patch, in order to reduce performance regressions. >> >> "in batches"? > > Yeah. Will fix it. > >>> diff --git a/drivers/gpu/drm/i915/gt/intel_ppgtt.c b/drivers/gpu/drm/i915/gt/intel_ppgtt.c >>> index d8b94d638559..2da6c82a8bd2 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_ppgtt.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_ppgtt.c >>> @@ -206,8 +206,12 @@ void ppgtt_bind_vma(struct i915_address_space *vm, >>> void ppgtt_unbind_vma(struct i915_address_space *vm, >>> struct i915_vma_resource *vma_res) >>> { >>> - if (vma_res->allocated) >>> - vm->clear_range(vm, vma_res->start, vma_res->vma_size); >>> + if (!vma_res->allocated) >>> + return; >>> + >>> + vm->clear_range(vm, vma_res->start, vma_res->vma_size); >>> + if (vma_res->tlb) >>> + vma_invalidate_tlb(vm, *vma_res->tlb); >> >> The patch is about more than batching? If there is a security hole in >> this area (unbind) with the current code? > > No, I don't think there's a security hole. The rationale for this is > not due to it. In this case obvious question is why are these changes in the patch which declares itself to be about batching invalidations? Because... > Since commit 2f6b90da9192 ("drm/i915: Use vma resources for async unbinding"), > VMA unbind can happen either sync or async. > > So, the logic needs to do TLB invalidate on two places. After this > patch, the code at __i915_vma_evict is: > > struct dma_fence *__i915_vma_evict(struct i915_vma *vma, bool async) > { > ... > if (async) > unbind_fence = i915_vma_resource_unbind(vma_res, > &vma->obj->mm.tlb); > else > unbind_fence = i915_vma_resource_unbind(vma_res, NULL); > > vma->resource = NULL; > > atomic_and(~(I915_VMA_BIND_MASK | I915_VMA_ERROR | I915_VMA_GGTT_WRITE), > &vma->flags); > > i915_vma_detach(vma); > > if (!async) { > if (unbind_fence) { > dma_fence_wait(unbind_fence, false); > dma_fence_put(unbind_fence); > unbind_fence = NULL; > } > vma_invalidate_tlb(vma->vm, vma->obj->mm.tlb); > } > ... > > So, basically, if !async, __i915_vma_evict() will do TLB cache invalidation. > > However, when async is used, the actual page release will happen later, > at this function: > > void ppgtt_unbind_vma(struct i915_address_space *vm, > struct i915_vma_resource *vma_res) > { > if (!vma_res->allocated) > return; > > vm->clear_range(vm, vma_res->start, vma_res->vma_size); > if (vma_res->tlb) > vma_invalidate_tlb(vm, *vma_res->tlb); > } .. frankly I don't follow since I don't see any page release happening in here. Just PTE clearing. I am explaining why it looks to me that the patch is doing two things. Implementing batching _and_ adding invalidation points at VMA unbind sites, while so far we had it at backing store release only. Maybe I am wrong and perhaps I am too slow to pick up on the explanation here. So if the patch is doing two things please split it up. I am further confused by the invalidation call site in evict and in unbind - why there can't be one logical site since the logical sequence is evict -> unbind. Regards, Tvrtko

2 years, 5 months

[PATCH v1 0/6] Move all drivers to a common dma-buf locking convention

by Dmitry Osipenko

Hello, This series moves all drivers to a dynamic dma-buf locking specification. From now on all dma-buf importers are made responsible for holding dma-buf's reservation lock around all operations performed over dma-bufs. This common locking convention allows us to utilize reservation lock more broadly around kernel without fearing of potential dead locks. This patchset passes all i915 selftests. It was also tested using VirtIO, Panfrost, Lima and Tegra drivers. I tested cases of display+GPU, display+V4L and GPU+V4L dma-buf sharing, which covers majority of kernel drivers since rest of the drivers share same or similar code paths. This is a continuation of [1] where Christian König asked to factor out the dma-buf locking changes into separate series. [1] https://lore.kernel.org/dri-devel/20220526235040.678984-1-dmitry.osipenko@c… Dmitry Osipenko (6): dma-buf: Add _unlocked postfix to function names drm/gem: Take reservation lock for vmap/vunmap operations dma-buf: Move all dma-bufs to dynamic locking specification dma-buf: Acquire wait-wound context on attachment media: videobuf2: Stop using internal dma-buf lock dma-buf: Remove internal lock drivers/dma-buf/dma-buf.c | 198 +++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 +- drivers/gpu/drm/armada/armada_gem.c | 14 +- drivers/gpu/drm/drm_client.c | 4 +- drivers/gpu/drm/drm_gem.c | 28 +++ drivers/gpu/drm/drm_gem_cma_helper.c | 6 +- drivers/gpu/drm/drm_gem_framebuffer_helper.c | 6 +- drivers/gpu/drm/drm_gem_shmem_helper.c | 6 +- drivers/gpu/drm/drm_prime.c | 12 +- drivers/gpu/drm/etnaviv/etnaviv_gem_prime.c | 6 +- drivers/gpu/drm/exynos/exynos_drm_gem.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 20 +- .../gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_object.h | 6 +- .../drm/i915/gem/selftests/i915_gem_dmabuf.c | 20 +- drivers/gpu/drm/i915/i915_gem_evict.c | 2 +- drivers/gpu/drm/i915/i915_gem_ww.c | 26 ++- drivers/gpu/drm/i915/i915_gem_ww.h | 15 +- drivers/gpu/drm/omapdrm/omap_gem_dmabuf.c | 8 +- drivers/gpu/drm/qxl/qxl_object.c | 17 +- drivers/gpu/drm/qxl/qxl_prime.c | 4 +- drivers/gpu/drm/tegra/gem.c | 27 +-- drivers/infiniband/core/umem_dmabuf.c | 11 +- .../common/videobuf2/videobuf2-dma-contig.c | 26 +-- .../media/common/videobuf2/videobuf2-dma-sg.c | 23 +- .../common/videobuf2/videobuf2-vmalloc.c | 17 +- .../platform/nvidia/tegra-vde/dmabuf-cache.c | 12 +- drivers/misc/fastrpc.c | 12 +- drivers/xen/gntdev-dmabuf.c | 14 +- include/drm/drm_gem.h | 3 + include/linux/dma-buf.h | 49 ++--- 32 files changed, 347 insertions(+), 257 deletions(-) -- 2.36.1

2 years, 5 months

[BUG] most: usb: Found a bug at the probe time

by Zheyu Ma

Hello, I found a bug in the most usb driver. When the driver fails at mdev->conf = kcalloc(num_endpoints, sizeof(*mdev->conf), GFP_KERNEL); I got the following warning message: [ 15.406256] kobject: '(null)' (ffff8881068f8000): is not initialized, yet kobject_put() is being called. [ 15.406986] WARNING: CPU: 3 PID: 396 at lib/kobject.c:720 kobject_put+0x6e/0x1c0 [ 15.410120] RIP: 0010:kobject_put+0x6e/0x1c0 [ 15.410470] Code: 01 75 29 4c 89 f8 48 c1 e8 03 80 3c 28 00 74 08 4c 89 ff e8 14 2e 73 ff 49 8b 37 48 c7 c7 c0 fc de 85 4c 89 fa e8 e2 61 21 ff <0f> 0b 49 8d 5f 38 48 89 df be 04 00 00 00 e8 df 2e 73 ff b8 ff ff [ 15.416529] Call Trace: [ 15.416896] hdm_probe+0xf3d/0x1090 [most_usb] Since I'm not familiar with the driver, I ask for your help to solve the warning. regards, Zheyu Ma

2 years, 5 months

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