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On 1/14/26 12:46 AM, Tomeu Vizoso wrote:
> Using the DRM GPU scheduler infrastructure, with a scheduler for each
> core.
>
> Contexts are created in all cores, and buffers mapped to all of them as
> well, so all cores are ready to execute any job.
>
> The job submission code was initially based on Panfrost.
>
> v2:
> - Add thames_accel.h UAPI header (Robert Nelson).
>
> Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net>
> ---
> drivers/accel/thames/Makefile | 1 +
> drivers/accel/thames/thames_core.c | 6 +
> drivers/accel/thames/thames_drv.c | 19 ++
> drivers/accel/thames/thames_job.c | 463 ++++++++++++++++++++++++++++++++++++
> drivers/accel/thames/thames_job.h | 51 ++++
> drivers/accel/thames/thames_rpmsg.c | 52 ++++
> include/uapi/drm/thames_accel.h | 54 +++++
> 7 files changed, 646 insertions(+)
>
> diff --git a/include/uapi/drm/thames_accel.h b/include/uapi/drm/thames_accel.h
> index 0a5a5e5f6637ab474e9effbb6db29c1dd95e56b5..5b35e50826ed95bfcc3709bef33416d2b6d11c70 100644
> --- a/include/uapi/drm/thames_accel.h
> +++ b/include/uapi/drm/thames_accel.h
> @@ -75,6 +78,55 @@ struct drm_thames_bo_mmap_offset {
> __u64 offset;
> };
>
> +/**
> + * struct drm_thames_job - A job to be run on the NPU
> + *
> + * The kernel will schedule the execution of this job taking into account its
> + * dependencies with other jobs. All tasks in the same job will be executed
> + * sequentially on the same core, to benefit from memory residency in SRAM.
> + */
Please make these comments full-fledged kernel-doc comments.
E.g.:
> +struct drm_thames_job {
> + /** Input: BO handle for kernel. */
/** @kernel: input: BO handle for kernel. */
> + __u32 kernel;
> +
> + /** Input: Size in bytes of the compiled kernel. */
> + __u32 kernel_size;
> +
> + /** Input: BO handle for params BO. */
> + __u32 params;
> +
> + /** Input: Size in bytes of the params BO. */
> + __u32 params_size;
> +
> + /** Input: Pointer to a u32 array of the BOs that are read by the job. */
> + __u64 in_bo_handles;
> +
> + /** Input: Pointer to a u32 array of the BOs that are written to by the job. */
> + __u64 out_bo_handles;
> +
> + /** Input: Number of input BO handles passed in (size is that times 4). */
> + __u32 in_bo_handle_count;
> +
> + /** Input: Number of output BO handles passed in (size is that times 4). */
> + __u32 out_bo_handle_count;
> +};
> +
> +/**
> + * struct drm_thames_submit - ioctl argument for submitting commands to the NPU.
> + *
> + * The kernel will schedule the execution of these jobs in dependency order.
> + */
Same here.
> +struct drm_thames_submit {
> + /** Input: Pointer to an array of struct drm_thames_job. */
> + __u64 jobs;
> +
> + /** Input: Number of jobs passed in. */
> + __u32 job_count;
> +
> + /** Reserved, must be zero. */
> + __u32 pad;
> +};
> +
--
~Randy
On 1/14/26 2:46 AM, Tomeu Vizoso wrote:
> This memory region is used by the DRM/accel driver to allocate addresses
> for buffers that are used for communication with the DSP cores and for
> their intermediate results.
>
> Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net>
> ---
> arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi
> index 3fbff927c4c08bce741555aa2753a394b751144f..b80d2a5a157ad59eaed8e57b22f1f4bce4765a85 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-ti-ipc-firmware.dtsi
> @@ -42,6 +42,11 @@ c7x_0_memory_region: memory@a3100000 {
> no-map;
> };
>
> + c7x_iova_pool: iommu-pool@a7000000 {
> + reg = <0x00 0xa7000000 0x00 0x18200000>;
> + no-map;
Could you expand on why this carveout is needed? The C7 NPU has a full
MMU and should be able to work with any buffer Linux allocates from any
address, even non-contiguous buffers too.
Communication should already happen over the existing RPMSG channels
without needing extra buffers. And space for intermediate results
should be provided dynamically by the drivers (I believe that would
match how GPUs without dedicated memory handle getting intermediate
buffers space from system memory these days, but do correct me if
I'm wrong about that one).
Andrew
> + };
> +
> c7x_1_dma_memory_region: memory@a4000000 {
> compatible = "shared-dma-pool";
> reg = <0x00 0xa4000000 0x00 0x100000>;
> @@ -151,13 +156,15 @@ &main_r5fss0_core0 {
> &c7x_0 {
> mboxes = <&mailbox0_cluster2 &mbox_c7x_0>;
> memory-region = <&c7x_0_dma_memory_region>,
> - <&c7x_0_memory_region>;
> + <&c7x_0_memory_region>,
> + <&c7x_iova_pool>;
> status = "okay";
> };
>
> &c7x_1 {
> mboxes = <&mailbox0_cluster3 &mbox_c7x_1>;
> memory-region = <&c7x_1_dma_memory_region>,
> - <&c7x_1_memory_region>;
> + <&c7x_1_memory_region>,
> + <&c7x_iova_pool>;
> status = "okay";
> };
>
On Tue, 13 Jan 2026, Tomeu Vizoso <tomeu(a)tomeuvizoso.net> wrote:
> +#include "linux/dev_printk.h"
Random drive-by comment, please use <> instead of "" for include/
headers.
> +#include <drm/drm_file.h>
> +#include <drm/drm_gem.h>
> +#include <drm/drm_print.h>
> +#include <drm/thames_accel.h>
> +#include <linux/platform_device.h>
In general, I think it will make everyone's life easier in the long run
if the include directives are grouped and sorted.
BR,
Jani.
--
Jani Nikula, Intel
On 1/14/26 10:53, Tvrtko Ursulin wrote:
> \
> On 13/01/2026 15:16, Christian König wrote:
>> Some driver use fence->ops to test if a fence was initialized or not.
>> The problem is that this utilizes internal behavior of the dma_fence
>> implementation.
>>
>> So better abstract that into a function.
>>
>> Signed-off-by: Christian König <christian.koenig(a)amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 13 +++++++------
>> drivers/gpu/drm/qxl/qxl_release.c | 2 +-
>> include/linux/dma-fence.h | 12 ++++++++++++
>> 3 files changed, 20 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> index 0a0dcbf0798d..b97f90bbe8b9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
>> @@ -278,9 +278,10 @@ void amdgpu_job_free_resources(struct amdgpu_job *job)
>> unsigned i;
>> /* Check if any fences were initialized */
>> - if (job->base.s_fence && job->base.s_fence->finished.ops)
>> + if (job->base.s_fence &&
>> + dma_fence_is_initialized(&job->base.s_fence->finished))
>> f = &job->base.s_fence->finished;
>> - else if (job->hw_fence && job->hw_fence->base.ops)
>> + else if (dma_fence_is_initialized(&job->hw_fence->base))
>> f = &job->hw_fence->base;
>> else
>> f = NULL;
>> @@ -297,11 +298,11 @@ static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
>> amdgpu_sync_free(&job->explicit_sync);
>> - if (job->hw_fence->base.ops)
>> + if (dma_fence_is_initialized(&job->hw_fence->base))
>> dma_fence_put(&job->hw_fence->base);
>> else
>> kfree(job->hw_fence);
>> - if (job->hw_vm_fence->base.ops)
>> + if (dma_fence_is_initialized(&job->hw_vm_fence->base))
>> dma_fence_put(&job->hw_vm_fence->base);
>> else
>> kfree(job->hw_vm_fence);
>> @@ -335,11 +336,11 @@ void amdgpu_job_free(struct amdgpu_job *job)
>> if (job->gang_submit != &job->base.s_fence->scheduled)
>> dma_fence_put(job->gang_submit);
>> - if (job->hw_fence->base.ops)
>> + if (dma_fence_is_initialized(&job->hw_fence->base))
>> dma_fence_put(&job->hw_fence->base);
>> else
>> kfree(job->hw_fence);
>> - if (job->hw_vm_fence->base.ops)
>> + if (dma_fence_is_initialized(&job->hw_vm_fence->base))
>> dma_fence_put(&job->hw_vm_fence->base);
>> else
>> kfree(job->hw_vm_fence);
>> diff --git a/drivers/gpu/drm/qxl/qxl_release.c b/drivers/gpu/drm/qxl/qxl_release.c
>> index 7b3c9a6016db..b38ae0b25f3c 100644
>> --- a/drivers/gpu/drm/qxl/qxl_release.c
>> +++ b/drivers/gpu/drm/qxl/qxl_release.c
>> @@ -146,7 +146,7 @@ qxl_release_free(struct qxl_device *qdev,
>> idr_remove(&qdev->release_idr, release->id);
>> spin_unlock(&qdev->release_idr_lock);
>> - if (release->base.ops) {
>> + if (dma_fence_is_initialized(&release->base)) {
>> WARN_ON(list_empty(&release->bos));
>> qxl_release_free_list(release);
>> diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h
>> index eea674acdfa6..371aa8ecf18e 100644
>> --- a/include/linux/dma-fence.h
>> +++ b/include/linux/dma-fence.h
>> @@ -274,6 +274,18 @@ void dma_fence_release(struct kref *kref);
>> void dma_fence_free(struct dma_fence *fence);
>> void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq);
>> +/**
>> + * dma_fence_is_initialized - test if fence was initialized
>> + * @fence: fence to test
>> + *
>> + * Return: True if fence was initialized, false otherwise. Works correctly only
>> + * when memory backing the fence structure is zero initialized on allocation.
>> + */
>> +static inline bool dma_fence_is_initialized(struct dma_fence *fence)
>> +{
>> + return fence && !!fence->ops;
>
> This patch should precede the one adding RCU protection to fence->ops. And that one then needs to add a rcu_dereference() here.
Good point.
> At which point however it would start exploding?
When we start setting the ops pointer to NULL in the next patch.
> Which also means the new API is racy by definition and can give false positives if fence would be to be signaled as someone is checking.
Oh, that is a really really good point. I haven't thought about that because all current users would check the fence only after it is signaled.
> Hmm.. is the new API too weak, being able to only be called under very limited circumstances?
Yes, exactly that. All callers use this only to decide on the correct cleanup path.
So the fence is either fully signaled or was never initialized in the first place.
> Would it be better to solve it in the drivers by tracking state?
The alternative I had in mind was to use another DMA_FENCE_FLAG_... for that.
I will probably use that approach instead, just to make it extra defensive.
Thanks,
Christian.
>
> Regards,
>
> Tvrtko
>
>> +}
>> +
>> /**
>> * dma_fence_put - decreases refcount of the fence
>> * @fence: fence to reduce refcount of
>