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[PATCH 0/2] USB: OHCI: more bus glues as separate modules

by Manjunath Goudar

These patches are for separating the SOC On-Chip ohci host controller from ohci-hcd host code into its own driver module. This work is part of enabling multi-platform kernels on ARM. Manjunath Goudar (2): USB: OHCI: make ohci-ep93xx a separate driver USB: OHCI: make ohci-pxa27x a separate driver drivers/usb/host/Kconfig | 16 +++++ drivers/usb/host/Makefile | 2 + drivers/usb/host/ohci-ep93xx.c | 84 ++++++++++------------ drivers/usb/host/ohci-hcd.c | 24 ------- drivers/usb/host/ohci-pxa27x.c | 154 ++++++++++++++++------------------------ 5 files changed, 120 insertions(+), 160 deletions(-) -- 1.7.9.5

11 years, 10 months

[PATCH 01/11] usb: misc: usb3503: Fix swapped properties in DT parsing

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> The intn and connect GPIO properties are swapped in the code which will cause failures at runtime if these are connected, fix the code. There are currently no in-tree users of this device to check or update. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- drivers/usb/misc/usb3503.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c index cbb6b78..4e3a2d2 100644 --- a/drivers/usb/misc/usb3503.c +++ b/drivers/usb/misc/usb3503.c @@ -215,10 +215,10 @@ static int usb3503_probe(struct i2c_client *i2c, const struct i2c_device_id *id) } } - hub->gpio_intn = of_get_named_gpio(np, "connect-gpios", 0); + hub->gpio_intn = of_get_named_gpio(np, "intn-gpios", 0); if (hub->gpio_intn == -EPROBE_DEFER) return -EPROBE_DEFER; - hub->gpio_connect = of_get_named_gpio(np, "intn-gpios", 0); + hub->gpio_connect = of_get_named_gpio(np, "connect-gpios", 0); if (hub->gpio_connect == -EPROBE_DEFER) return -EPROBE_DEFER; hub->gpio_reset = of_get_named_gpio(np, "reset-gpios", 0); -- 1.8.4.rc1

11 years, 10 months

[PATCH v2] ARM: KVM: Simplify tracepoint text

by Christoffer Dall

The tracepoint for kvm_guest_fault was extremely long, make it a slightly bit shorter. Cc: Sergei Shtylyov <sergei.shtylyov(a)cogentembedded.com> Signed-off-by: Christoffer Dall <christoffer.dall(a)linaro.org> --- Changelog[v1 -> v2]: - Remove redundant 0x prefixes arch/arm/kvm/trace.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/kvm/trace.h b/arch/arm/kvm/trace.h index a8e73ed..b1d640f 100644 --- a/arch/arm/kvm/trace.h +++ b/arch/arm/kvm/trace.h @@ -59,10 +59,9 @@ TRACE_EVENT(kvm_guest_fault, __entry->ipa = ipa; ), - TP_printk("guest fault at PC %#08lx (hxfar %#08lx, " - "ipa %#16llx, hsr %#08lx", - __entry->vcpu_pc, __entry->hxfar, - __entry->ipa, __entry->hsr) + TP_printk("ipa %#llx, hsr %#08lx, hxfar %#08lx, pc %#08lx", + __entry->ipa, __entry->hsr, + __entry->hxfar, __entry->vcpu_pc) ); TRACE_EVENT(kvm_irq_line, -- 1.7.10.4

11 years, 10 months

About buffer sychronization mechanism and cache operation

by Inki Dae

Hello all, The purpose of this email is to get other opinions and advices to buffer synchronization mechanism, and coupling cache operation feature with the buffer synchronization mechanism. First of all, I am not a native English speaker so I'm not sure that I can convey my intention to you. And I'm not a specialist in Linux than other people so also there might be my missing points. I had posted the buffer synchronization mechanism called dmabuf sync framework like below, http://lists.infradead.org/pipermail/linux-arm-kernel/2013-June/177045.html And I'm sending this email before posting next version with more stable patch set and features. The purpose of this framework is to provide not only buffer access control to CPU and DMA but also easy-to-use interfaces for device drivers and user application. This framework can be used for all DMA devices using system memory as DMA buffer, especially for most ARM based SoCs. There are two cases we are using this buffer synchronization framework. One is to primarily enhance GPU rendering performance on Tizen platform in case of 3d app with compositing mode that the 3d app draws something in off-screen buffer. And other is to couple buffer access control and cache operation between CPU and DMA; the cache operation is done by the dmabuf sync framework in kernel side. Why do we need buffer access control between CPU and DMA? --------------------------------------------------------- The below shows simple 3D software layers, 3D Application ----------------------------------------- Standard OpenGL ES and EGL Interfaces ------- [A] ----------------------------------------- MALI OpenGL ES and EGL Native modules --------- [B] ----------------------------------------- Exynos DRM Driver | GPU Driver ---------- [C] 3d application requests 3d rendering through A. And then B fills a 3d command buffer with the requests from A. And then 3D application calls glFlush so that the 3d command buffer can be submitted to C, and rendered by GPU hardware. Internally, glFlush(also glFinish) will call a function of native module[B] glFinish blocks caller's task until all GL execution is complete. On the other hand, glFlush forces execution of GL commands but doesn't block the caller's task until the completion. In composting mode, in case of using glFinish, the 3d rendering performance is quite lower than using glFlush because glFinish makes CPU blocked until the execution of the 3d commands is completed. However, the use of glFlush has one issue that the shared buffer with GPU could be broken when CPU accesses the shared buffer at once after glFlush because CPU cannot be aware of the completion of GPU access to the shared buffer: actually, Tizen platform internally calls only eglSwapBuffer instead of glFlush and glFinish, and whether flushing or finishing is decided according to compositing mode or not. So in such case, we would need buffer access control between CPU and DMA for more performance. About cache operation --------------------- The dmabuf sync framework can include cache operation feature, and the below shows how the cache operation based on dmabuf sync framework is performed, device driver in kernel or fctrl in user land dmabuf_sync_lock or dmabuf_sync_single_lock check before and after buffer access dma_buf_begin_cpu_access or dma_buf_end_cpu_access begin_cpu_access or end_cpu_access of exporter dma_sync_sg_for_device or dma_sync_sg_for_cpu In case that using dmabuf sync framework, kernel can be aware of when CPU and DMA access to a shared buffer is completed so we can do cache operation in kernel so that way, we can couple buffer access control and cache operation. So with this, we can avoid that user land overuses cache operation. I guess most Linux based platforms are using cachable mapped buffer for more performance: in case that CPU frequently accesses the shared buffer which is shared with DMA, the use of cachable mapped buffer is more fast than the use of non-cachable. However, this way could make cache operation overused by user land because only user land can be aware of the completion of CPU or DMA access to the shared buffer so user land could request cache operations every time it wants even the cache operation is unnecessary. That is how user land could overuse cache operations. To Android, Chrome OS, and other forks, Are there other cases that buffer access control between CPU and DMA is needed? I know Android sync driver and KDS are already being used for Android, Chrome OS, and so on. How does your platform do cache operation? And How do you think about coupling buffer access control and cache operation between CPU and DMA?. Lastly, I think we may need Linux generic buffer synchronization mechanism that uses only Linux standard interfaces (dmabuf) including user land interfaces (fcntl and select system calls), and the dmabuf sync framework could meet it. Thanks, Inki Dae

11 years, 10 months

Re: [PATCH v6 2/8] cpufreq: Add boost frequency support in core

by Viresh Kumar

On 25 July 2013 22:03, Lukasz Majewski <l.majewski(a)samsung.com> wrote: > diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c > /********************************************************************* > + * BOOST * > + *********************************************************************/ > +static int cpufreq_boost_set_sw(int state) > +{ > + struct cpufreq_frequency_table *freq_table; > + struct cpufreq_policy *policy; > + int ret = -EINVAL; > + > + list_for_each_entry(policy, &cpufreq_policy_list, policy_list) { > + freq_table = cpufreq_frequency_get_table(policy->cpu); > + if (freq_table) { > + ret = cpufreq_frequency_table_cpuinfo(policy, > + freq_table); > + if (!ret) { > + policy->user_policy.max = policy->max; > + __cpufreq_governor(policy, CPUFREQ_GOV_LIMITS); > + } > + } > + } > + > + return ret; > +} > + > +int cpufreq_boost_trigger_state(int state) > +{ > + unsigned long flags; > + int ret = 0; > + > + if (cpufreq_driver->boost_enabled == state) > + return 0; > + > + write_lock_irqsave(&cpufreq_driver_lock, flags); > + cpufreq_driver->boost_enabled = state; > + write_unlock_irqrestore(&cpufreq_driver_lock, flags); Not sure if we should leave the lock at this point of time, as we haven't enabled boost until now. If somebody tries to use this variable at this point of time, then it would get the wrong information about it. > + ret = cpufreq_driver->set_boost(state); > + if (ret) { > + write_lock_irqsave(&cpufreq_driver_lock, flags); > + cpufreq_driver->boost_enabled = 0; should be: cpufreq_driver->boost_enabled = !state; > + write_unlock_irqrestore(&cpufreq_driver_lock, flags); > + > + pr_err("%s: BOOST cannot %s\n", __func__, s/BOOST cannot %s/Cannot %s BOOST > + state ? "enabled" : "disabled"); > + } > + > + return ret; > +} > + > +int cpufreq_boost_supported(void) > +{ > + if (cpufreq_driver) This routine is always called from places where cpufreq_driver can't be NULL.. --contd-- > + return cpufreq_driver->boost_supported; > + > + return 0; > +} > +EXPORT_SYMBOL_GPL(cpufreq_boost_supported); > + > +int cpufreq_boost_enabled(void) > +{ > + return cpufreq_driver->boost_enabled; And if above check is necessary, then don't you need to check it here as well? > +} > +EXPORT_SYMBOL_GPL(cpufreq_boost_enabled); > + > +/********************************************************************* > * REGISTER / UNREGISTER CPUFREQ DRIVER * > *********************************************************************/ > > @@ -2008,9 +2099,25 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data) > cpufreq_driver = driver_data; > write_unlock_irqrestore(&cpufreq_driver_lock, flags); > > + if (cpufreq_boost_supported()) { > + /* > + * Check if boost driver provides function to enable boost - s/boost driver/driver > + * if not, use cpufreq_boost_set_sw as default > + */ > + if (!cpufreq_driver->set_boost) > + cpufreq_driver->set_boost = cpufreq_boost_set_sw; > + > + ret = cpufreq_sysfs_create_file(&(boost.attr)); You don't need braces around boost.attr. > + if (ret) { > + pr_err("%s: cannot register global BOOST sysfs file\n", > + __func__); > + goto err_null_driver; > + } > + } > + > ret = subsys_interface_register(&cpufreq_interface); > if (ret) > - goto err_null_driver; > + goto err_boost_unreg; > > if (!(cpufreq_driver->flags & CPUFREQ_STICKY)) { > int i; > @@ -2037,6 +2144,9 @@ int cpufreq_register_driver(struct cpufreq_driver *driver_data) > return 0; > err_if_unreg: > subsys_interface_unregister(&cpufreq_interface); > +err_boost_unreg: > + if (cpufreq_boost_supported()) > + cpufreq_sysfs_remove_file(&(boost.attr)); same here. > err_null_driver: > write_lock_irqsave(&cpufreq_driver_lock, flags); > cpufreq_driver = NULL; > @@ -2063,6 +2173,9 @@ int cpufreq_unregister_driver(struct cpufreq_driver *driver) > pr_debug("unregistering driver %s\n", driver->name); > > subsys_interface_unregister(&cpufreq_interface); > + if (cpufreq_boost_supported()) > + cpufreq_sysfs_remove_file(&(boost.attr)); here too. > + > unregister_hotcpu_notifier(&cpufreq_cpu_notifier); > > write_lock_irqsave(&cpufreq_driver_lock, flags); > +static ssize_t scaling_available_frequencies_show(struct cpufreq_policy *policy, > + char *buf) > +{ > + return show_available_freqs(policy, buf, 0); s/0/false > +} > +static ssize_t scaling_boost_frequencies_show(struct cpufreq_policy *policy, > + char *buf) > +{ > + return show_available_freqs(policy, buf, 1); s/1/true > +} Looks good mostly.. We Should be to get it in 3.12 :)

11 years, 10 months

[PATCH] ASoC: adau1701: Use gpio_set_value_cansleep()

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> The GPIO manipulation done by this driver is never in atomic context so we can use gpio_set_value_cansleep() and support GPIOs that can't be set from atomic context. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- sound/soc/codecs/adau1701.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/sound/soc/codecs/adau1701.c b/sound/soc/codecs/adau1701.c index 2c10252..ebff112 100644 --- a/sound/soc/codecs/adau1701.c +++ b/sound/soc/codecs/adau1701.c @@ -247,21 +247,21 @@ static int adau1701_reset(struct snd_soc_codec *codec, unsigned int clkdiv) gpio_is_valid(adau1701->gpio_pll_mode[1])) { switch (clkdiv) { case 64: - gpio_set_value(adau1701->gpio_pll_mode[0], 0); - gpio_set_value(adau1701->gpio_pll_mode[1], 0); + gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0); + gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0); break; case 256: - gpio_set_value(adau1701->gpio_pll_mode[0], 0); - gpio_set_value(adau1701->gpio_pll_mode[1], 1); + gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 0); + gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1); break; case 384: - gpio_set_value(adau1701->gpio_pll_mode[0], 1); - gpio_set_value(adau1701->gpio_pll_mode[1], 0); + gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1); + gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 0); break; case 0: /* fallback */ case 512: - gpio_set_value(adau1701->gpio_pll_mode[0], 1); - gpio_set_value(adau1701->gpio_pll_mode[1], 1); + gpio_set_value_cansleep(adau1701->gpio_pll_mode[0], 1); + gpio_set_value_cansleep(adau1701->gpio_pll_mode[1], 1); break; } } @@ -269,10 +269,10 @@ static int adau1701_reset(struct snd_soc_codec *codec, unsigned int clkdiv) adau1701->pll_clkdiv = clkdiv; if (gpio_is_valid(adau1701->gpio_nreset)) { - gpio_set_value(adau1701->gpio_nreset, 0); + gpio_set_value_cansleep(adau1701->gpio_nreset, 0); /* minimum reset time is 20ns */ udelay(1); - gpio_set_value(adau1701->gpio_nreset, 1); + gpio_set_value_cansleep(adau1701->gpio_nreset, 1); /* power-up time may be as long as 85ms */ mdelay(85); } -- 1.8.4.rc1

11 years, 10 months

[PATCH] ARM: dts: Add RTC DT node to Exynos5420 SoC

by Vikas Sajjan

Adds RTC DT node to Exynos5420 SoC. Signed-off-by: Vikas Sajjan <vikas.sajjan(a)linaro.org> --- arch/arm/boot/dts/exynos5.dtsi | 2 +- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos5420.dtsi | 6 ++++++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index f65e124..4a8e223 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -95,7 +95,7 @@ interrupts = <0 54 0>; }; - rtc { + rtc@101E0000 { compatible = "samsung,s3c6410-rtc"; reg = <0x101E0000 0x100>; interrupts = <0 43 0>, <0 44 0>; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 88589b7..f426ce6 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -178,7 +178,7 @@ samsung,power-domain = <&pd_mfc>; }; - rtc { + rtc@101E0000 { clocks = <&clock 337>; clock-names = "rtc"; }; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 9e90d1e..b48d62c 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -145,4 +145,10 @@ clocks = <&clock 260>, <&clock 131>; clock-names = "uart", "clk_uart_baud0"; }; + + rtc@101E0000 { + clocks = <&clock 317>; + clock-names = "rtc"; + }; + }; -- 1.7.9.5

11 years, 10 months

[PATCH] ASoC: compress: Use power efficient workqueue

by Mark Brown

From: Mark Brown <broonie(a)linaro.org> There is no need for the power down work to be done on a per CPU workqueue especially considering the fairly long delay before powerdown. Signed-off-by: Mark Brown <broonie(a)linaro.org> --- sound/soc/soc-compress.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/sound/soc/soc-compress.c b/sound/soc/soc-compress.c index d220150..53c9ecd 100644 --- a/sound/soc/soc-compress.c +++ b/sound/soc/soc-compress.c @@ -149,8 +149,9 @@ static int soc_compr_free(struct snd_compr_stream *cstream) SND_SOC_DAPM_STREAM_STOP); } else { rtd->pop_wait = 1; - schedule_delayed_work(&rtd->delayed_work, - msecs_to_jiffies(rtd->pmdown_time)); + queue_delayed_work(system_power_efficient_wq, + &rtd->delayed_work, + msecs_to_jiffies(rtd->pmdown_time)); } } else { /* capture streams can be powered down now */ -- 1.8.4.rc1

11 years, 10 months

[PATCH] ARM: KVM: Simplify tracepoint text

by Christoffer Dall

The tracepoint for kvm_guest_fault was extremely long, make it a slightly bit shorter. Signed-off-by: Christoffer Dall <christoffer.dall(a)linaro.org> --- arch/arm/kvm/trace.h | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/kvm/trace.h b/arch/arm/kvm/trace.h index a8e73ed..8cbaea2 100644 --- a/arch/arm/kvm/trace.h +++ b/arch/arm/kvm/trace.h @@ -59,10 +59,9 @@ TRACE_EVENT(kvm_guest_fault, __entry->ipa = ipa; ), - TP_printk("guest fault at PC %#08lx (hxfar %#08lx, " - "ipa %#16llx, hsr %#08lx", - __entry->vcpu_pc, __entry->hxfar, - __entry->ipa, __entry->hsr) + TP_printk("ipa 0x%llx, hsr 0x%#08lx, hxfar 0x%#08lx, pc 0x%#08lx", + __entry->ipa, __entry->hsr, + __entry->hxfar, __entry->vcpu_pc) ); TRACE_EVENT(kvm_irq_line, -- 1.7.10.4

11 years, 10 months

[PATCH] usb: misc: Fix swapped properties in usb3503 DT parsing

by Mark Brown

11 years, 10 months

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