This patch adds support for Samsung GH7 PCIe host controller.
Samsung GH7 PCIe controller driver has dependency on the PCI arm64
arch support. So, the Liviu Dudau's patcheset for creating generic
host_bridge from device tree [1] and supporting PCI in AArch64 [2]
are required.
This patch is marked as RFC, so any comment will be welcomed.
Thank you.
[1] http://www.spinics.net/lists/linux-pci/msg29786.html
[2] http://www.spinics.net/lists/linux-pci/msg29793.html
Jingoo Han (2)
PCI: designware: Add ARM64 PCI support
PCI: exynos: Add PCIe support for Samsung GH7 SoC
---
drivers/pci/host/Kconfig | 2 +-
drivers/pci/host/pci-exynos.c | 135 +++++++++++++++++++++++++++++++++---
drivers/pci/host/pcie-designware.c | 32 +++++++++
3 files changed, 158 insertions(+), 11 deletions(-)
Best regards,
Jingoo Han
From: Arnd Bergmann <arnd(a)arndb.de>
The sh_mobile_lcdcfb driver calls interfaces provided
by the corresponding "meram" helper. This fails if meram
is a module but lcdcfb is built-in.
To work around it, this uses special Kconfig magic to
only allow lcdcfb to be built if
a) both are modules,
b) meram is built-in, or
c) meram is disabled and the helpers stubbed out
Changing meram from 'y' to 'm' now forces clcd to
be a module as well, which seems to be the desired
behavior.
Signed-off-by: Arnd Bergmann <arnd(a)arndb.de>
Signed-off-by: Peter Griffin <peter.griffin(a)linaro.org>
Cc: Simon Horman <horms+renesas(a)verge.net.au>
Cc: Magnus Damm <magnus.damm(a)gmail.com>
Cc: linux-sh(a)vger.kernel.org
Cc: Jean-Christophe Plagniol-Villard <plagnioj(a)jcrosoft.com>
Cc: Tomi Valkeinen <tomi.valkeinen(a)ti.com>
Cc: linux-fbdev(a)vger.kernel.org
---
drivers/video/fbdev/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index e1f4727..a4116bf 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -1971,6 +1971,7 @@ config FB_W100
config FB_SH_MOBILE_LCDC
tristate "SuperH Mobile LCDC framebuffer support"
depends on FB && (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
+ depends on FB_SH_MOBILE_MERAM || !FB_SH_MOBILE_MERAM
select FB_SYS_FILLRECT
select FB_SYS_COPYAREA
select FB_SYS_IMAGEBLIT
--
1.7.9.5
Hi,
File: hrtimer.c
Function: hrtimer_get_next_event()
I was looking closely at what's waking up my system and
found this piece of code:
ktime_t hrtimer_get_next_event(void)
{
if (!hrtimer_hres_active()) {
find next hrtimer event ....
}
}
Which probably means that: "don't consider hrtimers for getting
next timer event if we are running ticks in high resolution mode".
And I couldn't understand why is it so?
When hres_active isn't set, we run hrtimer handlers from timer
handlers, which means that timers would be sufficient in finding
the next event and we don't need to check for hrtimers.
But when hres_active is set, hrtimers could be set to fire before
the next timer event and so we must take them into account.
I am new to this whole world of core frameworks and might be
missing something very very obvious. But its always better to
ask than to ignore and think that things are probably fine and
just shut up.
Thanks for your patience during my learning curve :)
--
viresh
If DCACHE_WORD_ACCESS is enabled big endian image failed to
boot. commit 7bc13fd33adb9536bd73965cd46bbf7377df097c
"arm64: dcache: select DCACHE_WORD_ACCESS for little-endian CPUs"
enabled this setting for both big endian and little endian
cpus. And code in commit itself seems to be endian agnostic,
however other, i.e C, code that sits under DCACHE_WORD_ACCESS
seems to be not endian agnostic, I could not figure out where
though.
Solution is to enable DCACHE_WORD_ACCESS only if little
endian mode is enabled (default).
Signed-off-by: Victor Kamensky <victor.kamensky(a)linaro.org>
---
arch/arm64/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index e6e4d37..106ac4f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -13,7 +13,7 @@ config ARM64
select CLONE_BACKWARDS
select COMMON_CLK
select CPU_PM if (SUSPEND || CPU_IDLE)
- select DCACHE_WORD_ACCESS
+ select DCACHE_WORD_ACCESS if !CPU_BIG_ENDIAN
select GENERIC_CLOCKEVENTS
select GENERIC_CLOCKEVENTS_BROADCAST if SMP
select GENERIC_CPU_AUTOPROBE
--
1.8.1.4
Hi Guys,
This second version of patch to flush icache and dcache after
uprobes xol write to make written instruction available in icache.
Please see [1] for initial discussion.
This patch follows Russell's suggestion, and function that does
cache flush after xol slot instruction write is shared/reused
with similar one implemented already for ptrace code.
In order to reuse common implementation but to avoid vma use
by xol_get_insn_slot I split flush_ptrace_access into two
functions. Where first part retrieves all required conditions
from vma and places them into flags variable and then calls
second function which is common code.
Also I had to change xol_get_insn_slot function to map page
into kernel explicitly within function without use of
copy_to_page helper because ARM cache flush code need both
kernel address through which instruction write happens and
virtual address of user-land process where instruction will
end up. I hope this call back is universal enough so other
CPU could implement their cache invalidation/sync after
uprobes xol instruction write logic based on provided
parameters.
I've tested it on Arndale board with my SystemTap test case
that had cache problem before. Disassemble of
flush_uprobe_xol_access in case of Arndale shows that compiler
does good job and optimizes out all flags check effectively
leaving on this cpu call to flush_icache_alias or call to
v7_coherent_user_range (__cpuc_coherent_kern_range).
Also tested basic user-level debugging.
Wondering on what ARM boards/cpus could we test cache_is_vivt()
and cache_is_vipt_aliasing cases ...
Just to summarize, please note on [1] there were couple other
suggestions:
Oleg suggested to use flush_icache_user_range but Russell
argument was that meaning of the function is lost and on ARM
it is not implemented in such way that it could address the
issue anyway. Please see [2] for details. Note it would has
vma problem use or not, that should be hacked.
Dave Martin suggested to use flush_icache_range, which is
effectively better way to call
__cpuc_coherent_[kern|user]_range(s,e), that was originally
suggested. But Russell explained that it won't be enough in
case of user-land process pages and variety of cache types have
to be covered. Note for kernel pages it would be OK and it is
used in multiple places like kprobes, modules, etc.
Thanks,
Victor
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/245595.htmlhttp://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/245427.html
[2] http://lists.infradead.org/pipermail/linux-arm-kernel/2014-April/245605.html
Victor Kamensky (1):
ARM: uprobes need icache flush after xol write
arch/arm/include/asm/cacheflush.h | 2 ++
arch/arm/kernel/uprobes.c | 6 ++++++
arch/arm/mm/flush.c | 41 +++++++++++++++++++++++++++++++++------
include/linux/uprobes.h | 3 +++
kernel/events/uprobes.c | 33 +++++++++++++++++++++++++------
5 files changed, 73 insertions(+), 12 deletions(-)
--
1.8.1.4
On Tue, Apr 22, 2014 at 05:39:28PM -0700, Dmitry Torokhov wrote:
> On Tue, Apr 22, 2014 at 10:18:21PM +0100, Mark Brown wrote:
> > Remove the bitrotted comment, though in actual fact the use case mentioned
> > is a great use for spi_async() since it would cut down on latency handling
> > the interrupt by saving us a context switch before we start SPI.
> > This was previously implemented, it was removed in commit b534422b2d11
> > (Input: ad7877 - switch to using threaded IRQ) for code complexity reasons.
> > It may be better to revert that commit instead.
> Hmm, maybe.. although I think original would cause device 'stuck' if
> call to spi_async() fails, so probably not a straight revert...
Probably best just to apply this, then - someone can always reimplement
if they need to.
Hello, hopefully this is the correct mailing list for this question:
I'm working on a derivative of the mainline Linux 3.8 kernel and I'm trying
to enable ARM kdump functionality to collect crashdumps when we have kernel
problems. But, there's some kind of unresolved issue in
arch/arm/mm/ioremap.c which prevents /proc/vmcore from being able to
function properly. I checked and this appears to still be in kernel.org
Linux 3.13. The target is a normal, recent ARMv7 chip.
Has this issue been addressed in any version of Linaro's kernel? Or, is
there a work-around? If not, how does a crashdump file get generated when/if
the Linaro kernel crashes or a driver faults?
>> WARNING: at arch/arm/mm/ioremap.c:244
__arm_ioremap_pfn_caller+0x1d8/0x1f0()
>> Modules linked in:
>> [<c0016660>] (unwind_backtrace+0x0/0x138) from [<c0020480>]
(warn_slowpath_common+0x4c/0x64)
>> [<c0020480>] (warn_slowpath_common+0x4c/0x64) from [<c00204b4>]
(warn_slowpath_null+0x1c/0x24)
>> [<c00204b4>] (warn_slowpath_null+0x1c/0x24) from [<c0018e9c>]
(__arm_ioremap_pfn_caller+0x1d8/0x1f0)
>> [<c0018e9c>] (__arm_ioremap_pfn_caller+0x1d8/0x1f0) from [<c0018f20>]
(__arm_ioremap_caller+0x54/0x5c)
>> [<c0018f20>] (__arm_ioremap_caller+0x54/0x5c) from [<c0018c58>]
(__arm_ioremap+0x18/0x1c)
>> [<c0018c58>] (__arm_ioremap+0x18/0x1c) from [<c00168fc>]
(copy_oldmem_page+0x34/0xc0)
>> [<c00168fc>] (copy_oldmem_page+0x34/0xc0) from [<c010350c>]
(read_from_oldmem+0xb8/0xe4)
>> [<c010350c>] (read_from_oldmem+0xb8/0xe4) from [<c05c37e0>]
(parse_crash_elf32_headers+0x184/0x43c)
>> [<c05c37e0>] (parse_crash_elf32_headers+0x184/0x43c) from [<c05c3b64>]
(vmcore_init+0xcc/0x198)
>> [<c05c3b64>] (vmcore_init+0xcc/0x198) from [<c000863c>]
(do_one_initcall+0x34/0x184)
>> [<c000863c>] (do_one_initcall+0x34/0x184) from [<c05b28dc>]
(kernel_init_freeable+0xfc/0x1c8)
>> [<c05b28dc>] (kernel_init_freeable+0xfc/0x1c8) from [<c04326d4>]
(kernel_init+0x8/0xe4)
>> [<c04326d4>] (kernel_init+0x8/0xe4) from [<c000ec58>]
(ret_from_fork+0x14/0x3c)
>>
>> arch/arm/mm/ioremap.c:244
>> /*
>> * Don't allow RAM to be mapped - this causes problems with
ARMv6+
>> */
>> if (WARN_ON(pfn_valid(pfn)))
>> return NULL;
Thanks in advance for any help.
-andy