Re: [RFC PATCH v4 05/15] dt-bindings: arm: Adds CoreSight CTI hardware definitions.

On Mon, Aug 19, 2019 at 10:13:51PM +0100, Mike Leach wrote:

Adds new .txt file describing the bindings required to define CTI in the device trees.

Adds an include file to dt-bindings/arm to define constants describing common signal functionality used in CoreSight and generic usage.

As we talked about, this will need to comply with the new DT schema format but I decided to give it a read anyway.

Signed-off-by: Mike Leach mike.leach@linaro.org

.../bindings/arm/coresight-ect-cti.txt | 396 ++++++++++++++++++ .../devicetree/bindings/arm/coresight.txt | 7 + MAINTAINERS | 2 + include/dt-bindings/arm/coresight-cti-dt.h | 36 ++ 4 files changed, 441 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/coresight-ect-cti.txt create mode 100644 include/dt-bindings/arm/coresight-cti-dt.h

diff --git a/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt b/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt new file mode 100644 index 000000000000..5f78b610be4d --- /dev/null +++ b/Documentation/devicetree/bindings/arm/coresight-ect-cti.txt @@ -0,0 +1,396 @@ +*CoreSight Embedded Cross Trigger Components

+The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected +to one or more CoreSight components and/or a CPU, with CTIs interconnected in +a star topology via the CTM (which is not programmable). The ECT components +are not part of the trace generation data path and are thus not part of the +CoreSight graph described in the general CoreSight bindings file coresight.txt.

+The CTI component properties define the connections between the individual CTI +and the components it is directly connected to, consisting of input and output +hardware trigger signals. CTIs can have a maximum number of input and output +hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The number is +defined at design time, the maximum of each defined in the DEVID register. +Note that some hardware trigger signals can be connected to non-CoreSight +components (e.g. UART etc) depending on hardware implementation.

+CTIs are interconnected in a star topology via the CTM, using a number of +programmable channels usually 4, but again implementation defined and described +in the DEVID register. The star topology is not required to be described in the +bindings as the actual connections are software programmable.

+In general the connections between CTI and components via the trigger signals +are implementation defined, other than when v8 core and ETM is present. The v8 +architecture defines the required signal connections between CPU core and CTI, +and ETM and CTI, if the ETM if present.

+Certain triggers between CoreSight devices and the CTI have specific types / +usages. These can be defined along with the signal indexes with the constants +defined in <dt-bindings/arm/coresight-cti-dt.h>

+For example a CTI connected to a core will usually have a DBGREQ signal. This +is defined in the binding as type PE_EDBGREQ. These types will appear in an +optional array alongside the signal indexes. Omitting types will default all +signals to GEN_IO.

+The minimum required binding for a CTI consists of only the following required +properties defined in coresight.txt:-

+* Required properties:

• • compatible: These have to be supplemented with "arm,primecell" as

•  drivers are using the AMBA bus interface.
  

• - Coresight Cross Trigger Interface (CTI):
  

• 	"arm,coresight-cti", "arm,primecell";
  

I think the above requires better formatting.

• • reg
• • clocks
• • clock-names

+e.g.(1) +/* sys cti 0 */ +cti0: cti@20020000 {

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0x20020000 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";
• power-domains = <&scpi_devpd 0>;

+};

+This will result in the driver using the DEVID register to set the +input and output triggers and channels in use. Any user / client +application will require additional information on the connections +between the CTI and other components for correct operation.

+Where information is immediately available for the component connections then +a series of trigger connection nodes can be defined (trig-conns).

+These connections explicitly define the input and output triggers between the +CTI and a connected component. Connections to an cpu use the standard "cpu"

s/an cpu/a cpu

+property, connections to other CoreSight components use the arm,cs-dev-assoc +property.

+e.g.(2) +/* CPU CTI connected to Core and ETM */ +cti@858000 {

•   compatible = "arm,coresight-cti", "arm,primecell";
  

•   reg = <0x858000 0x1000>;
  

•   clocks = <&rpmcc RPM_QDSS_CLK>;
  

•   clock-names = "apb_pclk";
  

•   trig-conns@0 {
  

• 	arm,trig-in-sigs = <4 5 6 7>;
  

• 	arm,trig-in-types = <ETM_EXTOUT
  

• 			  ETM_EXTOUT
  

• 			  ETM_EXTOUT
  

• 			  ETM_EXTOUT>;
  

• 	arm,trig-out-sigs = <4 5 6 7>;
  

• 	arm,trig-out-types = <ETM_EXTIN
  

• 			   ETM_EXTIN
  

• 			   ETM_EXTIN
  

• 			   ETM_EXTIN>;
  

• 	arm,cs-dev-assoc = <&etm0>;
  

•   };
  

•   trig-conns@1 {
  

•        cpu = <&CPU0>;
  

•        arm,trig-in-sigs = <0 1>;
  

•        arm,trig-in-types = <PE_DBGTRIGGER
  

• 			   PE_PMUIRQ>;
  

•        arm,trig-out-sigs=<0 1 2 >;
  

•        arm,trig-out-types = <PE_EDBGREQ
  

• 			  PE_DBGRESTART
  

• 			  PE_CTIIRQ>;
  

•        arm,trig-filters = <0>;
  

•   };
  

+};

+Note that where input and output triggers are defined as above, then the driver +will limit the channel connection sysfs API to using only the defined signals.

+The arm,trig-filters property blocks output signals that could cause system +issues if set - such as the PE_EDBGREQ signal into a CPU. The filtering is +enabled by default, but can be disabled at runtime.

+Where the signals are connected to a device that is not CoreSight device then +no association is registered. In this case a name can be used to identify the +component (arm,trig-conn-name)

+e.g.(3) +/* CTI connected to none coresight devices */ +cti@20110000 { /* Juno sys_cti_1 */

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0 0x20110000 0 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";
• power-domains = <&scpi_devpd 0>;
• trig-conns@0 {

• arm,trig-in-sigs=<0>;
  

• arm,trig-in-types=<GEN_INTREQ>;
  

• arm,trig-out-sigs=<0>;
  

• arm,trig-out-types=<GEN_HALTREQ>;
  

• arm,trig-conn-name = "sys_profiler";
  

• };
• trig-conns@1 {

• arm,trig-out-sigs=<2 3>;
  

• arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
  

• arm,trig-conn-name = "watchdog";
  

• };
• trig-conns@2 {

• arm,trig-out-sigs=<1 6>;
  

• arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
  

• arm,trig-conn-name = "g_counter";
  

• };

+};

+Finally, a CTI that is an architecturally defined v8 CTI connected to a cpu

To be consistent with what you have in the previous paragraphs:

s/cpu/CPU

+and optional ETM may be declared as:

+e.g.(4) +/* v8 architectural CTI, connected to core and ETM */ +cti@859000 {

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0x859000 0x1000>;
• clocks = <&rpmcc RPM_QDSS_CLK>;
• clock-names = "apb_pclk";
• arm,cti-v8-arch;
• cpu = <&CPU1>;
• arm,cs-dev-assoc = <&etm1>;

+};

+This example will result in the same internal structure as e.g.(2)

+The arm,cti-v8-arch property declares this as a v8 CTI, the cpu property must +be present, and a single arm,cs-dev-assoc may be present to define an attached +ETM. No additional trig-conns nodes are permitted. The driver will build a +connection model according to architectural requirements. This will include +a filter on the CPU dbgreq signal as described above.

s/dbgreq/DBGREQ

+All the CTI devices are associated with a CTM. On many systems there will be a +single effective CTM (one CTM, or multiple CTMs all interconnected), but it is +possible that systems can have nets of CTIs+CTM that are not interconnected by +a CTM. On these systems a CTM index is declared to associate CTI devices that +are interconnected via the CTM.

• e.g.
• arm,cti-ctm-id=<2>

+CTI devices with the same CTM ID are considered connected by the CTM. If this +parameter is absent then all CTIs are considered interconnected by the same +CTM.

+*Summary of CTI required properties:

• • compatible : should be "arm,coresight-cti"; supplemented with

•  "arm,primecell" since this driver is using the AMBA bus
  

•  interface.
  

• • reg: physical base address and length of the register

•  set(s) of the component.
  

• • clocks: the clocks associated to this component.
• • clock-names: the name of the clocks referenced by the code.

•  Since we are using the AMBA framework, the name of the clock
  

•  providing the interconnect should be "apb_pclk", and some
  

•  coresight blocks also have an additional clock "atclk", which
  

•  clocks the core of that coresight component. The latter clock
  

•  is optional.
  

+*Summary of CTI optional properties:

• • trig-conns: defines a connection node between CTI and a component.

•  Component may be a CPU, CoreSight device, any other hardware device
  

•  or simple external IO lines.
  

• • arm,cti-v8-arch: Declares this CTI device as a v8 architecturally

•  defined device. Use in CTI base node only, no additional trig-conns
  

•  nodes permitted if this is declared.
  

• • cpu: defines a phandle reference to an associated CPU. Used in

•  trig-conns node, or in CTI base node when arm,cti-v8-arch present.
  

• • arm,cs-dev-assoc: defines a phandle reference to an associated

•  CoreSight trace device. When the associated trace device is enabled,
  

•  then the respective CTI will be enabled. Use in a trig-conns node,
  

•  or in CTI base node when arm,cti-v8-arch present. If the associated
  

•  device has not been registered then the node name will be stored as
  

•  the connection name for later resolution. If the associated device is
  

•  not a CoreSight device or not registered then the node name will
  

•  remain the connection name and automatic enabling will not occur.
  

• • arm,cti-ctm-id: Defines the interconnecting CTM for this device.

•  Use in CTI base node.
  

• • Properties valid in the trig-conns node:

• * arm,trig-in-sigs: List of CTI trigger in signals in use by a
  

•   trig-conns node.
  

• * arm,trig-in-types: List of types for the CTI trigger in
  

•   signals. Types in this array match to the corresponding signal
  

•   in the arm,trig-in-sigs array. If the -types array is smaller,
  

•   or omitted completely, then the types will default to GEN_IO.
  

• * arm,trig-out-sigs: List of CTI trigger out signals in use by a
  

•   trig-conns node.
  

• * arm,trig-out-types: List of types for the CTI trigger out
  

•   signals. Types in this array match to the corresponding signal
  

•   in the arm,trig-out-sigs array. If the "-types" array is
  

•   smaller, or omitted completely, then the types will default
  

•   to GEN_IO.
  

• * arm-trig-filters: List of CTI trigger out signals that will be
  

•   blocked from becoming active, unless filtering is disabled on
  

•   the driver.
  

•  *arm,trig-conn-name: defines a connection name that will be
  

•  displayed, if not overridden by the name of associated device
  

•  from arm,cs-dev-assoc or the CPU. Principle use for CTI that
  

•  are connected to non-CoreSight devices, or external IO.
  

The above lines need to be shifted to the right by one to align with "arm".

+e.g.(5) Combined examples showing all properties:

+a) Minimum CTI definition +cti0: cti@20020000 {

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0x20020000 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";

+};

+b) v8 architecturally defined CTI - CPU + ETM connections. +cti@859000 {

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0x859000 0x1000>;
• clocks = <&rpmcc RPM_QDSS_CLK>;
• clock-names = "apb_pclk";
• arm,cti-v8-arch;
• cpu = <&CPU1>;
• arm,cs-dev-assoc = <&etm1>;

+};

+c) Implementation defined CTI - CPU + ETM connections. +cti@858000 {

•   compatible = "arm,coresight-cti", "arm,primecell";
  

•   reg = <0x858000 0x1000>;
  

•   clocks = <&rpmcc RPM_QDSS_CLK>;
  

•   clock-names = "apb_pclk";
  

•   trig-conns@0 {
  

• 	arm,trig-in-sigs = <4 5 6 7>;
  

• 	arm,trig-in-types = <ETM_EXTOUT
  

• 			  ETM_EXTOUT
  

• 			  ETM_EXTOUT
  

• 			  ETM_EXTOUT>;
  

• 	arm,trig-out-sigs = <4 5 6 7>;
  

• 	arm,trig-out-types = <ETM_EXTIN
  

• 			   ETM_EXTIN
  

• 			   ETM_EXTIN
  

• 			   ETM_EXTIN>;
  

• 	arm,cs-dev-assoc = <&etm0>;
  

•   };
  

•   trig-conns@1 {
  

•        cpu = <&CPU0>;
  

•        arm,trig-in-sigs = <0 1>;
  

•        arm,trig-in-types = <PE_DBGTRIGGER
  

• 			   PE_PMUIRQ>;
  

•        arm,trig-out-sigs=<0 1 2 >;
  

•        arm,trig-out-types = <PE_EDBGREQ
  

• 			  PE_DBGRESTART
  

• 			  PE_CTIIRQ>;
  

•        arm,trig-filters = <0>;
  

•   };
  

•   arm,cti-ctm-id = <1>;
  

+};

+d) Implementation defined CTI - Coresight STM, ETF, ETR connections. +cti@20020000 { /*Juno sys_cti_0 */

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0 0x20020000 0 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";
• power-domains = <&scpi_devpd 0>;
• trig-conns@0 {

• arm,trig-in-sigs=<2 3>;
  

• arm,trig-in-types=<SNK_FULL
  

• 		   SNK_ACQCOMP>;
  

• arm,trig-out-sigs=<0 1>;
  

• arm,trig-out-types=<SNK_FLUSHIN
  

• 		    SNK_TRIGIN>;
  

• arm,cs-dev-assoc = <&etr_sys>;
  

• };
• trig-conns@1 {

• arm,trig-in-sigs=<0 1>;
  

• arm,trig-in-types=<SNK_FULL
  

• 		   SNK_ACQCOMP>;
  

• arm,trig-out-sigs=<7 6>;
  

• arm,trig-out-types=<SNK_FLUSHIN
  

• 		    SNK_TRIGIN>;
  

• arm,cs-dev-assoc = <&etf_sys0>;
  

• };
• trig-conns@2 {

• arm,trig-in-sigs=<4 5 6 7>;
  

• arm,trig-in-types=<STM_TOUT_SPTE
  

• 		   STM_TOUT_SW
  

• 		   STM_TOUT_HETE
  

• 		   STM_ASYNCOUT>;
  

• arm,trig-out-sigs=<4 5>;
  

• arm,trig-out-types=<STM_HWEVENT
  

• 		    STM_HWEVENT>;
  

• arm,cs-dev-assoc = <&stm_sys>;
  

• };
• trig-conns@3 {

• arm,trig-out-sigs=<2 3>;
  

• arm,trig-out-types=<SNK_FLUSHIN
  

• 		    SNK_TRIGIN>;
  

• arm,cs-dev-assoc = <&tpiu_sys>;
  

• };

+};

+e) Implementation defined CTI - none CoreSight component connections. +cti@20110000 { /* Juno sys_cti_1 */

• compatible = "arm,coresight-cti", "arm,primecell";
• reg = <0 0x20110000 0 0x1000>;
• clocks = <&soc_smc50mhz>;
• clock-names = "apb_pclk";
• power-domains = <&scpi_devpd 0>;
• trig-conns@0 {

• arm,trig-in-sigs=<0>;
  

• arm,trig-in-types=<GEN_INTREQ>;
  

• arm,trig-out-sigs=<0>;
  

• arm,trig-out-types=<GEN_HALTREQ>;
  

• arm,trig-conn-name = "sys_profiler";
  

• };
• trig-conns@1 {

• arm,trig-out-sigs=<2 3>;
  

• arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
  

• arm,trig-conn-name = "watchdog";
  

• };
• trig-conns@2 {

• arm,trig-out-sigs=<1 6>;
  

• arm,trig-out-types=<GEN_HALTREQ GEN_RESTARTREQ>;
  

• arm,trig-conn-name = "g_counter";
  

• };

+}; diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt index fcc3bacfd8bc..a24713e48304 100644 --- a/Documentation/devicetree/bindings/arm/coresight.txt +++ b/Documentation/devicetree/bindings/arm/coresight.txt @@ -45,6 +45,10 @@ its hardware characteristcs. - Coresight Address Translation Unit (CATU) "arm,coresight-catu", "arm,primecell";

• - Coresight Cross Trigger Interface (CTI):
  

•   	"arm,coresight-cti", "arm,primecell";
  

• 	See coresight-ect-cti.txt for full CTI definitions.
  

• • reg: physical base address and length of the register set(s) of the component.

@@ -72,6 +76,9 @@ its hardware characteristcs.

• reg-names: the only acceptable values are "stm-base" and "stm-stimulus-base", each corresponding to the areas defined in "reg".

+* Required properties for Coresight Cross Trigger Interface (CTI)

•   See coresight-ect-cti.txt for full CTI definitions.
  

• Required properties for devices that don't show up on the AMBA bus, such as non-configurable replicators and non-configurable funnels:

diff --git a/MAINTAINERS b/MAINTAINERS index 783569e3c4b4..a81f3bd8340a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1582,10 +1582,12 @@ R: Suzuki K Poulose suzuki.poulose@arm.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/hwtracing/coresight/* +F: include/dt-bindings/arm/coresight-cti-dt.h F: Documentation/trace/coresight.txt F: Documentation/trace/coresight-cpu-debug.txt F: Documentation/devicetree/bindings/arm/coresight.txt F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt +F: Documentation/devicetree/bindings/arm/coresight-ect-cti.txt F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: tools/perf/arch/arm/util/pmu.c F: tools/perf/arch/arm/util/auxtrace.c diff --git a/include/dt-bindings/arm/coresight-cti-dt.h b/include/dt-bindings/arm/coresight-cti-dt.h new file mode 100644 index 000000000000..88580b5a0388 --- /dev/null +++ b/include/dt-bindings/arm/coresight-cti-dt.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • This header provides constants for the defined trigger signal
• • types on CoreSight CTI.
• */

+#ifndef _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H +#define _DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H

+#define GEN_IO 0 +#define GEN_INTREQ 1 +#define GEN_INTACK 2 +#define GEN_HALTREQ 3 +#define GEN_RESTARTREQ 4 +#define PE_EDBGREQ 5 +#define PE_DBGRESTART 6 +#define PE_CTIIRQ 7 +#define PE_PMUIRQ 8 +#define PE_DBGTRIGGER 9 +#define ETM_EXTOUT 10 +#define ETM_EXTIN 11 +#define SNK_FULL 12 +#define SNK_ACQCOMP 13 +#define SNK_FLUSHCOMP 14 +#define SNK_FLUSHIN 15 +#define SNK_TRIGIN 16 +#define STM_ASYNCOUT 17 +#define STM_TOUT_SPTE 18 +#define STM_TOUT_SW 19 +#define STM_TOUT_HETE 20 +#define STM_HWEVENT 21 +#define ELA_TSTART 22 +#define ELA_TSTOP 23 +#define ELA_DBGREQ 24

+#endif /*_DT_BINDINGS_ARM_CORESIGHT_CTI_DT_H */

2.17.1