On Thu, Nov 20, 2025 at 01:52:03PM +0000, James Clark wrote:
[...]
config->cntr_ctrl[ctridx] = TRCCNTCTLRn_RLDSELF |FIELD_PREP(TRCCNTCTLRn_RLDSEL_MASK, ETM_RES_SEL_FALSE) |FIELD_PREP(TRCCNTCTLRn_CNTSEL_MASK, ETM_RES_SEL_TRUE);So if we define generic event generators:-
#define ETM4_SEL_RS_PAIR BIT(7) #defiine ETM4_RS_SEL_EVENT_SINGLE(rs_sel_idx) (GENMASK(4:0) & rs_sel_idx) #define ETM4_RS_SEL_EVENT_PAIR(rs_sel_pair_idx) ((GENMASK(3:0) & rs_sel_pair_idx) | ETM4_SEL_RS_PAIR)
these are then reuseable for all registers that need the 8 bit event selectors, beyond just this register.
Thus we now accurately define the fields in the TRCCNTCTLRn
#define TRCCNTCTLRn_RLDEVENT_MASK GENMASK(15, 8)
and use
FIELD_PREP(TRCCNTCTLRn_RLDEVENT_MASK, ETM4_RS_SEL_EVENT_SINGLE(ETM_RES_SEL_FALSE))
etc.
I'm not sure I agree with that, the Arm ARM has CNTEVENT_TYPE as a regular bit in the TRCCNTCTLRn register so it should be set like any other. Hiding it as a subfield of "EVENT" when it always exists and always does the same thing was maybe seen as a bad decision which is why it was updated?
Also IMO, beyond using labels instead of raw numbers, the code should just show what's programmed into the register. ETM4_RS_SEL_EVENT_SINGLE() would be one more macro to jump through to see what's actually happening.
Maybe define a general macro but with extra checking:
#define TRCCNTCTLRn_RLDEVENT_MASK GENMASK(15, 8)
#define ETM4_RS_SEL_EVENT(paired, sel) ({ \ if (paired) \ assert(!(sel & ~GENMASK(3, 0))); \ else \ assert(!(sel & ~GENMASK(4, 0))); \ FIELD_PREP(TRCCNTCTLRn_RLDEVENT_MASK, \ ((paird << 7) | sel)); \ })
Thanks, Leo