Re: [PATCH] coresight: trbe: Add ISB after TRBLIMITR write

On Mon, 09 Jun 2025 11:19:05 +0100, James Clark wrote:

DEN0154 states that hardware will be allowed to ignore writes to TRB* registers while the trace buffer is enabled. Add an ISB to ensure that it's disabled before clearing the other registers.

This is purely defensive because it's expected that arm_trbe_disable() would be called before teardown which has the required ISB.

[...]

Applied, thanks!

[1/1] coresight: trbe: Add ISB after TRBLIMITR write https://git.kernel.org/coresight/c/ba3264a1

Best regards,