CoreSight

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6 participants
2351 discussions

Re: [PATCH] Coresight: tpda/tpdm: remove incorrect __exit annotation

by Suzuki K Poulose

Hi Arnd, On 26/01/2023 16:35, Arnd Bergmann wrote: > From: Arnd Bergmann <arnd(a)arndb.de> > > 'remove' callbacks get called whenever a device is unbound from > the driver, which can get triggered from user space. > > Putting it into the __exit section means that the function gets > dropped in for built-in drivers, as pointed out by this build > warning: > > `tpda_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-tpda.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-tpda.o > `tpdm_remove' referenced in section `.data' of drivers/hwtracing/coresight/coresight-tpdm.o: defined in discarded section `.exit.text' of drivers/hwtracing/coresight/coresight-tpdm.o > Thanks for the fix, I will queue this. Btw, I did try to reproduce it locally, but couldn't trigger the warnings, even with CONFIG_WERROR=y and all CORESIGHT configs builtin. I see other drivers doing the same outside coresight too. Just curious to know why is this any different. Is it specific to "bus" driver (e.g. AMBA) ? Suzuki > Fixes: 5b7916625c01 ("Coresight: Add TPDA link driver") > Fixes: b3c71626a933 ("Coresight: Add coresight TPDM source driver") > Signed-off-by: Arnd Bergmann <arnd(a)arndb.de> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 2 +- > drivers/hwtracing/coresight/coresight-tpdm.c | 2 +- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 19c25c9f6157..382d648529e7 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -174,7 +174,7 @@ static int tpda_probe(struct amba_device *adev, const struct amba_id *id) > return 0; > } > > -static void __exit tpda_remove(struct amba_device *adev) > +static void tpda_remove(struct amba_device *adev) > { > struct tpda_drvdata *drvdata = dev_get_drvdata(&adev->dev); > > diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c > index 349a82bb3270..9479a5e8c672 100644 > --- a/drivers/hwtracing/coresight/coresight-tpdm.c > +++ b/drivers/hwtracing/coresight/coresight-tpdm.c > @@ -223,7 +223,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id) > return 0; > } > > -static void __exit tpdm_remove(struct amba_device *adev) > +static void tpdm_remove(struct amba_device *adev) > { > struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev); >

2 years, 3 months

Re: [PATCH] coresight: tmc-etr: Don't enable ETR when it's not ready

by Suzuki K Poulose

Folks, On 24/01/2023 20:09, Yabin Cui wrote: > Ping for review. And I still can't reproduce it, even if I reduced the > timeout to 2us and tried different workloads. Any suggestions for how > to reproduce it? > I think we should go ahead and fix this in the driver to handle flaky hardware cases. But I would like this to be addressed for all the TMC types, not just ETRs, as Mike pointed out. Thanks Suzuki > Thanks, > Yabin > > On Tue, Jan 10, 2023 at 1:06 PM Yabin Cui <yabinc(a)google.com> wrote: >> >>> Do you have a reproducer for this or some more info? >>> For example is it a regression or has it always been there? And on which >>> platform. >> >> It happens on Pixel 6 and 7. We collect ETM data periodically from some >> internal dogfood devices. The problem has happened several times on >> dogfood devices. But I am still trying to reproduce it locally. >> >> We use the scatter-gather mode of ETR, and allocate a 4M buffer. In userspace, >> we use simpleperf in Android to collect system wide ETM data. What is special >> is, simpleperf disables and reenables perf events every 100ms to flush ETM >> data to perf aux buffer. >> >> Pixel 6 and 7 have hardware monitoring AXI traffic. The hardware finds ETR is >> trying to read from or write to a low invalid address (like 0x2E0000). The >> problem always happens right after the "tmc_etr: timeout while waiting for TMC >> to be Ready" message. And in almost all cases, I can find a "timeout while >> waiting for completion of Manual Flush" message from the previous session. >> >> One log history is below: >> [11484.610008][ C0] coresight tmc_etr0: timeout while waiting for >> completion of Manual Flush >> [11484.610177][ C0] coresight tmc_etr0: timeout while waiting for >> TMC to be Ready >> [11484.615367][ C0] coresight tmc_etr0: timeout while waiting for >> completion of Manual Flush >> [11484.615534][ C0] coresight tmc_etr0: timeout while waiting for >> TMC to be Ready >> [12089.486044][ C0] coresight tmc_etr0: timeout while waiting for >> TMC to be Ready >> AXI error report reading from invalid address >> >> Another log history is below: >> [76709.382650][ C5] coresight tmc_etf1: timeout while waiting for >> TMC to be Ready >> [76709.382852][ C7] coresight tmc_etr0: timeout while waiting for >> completion of Manual Flush >> [76709.382995][ C7] coresight tmc_etr0: timeout while waiting for >> TMC to be Ready >> [76709.384510][ C7] coresight tmc_etr0: timeout while waiting for >> completion of Manual Flush >> [76709.384649][ C7] coresight tmc_etr0: timeout while waiting for >> TMC to be Ready >> [76709.384838][ C0] coresight tmc_etr0: timeout while waiting for >> TMC to be Ready >> AIX error report writing to invalid address >> >> It seems if the previous manual flush doesn't finish gracefully, ETR may not be >> ready for the next enable (even after 10min as in the first log). And if we >> continue to enable ETR, an invalid AXI IO may happen. >> >> Thanks, >> Yabin >> >> On Tue, Jan 10, 2023 at 10:04 AM Suzuki K Poulose >> <suzuki.poulose(a)arm.com> wrote: >>> >>> On 10/01/2023 17:48, Mike Leach wrote: >>>> Hi, >>>> >>>> On Tue, 10 Jan 2023 at 09:30, James Clark <james.clark(a)arm.com> wrote: >>>>> >>>>> >>>>> >>>>> On 09/01/2023 23:43, Yabin Cui wrote: >>>>>> Otherwise, it may cause error in AXI bus and result in a kernel panic. >>>>> >>>>> Hi Yabin, >>>>> >>>>> Thanks for the fix. Do you have a reproducer for this or some more info? >>>>> For example is it a regression or has it always been there? And on which >>>>> platform. >>>>> >>>>> Thanks >>>>> James >>>>> >>>>>> >>>>>> Signed-off-by: Yabin Cui <yabinc(a)google.com> >>>>>> --- >>>>>> .../hwtracing/coresight/coresight-tmc-core.c | 4 +++- >>>>>> .../hwtracing/coresight/coresight-tmc-etr.c | 18 +++++++++++++++--- >>>>>> drivers/hwtracing/coresight/coresight-tmc.h | 2 +- >>>>>> 3 files changed, 19 insertions(+), 5 deletions(-) >>>>>> >>>>>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c >>>>>> index 07abf28ad725..c106d142e632 100644 >>>>>> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c >>>>>> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c >>>>>> @@ -31,7 +31,7 @@ DEFINE_CORESIGHT_DEVLIST(etb_devs, "tmc_etb"); >>>>>> DEFINE_CORESIGHT_DEVLIST(etf_devs, "tmc_etf"); >>>>>> DEFINE_CORESIGHT_DEVLIST(etr_devs, "tmc_etr"); >>>>>> >>>>>> -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) >>>>>> +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) >>>>>> { >>>>>> struct coresight_device *csdev = drvdata->csdev; >>>>>> struct csdev_access *csa = &csdev->access; >>>>>> @@ -40,7 +40,9 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata) >>>>>> if (coresight_timeout(csa, TMC_STS, TMC_STS_TMCREADY_BIT, 1)) { >>>>>> dev_err(&csdev->dev, >>>>>> "timeout while waiting for TMC to be Ready\n"); >>>>>> + return -EBUSY; >>>>>> } >>>>>> + return 0; >>>>>> } >>>>>> >>>>>> void tmc_flush_and_stop(struct tmc_drvdata *drvdata) >>>>>> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c >>>>>> index 867ad8bb9b0c..2da99dd41ed6 100644 >>>>>> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c >>>>>> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c >>>>>> @@ -983,15 +983,21 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata) >>>>>> etr_buf->ops->sync(etr_buf, rrp, rwp); >>>>>> } >>>>>> >>>>>> -static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) >>>>>> +static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) >>>>>> { >>>>>> u32 axictl, sts; >>>>>> struct etr_buf *etr_buf = drvdata->etr_buf; >>>>>> + int rc = 0; >>>>>> >>>>>> CS_UNLOCK(drvdata->base); >>>>>> >>>>>> /* Wait for TMCSReady bit to be set */ >>>>>> - tmc_wait_for_tmcready(drvdata); >>>>>> + rc = tmc_wait_for_tmcready(drvdata); >>>>>> + if (rc) { >>>>>> + dev_err(&drvdata->csdev->dev, "not ready ETR isn't enabled\n"); >>>>>> + CS_LOCK(drvdata->base); >>>>>> + return rc; >>>>>> + } >>>>>> >>>>>> writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ); >>>>>> writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); >>>>>> @@ -1032,6 +1038,7 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) >>>>>> tmc_enable_hw(drvdata); >>>>>> >>>>>> CS_LOCK(drvdata->base); >>>>>> + return rc; >>>>>> } >>>>>> >>>>>> static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, >>>>>> @@ -1060,7 +1067,12 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvdata, >>>>>> rc = coresight_claim_device(drvdata->csdev); >>>>>> if (!rc) { >>>>>> drvdata->etr_buf = etr_buf; >>>>>> - __tmc_etr_enable_hw(drvdata); >>>>>> + rc = __tmc_etr_enable_hw(drvdata); >>>>>> + if (rc) { >>>>>> + drvdata->etr_buf = NULL; >>>>>> + coresight_disclaim_device(drvdata->csdev); >>>>>> + tmc_etr_disable_catu(drvdata); >>>>>> + } >>>>>> } >>>>>> >>>>>> return rc; >>>>>> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h >>>>>> index 66959557cf39..01c0382a29c0 100644 >>>>>> --- a/drivers/hwtracing/coresight/coresight-tmc.h >>>>>> +++ b/drivers/hwtracing/coresight/coresight-tmc.h >>>>>> @@ -255,7 +255,7 @@ struct tmc_sg_table { >>>>>> }; >>>>>> >>>>>> /* Generic functions */ >>>>>> -void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); >>>>>> +int tmc_wait_for_tmcready(struct tmc_drvdata *drvdata); >>>>>> void tmc_flush_and_stop(struct tmc_drvdata *drvdata); >>>>>> void tmc_enable_hw(struct tmc_drvdata *drvdata); >>>>>> void tmc_disable_hw(struct tmc_drvdata *drvdata); >>>> >>>> There is no point in waiting for a timeout, and then carrying on even >>>> when it is exceeded. As such this patch seems reasonable. >>>> We should also apply the same principle to the ETF and ETB devices >>>> which use the same tmc_wait_for_tmcready() function. >>> >>> +1 >>> >>> I am fine with pushing this change, as it is doing the right thing. >>> >>>> >>>> However - the concern is that this appears to be happening on starting >>>> the ETR - there should be no outstanding AXI operations that cause the >>>> system to not be ready - as we will either be using this the first >>>> time after reset, or we should have successfully stopped and flushed >>>> the ETR from the previous operation. This warrants further >>>> investigation - should we be extending the timeout - which is already >>>> at a rather generous 100uS, and do we also need to check the MemErr >>>> bit in the status register? >>> >>> It would be good to dump the value of TMC_STATUS to see what is going >>> on. >>> >>>> >>>> As James says, we need details of when and how the problem occurs - >>>> as far as I know it has not been seen on any systems we currently use >>>> (though could have been missed given the current code) >>> >>> +1 >>> >>> Kind regards >>> Suzuki >>> >>> >>>> >>>> Regards >>>> >>>> Mike >>>> >>>> >>>> -- >>>> Mike Leach >>>> Principal Engineer, ARM Ltd. >>>> Manchester Design Centre. UK >>>

2 years, 3 months

Re: [PATCH] coresight: tmc-etr: Don't enable ETR when it's not ready

by James Clark

On 24/01/2023 20:09, Yabin Cui wrote: > Ping for review. And I still can't reproduce it, even if I reduced the > timeout to 2us and tried different workloads. Any suggestions for how > to reproduce it? > Hi Yabin, I just found this in my kernel log files from a few days ago. Jan 19 15:03:35 n1-sdp kernel: [865337.521413] coresight tmc_etr0: timeout while waiting for completion of Manual Flush Jan 19 15:03:35 n1-sdp kernel: [865337.529351] coresight tmc_etr0: timeout while waiting for TMC to be Ready This is on N1SDP, and I've only been running "normal" perf commands like: perf record -e cs_etm//k -- taskset -c 2 sleep 1 perf record -e cs_etm// -- stress -c 2 -t 1 I also haven't been able to reproduce it since James

2 years, 3 months

[PATCH v2] perf: cs-etm: Improve missing sink warning message

by James Clark

Make the sink error message more similar to the event error message that reminds about missing kernel support. The available sinks are also determined by the hardware so mention that too. Also, usually it's not necessary to specify the sink, so add that as a hint. Now the error for a made up sink looks like this: $ perf record -e cs_etm/@abc/ Couldn't find sink "abc" on event cs_etm/@abc/. Missing kernel or device support? Hint: An appropriate sink will be picked automatically if one isn't is specified. For any error other than ENOENT, the same message as before is displayed. Signed-off-by: James Clark <james.clark(a)arm.com> --- V1 -> V2: Keep old error message unless it's ENOENT tools/perf/arch/arm/util/cs-etm.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 481e170cd3f1..7f71c8a237ff 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -283,9 +283,15 @@ static int cs_etm_set_sink_attr(struct perf_pmu *pmu, ret = perf_pmu__scan_file(pmu, path, "%x", &hash); if (ret != 1) { - pr_err("failed to set sink \"%s\" on event %s with %d (%s)\n", - sink, evsel__name(evsel), errno, - str_error_r(errno, msg, sizeof(msg))); + if (errno == ENOENT) + pr_err("Couldn't find sink \"%s\" on event %s\n" + "Missing kernel or device support?\n\n" + "Hint: An appropriate sink will be picked automatically if one isn't specified.\n", + sink, evsel__name(evsel)); + else + pr_err("Failed to set sink \"%s\" on event %s with %d (%s)\n", + sink, evsel__name(evsel), errno, + str_error_r(errno, msg, sizeof(msg))); return ret; } base-commit: 5670ebf54bd26482f57a094c53bdc562c106e0a9 -- 2.39.1

2 years, 3 months

[PATCH] coresight: perf: Output trace id only once

by Suzuki K Poulose

With the dynamic traceid allocation scheme in, we output the AUX_OUTPUT_HWID packet every time event->start() is called. This could cause too many such records in the perf.data, while only one per CPU throughout the life time of the event is required. Make sure we only output it once. Before this patch: $ perf report -D | grep OUTPUT_HW_ID ... AUX_OUTPUT_HW_ID events: 55 (18.3%) After this patch: $ perf report -D | grep OUTPUT_HW_ID ... AUX_OUTPUT_HW_ID events: 5 ( 1.9%) Cc: Mike Leach <mike.leach(a)linaro.org> Cc: James Clark <james.clark(a)arm.com> Cc: Leo Yan <leo.yan(a)linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-etm-perf.c | 16 ++++++++++++---- drivers/hwtracing/coresight/coresight-etm-perf.h | 2 ++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 12fff661456e..a48c97da8165 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -495,10 +495,18 @@ static void etm_event_start(struct perf_event *event, int flags) if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) goto fail_disable_path; - /* output cpu / trace ID in perf record */ - hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, CS_AUX_HW_ID_CURR_VERSION); - hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, coresight_trace_id_read_cpu_id(cpu)); - perf_report_aux_output_id(event, hw_id); + /* + * output cpu / trace ID in perf record, once for the lifetime + * of the event. + */ + if (!cpumask_test_cpu(cpu, &event_data->aux_hwid_done)) { + cpumask_set_cpu(cpu, &event_data->aux_hwid_done); + hw_id = FIELD_PREP(CS_AUX_HW_ID_VERSION_MASK, + CS_AUX_HW_ID_CURR_VERSION); + hw_id |= FIELD_PREP(CS_AUX_HW_ID_TRACE_ID_MASK, + coresight_trace_id_read_cpu_id(cpu)); + perf_report_aux_output_id(event, hw_id); + } out: /* Tell the perf core the event is alive */ diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.h b/drivers/hwtracing/coresight/coresight-etm-perf.h index 468f7799ab4f..bebbadee2ceb 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.h +++ b/drivers/hwtracing/coresight/coresight-etm-perf.h @@ -48,6 +48,7 @@ struct etm_filters { * struct etm_event_data - Coresight specifics associated to an event * @work: Handle to free allocated memory outside IRQ context. * @mask: Hold the CPU(s) this event was set for. + * @aux_hwid_done: Whether a CPU has emitted the TraceID packet or not. * @snk_config: The sink configuration. * @cfg_hash: The hash id of any coresight config selected. * @path: An array of path, each slot for one CPU. @@ -55,6 +56,7 @@ struct etm_filters { struct etm_event_data { struct work_struct work; cpumask_t mask; + cpumask_t aux_hwid_done; void *snk_config; u32 cfg_hash; struct list_head * __percpu *path; -- 2.34.1

2 years, 3 months

[PATCH] coresight: Fix uninitialised variable use in coresight_disable

by Suzuki K Poulose

Kernel test robot reports: drivers/hwtracing/coresight/coresight-core.c:1176:7: warning: variable 'hash' is used uninitialized whenever switch case is taken [-Wsometimes-uninitialized] case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/hwtracing/coresight/coresight-core.c:1195:24: note: uninitialized use occurs here idr_remove(&path_idr, hash); ^~~~ Fix this by moving the usage of the hash variable to where it actually should have been. Cc: Mao Jinlong <quic_jinlmao(a)quicinc.com> Reported-by: kernel test robot <lkp(a)intel.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> --- drivers/hwtracing/coresight/coresight-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index a798008ac56e..d3bf82c0de1d 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -1189,13 +1189,13 @@ void coresight_disable(struct coresight_device *csdev) pr_err("Path is not found for %s\n", dev_name(&csdev->dev)); goto out; } + idr_remove(&path_idr, hash); break; default: /* We can't be here */ break; } - idr_remove(&path_idr, hash); coresight_disable_path(path); coresight_release_path(path); -- 2.34.1

2 years, 3 months

Re: [PATCH 1/3] coresight etm4x: Early clear TRCOSLAR.OSLK prior to TRCIDR1 read

by Suzuki K Poulose

On 23/01/2023 19:48, Steve Clevenger wrote: > > > On 1/23/2023 9:33 AM, Suzuki K Poulose wrote: >> On 23/01/2023 17:22, Steve Clevenger wrote: >>> >>> >>> On 1/23/2023 2:54 AM, Suzuki K Poulose wrote: >>>> On 21/01/2023 07:30, Steve Clevenger wrote: >>>>> >>>>> Hi Suzuki, >>>>> >>>>> Comments in-line. Please note the approach I attempted while adding in >>>>> the Ampere support was to otherwise not disturb existing driver code >>>>> for >>>>> non-Ampere parts. >>>>> >>>>> Steve >>>>> >>>>> On 1/20/2023 3:12 AM, Suzuki K Poulose wrote: >>>>>> Hi Steve >>>>>> >>>>>> Thanks for the patches. Have a few comments below. >>>>>> >>>>>> On 20/01/2023 00:51, Steve Clevenger wrote: >>>>>>> Add Ampere early clear of ETM TRCOSLAR.OSLK prior to TRCIDR1 access. >>>>>>> Ampere Computing erratum AC03_DEBUG_06 describes an Ampere >>>>>>> Computing design decision MMIO reads are considered the same as an >>>>>>> external debug access. If TRCOSLAR.OSLK is set, the TRCIDR1 access >>>>>>> results in a bus fault followed by a kernel panic. A TRCIDR1 read >>>>>>> is valid regardless of TRCOSLAR.OSLK provided MMIO access >>>>>>> (now deprecated) is supported. >>>>>>> AC03_DEBUG_06 is described in the AmpereOne Developer Errata: >>>>>>> https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-d… >>>>>> >>>>>> Please could you add this erratum to the : >>>>>> >>>>>> Documentation/arm64/silicon-errata.rst ? >>>>>> >>>>>> Given the ETM is v4.6, doesn't it support system instructions and >>>>>> that is causing this issue of "MMIO access is considered external" ? >>>>>> If it does, I think we should drop all of this and simply wire the >>>>>> system instruction access support. >>>> >>>>> That's not the issue in this case. This MMIO access should've been >>>>> allowed by the Ampere ETMv4.6 implementation. Based on comments I've >>>> >>>> That doesn't answe the question. Please could you confirm the value of >>>> ID_AA64DFR0_EL1 on your system ? >>> This ID_AA64DFR0_EL1 value came from a TRACE32 debug session connected >>> to this part. The ID_AA64DFR0_EL1 value is 0x000F01F210307619. So, >>> TraceVer, bits [7:4] are b0001. My understanding is the system register >>> interface must be implemented on all ETMv4.6 parts. >> >> So, I don't understand why we are pushing towards enabling the >> "obsolete" MMIO interface ? Is this because "ACPI" mandates it ? >> Then, please don't. The spec needs an update to reflect the ETMs >> with sysreg access and ETEs. >> >> Why not stick to the system register access* ? >> >> * PS: The ACPI support for the ETM/ETE needs additional changes to the >> CoreSight driver, *not* the CoreSight ACPI spec. @Anshuman is working on >> this at the moment and will be available soon. >> >> The hack patch below should be sufficient to give it a try and if it works. > I don't understand your postscript. Certainly there's driver work to be > done, but I also think the DEN0067 CoreSight ACPI specification needs The issue is having a single HID for ETMs (which from a spec point of view makes sense for) with and without MMIO access. That brings two different components in Linux (AMBA hook for ACPI and a platform driver) compete for the said HID. There are other reasons to disconnect the CoreSight from AMBA framework and manage them directly [0]. So, that needs a bit of ground work to move ETM driver away from AMBA and then we can have a single driver handling both devices. It is much easier on DT based systems, as we have different compatible strings. > update. There's no example for defining a trace implementation without > memory mapped component descriptions. Considering the ACPI as it exists, I have raised this with the concerned people in Arm and can share the update via other channels once we have it. Basically we should be able to reuse the one for MMIO based systems, except the memory resource. The Graph connections remain unaffected by this change. This never made it to the document. > the component graphs are the most important. Please see my last exchange > with Mike Leach. > > My patches were submitted based on the existing CoreSight driver, not > what it should be. Ampere does not have the flexibility to wait for a > decision on some details we've discussed. I'm available to work through Understand. But that doesn't mean we can push something in that is not meant to work the way it should. > any concerns the maintainers have with my submissions. What is the best > way forward here? If this is a system with system instruction access, it should be described as such and can be supported when the above mentioned change is in the kernel. Suzuki > >> Kind regards >> Suzuki >> >>> >>>> >>>> Or, are you able to try this on your ACPI based system and see if you >>>> are able to use the etm ? (UNTESTED hack !) >>>> >>>> >>>> diff --git a/drivers/acpi/acpi_amba.c b/drivers/acpi/acpi_amba.c >>>> index f5b443ab01c2..099966cbac5a 100644 >>>> --- a/drivers/acpi/acpi_amba.c >>>> +++ b/drivers/acpi/acpi_amba.c >>>> @@ -22,7 +22,6 @@ >>>> static const struct acpi_device_id amba_id_list[] = { >>>> {"ARMH0061", 0}, /* PL061 GPIO Device */ >>>> {"ARMH0330", 0}, /* ARM DMA Controller DMA-330 */ >>>> - {"ARMHC500", 0}, /* ARM CoreSight ETM4x */ >>>> {"ARMHC501", 0}, /* ARM CoreSight ETR */ >>>> {"ARMHC502", 0}, /* ARM CoreSight STM */ >>>> {"ARMHC503", 0}, /* ARM CoreSight Debug */ >>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>> b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>> index 1ea8f173cca0..66670533fd54 100644 >>>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>> @@ -3,6 +3,7 @@ >>>> * Copyright (c) 2014, The Linux Foundation. All rights reserved. >>>> */ >>>> >>>> +#include <linux/acpi.h> >>>> #include <linux/bitops.h> >>>> #include <linux/kernel.h> >>>> #include <linux/moduleparam.h> >>>> @@ -2286,12 +2287,22 @@ static const struct of_device_id >>>> etm4_sysreg_match[] = { >>>> {} >>>> }; >>>> >>>> +#ifdef CONFIG_ACPI >>>> +static const struct acpi_device_id etm4x_acpi_ids[] = { >>>> + {"ARMHC500", 0}, /* ARM CoreSight ETM4x */ >>>> + {} >>>> +}; >>>> + >>>> +MODULE_DEVICE_TABLE(acpi, etm4x_acpi_ids); >>>> +#endif >>>> + >>>> static struct platform_driver etm4_platform_driver = { >>>> .probe = etm4_probe_platform_dev, >>>> .remove = etm4_remove_platform_dev, >>>> .driver = { >>>> .name = "coresight-etm4x", >>>> .of_match_table = etm4_sysreg_match, >>>> + .acpi_match_table = ACPI_PTR(etm4x_acpi_ids), >>>> .suppress_bind_attrs = true, >>>> }, >>>> }; >>>> >>>> >>>> >>>> >>>>> read in the driver code, the MMIO read access to TRCIDR1 occurs after a >>>>> TRCDEVARCH access. The comments suggest this was to accommodate >>>>> potentially unreliable TRCDEVARCH (and TRCIDR1) values. This Ampere >>>>> ETMv4.6 allows an MMIO access to TRCDEVARCH, but not to TRCIDR1 unless >>>>> the TRCOSLAR.OSLK lock is cleared first. >>>>> >>>>>> >>>>>>> >>>>>>> Add Ampere ETM PID required for Coresight ETM driver support. >>>>>>> >>>>>>> Signed-off-by: Steve Clevenger <scclevenger(a)os.amperecomputing.com> >>>>>>> --- >>>>>>> .../coresight/coresight-etm4x-core.c | 36 >>>>>>> +++++++++++++++---- >>>>>>> drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ >>>>>>> 2 files changed, 32 insertions(+), 6 deletions(-) >>>>>>> >>>>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>>>>> b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>>>>> index 1cc052979e01..533be1928a09 100644 >>>>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>>>>> @@ -1091,19 +1091,34 @@ static void etm4_init_arch_data(void *info) >>>>>>> drvdata = dev_get_drvdata(init_arg->dev); >>>>>>> csa = init_arg->csa; >>>>>>> + /* Detect the support for OS Lock before we actually use >>>>>>> it */ >>>>>>> + etm_detect_os_lock(drvdata, csa); >>>>>>> + > + /* >>>>>>> + * For ETM implementations that consider MMIO an external access >>>>>>> + * clear TRCOSLAR.OSLK early. >>>>>>> + */ >>>>>>> + if (drvdata->mmio_external) >>>>>>> + etm4_os_unlock_csa(drvdata, csa); >>>>>>> + >>>>>>> /* >>>>>>> * If we are unable to detect the access mechanism, >>>>>>> * or unable to detect the trace unit type, fail >>>>>>> - * early. >>>>>>> + * early. Reset TRCOSLAR.OSLK if cleared. >>>>>>> */ >>>>>>> - if (!etm4_init_csdev_access(drvdata, csa)) >>>>>>> + if (!etm4_init_csdev_access(drvdata, csa)) { >>>>>>> + if (drvdata->mmio_external) >>>>>>> + etm4_os_lock(drvdata); >>>>>> >>>>>> Couldn't this unlock/lock sequence be moved into the >>>>>> etm4_init_csdev_iomem_access() where it actually matters ? >>>>>> >>>>>> Or thinking more about it, we could actually move the unlock step >>>>>> early >>>>>> for all ETMs irrespective of whether they are affected by this >>>>>> erratum. >>>>>> Of course, putting this back, if we fail to detect the ETM properly. >>>>>> I don't see any issue with that. >>>> >>>> >>>>> I agree the lock could be cleared earlier in the code. That's what this >>>>> patch does for Ampere. If it's decided ok to do for other (or all) >>>>> manufacturers, then the Ampere specific ID check goes away in this >>>>> place. The Ampere ID check (and flag) to determine whether the [Patch >>>>> 2/3] 64-bit access is split into 2 ea. 32-bit accesses would remain, or >>>>> use an existing feature mask as suggested by Mike Leach in a later >>>>> review. >>>>> >>>>>> >>>>>>> return; >>>>>>> + } >>>>>>> - /* Detect the support for OS Lock before we actually use >>>>>>> it */ >>>>>>> - etm_detect_os_lock(drvdata, csa); >>>>>>> + /* >>>>>>> + * Make sure all registers are accessible >>>>>>> + * TRCOSLAR.OSLK may already be clear >>>>>>> + */ >>>>>>> + if (!drvdata->mmio_external) >>>>>>> + etm4_os_unlock_csa(drvdata, csa); >>>>>>> - /* Make sure all registers are accessible */ >>>>>>> - etm4_os_unlock_csa(drvdata, csa); >>>>>>> etm4_cs_unlock(drvdata, csa); >>>>>>> etm4_check_arch_features(drvdata, init_arg->pid); >>>>>>> @@ -2027,6 +2042,14 @@ static int etm4_probe(struct device *dev, void >>>>>>> __iomem *base, u32 etm_pid) >>>>>>> init_arg.csa = &access; >>>>>>> init_arg.pid = etm_pid; >>>>>>> + /* >>>>>>> + * Ampere ETM v4.6 considers MMIO access as external. This mask >>>>>>> + * isolates the manufacturer JEP106 ID in the PID. >>>>>>> + * TRCPIDR2 (JEDC|DES_1) << 16 | TRCPIDR1 (DES_0) << 8) >>>>>>> + */ >>>>>> >>>>>> Does it affect all Ampere ETMs ? You seem to be ignoring the >>>>>> PDIR1.PART_1, PDIR0_PART_0 fields, which happens to be 0. >>>> >>>>> This is the first Ampere ETMv4.x implementation. I wrote the ID check >>>>> like this specifically because Ampere does not intend to address this >>>>> for ETM designs in progress. >>>> >>>> I would recommend to make this mask stricter and apply this to the >>>> current implementation. When there are more, we could add this here, >>>> rather than having to leave this work around for all the possible cores. >>>> >>>>> >>>>>> >>>>>>> + if ((init_arg.pid & 0x000FF000) == 0x00096000) >>>>>>> + drvdata->mmio_external = true; >>>>>> Like I said, we may be able to get rid of this flag and do the step >>>>>> for >>>>>> all ETMs. But before all of that, I would like to see if this is >>>>>> problem >>>>>> because we are skipping the system instruction route. >>>>>> >>>> >>>>> We understand MMIO access is deprecated going forward. There is other >>>>> Linux code to be concerned about. For example, AMBA code reads the >>>>> component PID/CID. This discovery code uses mapped values digested from >>>>> the CoreSight ACPI which are the descriptions and graphs for the >>>> >>>> With the "proposed" ACPI support for system register, AMBA would not be >>>> involved at all. >>>> >>>>> manufacturer trace implementation. There may be other Linux code I'm >>>>> not >>>>> aware. Note the ASL examples in ARM Document number: DEN0067 specify >>>>> MMIO locations for every CoreSight component. >>>> >>>> Yes, but this was never updated to cover the system register based >>>> implementations. I will chase this up. >>>> >>>> >>>> Suzuki >>>> >>

2 years, 3 months

Re: [PATCH 1/3] coresight etm4x: Early clear TRCOSLAR.OSLK prior to TRCIDR1 read

by Suzuki K Poulose

On 23/01/2023 19:47, Steve Clevenger wrote: > > > On 1/23/2023 2:54 AM, Mike Leach wrote: >> Hi Steve, >> >> On Sat, 21 Jan 2023 at 07:31, Steve Clevenger >> <scclevenger(a)os.amperecomputing.com> wrote: >>> >>> >>> Hi Mike, >>> >>> Comments in-line. >>> >>> Steve >>> >>> On 1/20/2023 3:45 AM, Mike Leach wrote: >>>> Hi Steve, >>>> >>>> On Fri, 20 Jan 2023 at 00:52, Steve Clevenger >>>> <scclevenger(a)os.amperecomputing.com> wrote: >>>>> >>>>> Add Ampere early clear of ETM TRCOSLAR.OSLK prior to TRCIDR1 access. >>>>> Ampere Computing erratum AC03_DEBUG_06 describes an Ampere >>>>> Computing design decision MMIO reads are considered the same as an >>>>> external debug access. If TRCOSLAR.OSLK is set, the TRCIDR1 access >>>>> results in a bus fault followed by a kernel panic. A TRCIDR1 read >>>>> is valid regardless of TRCOSLAR.OSLK provided MMIO access >>>>> (now deprecated) is supported. >>>>> AC03_DEBUG_06 is described in the AmpereOne Developer Errata: >>>>> https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-d… >>>>> >>>>> Add Ampere ETM PID required for Coresight ETM driver support. >>>>> >>>>> Signed-off-by: Steve Clevenger <scclevenger(a)os.amperecomputing.com> >>>>> --- >>>>> .../coresight/coresight-etm4x-core.c | 36 +++++++++++++++---- >>>>> drivers/hwtracing/coresight/coresight-etm4x.h | 2 ++ >>>>> 2 files changed, 32 insertions(+), 6 deletions(-) >>>>> >>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>>> index 1cc052979e01..533be1928a09 100644 >>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>>>> @@ -1091,19 +1091,34 @@ static void etm4_init_arch_data(void *info) >>>>> drvdata = dev_get_drvdata(init_arg->dev); >>>>> csa = init_arg->csa; >>>>> >>>> >>>> As far as I can tell there appears to be an initialisation issue here. >>>> etm_probe() >>>> ... >>>> struct csdev_access access = { 0 }; >>>> ... >>>> init_arg.csa = &access >>>> >>>> ::call=> etm4_init_arch_data(init_arg) >>>> >>>> Thus csa is uninitialised? >>> It looks to me csa is intended to be initialized to zero? In any case, >>> the Ampere check uses only the ETM pid, which is initialized directly above. >>> >> >> Sorry, I should have been more explicit. >> >> csa is the addressing abstraction used by all the underlying register >> read/write code. >> >> It is initialised to {0} in the calling code, probably to avoid the >> kernel tests complaining about uninitialised use of a variable. >> >> However in the etm4_init_csdev_access() function we are using a base >> address then it is initialised to:- >> >> struct csdev_access { >> io_mem = true; >> *base = io_mem_base_addr; >> }; >> >> and in the access using system registers for an etm4 to: >> >> struct csdev_access { >> io_mem = false; >> *read = etm4x_sysreg_read() >> *write = etm4x_sysreg_write() >> }; > Yes, csa is initialized indirectly in etm4_init_csdev_access via calls > to etm4_init_iomem_access and etm4_init_sysreg_access. So, you are > correct. csa is zero initialized for the call to etm4_detect_os_lock > (TRCOSLSR read) prior to my patch which clears TRCOSLAR.OSLK. The > TRCOSLSR read and TRCOSLAR.OSLK clear default to sysreg access. The csa > initialization problem is an existing bug I didn't see. >> >> Thus all underlying register access can use the correct method for the device. >> >>>> >>>>> + /* Detect the support for OS Lock before we actually use it */ >>>>> + etm_detect_os_lock(drvdata, csa); >>>>> + >> >> Thus passing a 0 init csa object to the etm_detect_os_lock() fn above >> seems to be suspicious. >> >>>>> + /* >>>>> + * For ETM implementations that consider MMIO an external access >>>>> + * clear TRCOSLAR.OSLK early. >>>>> + */ >>>>> + if (drvdata->mmio_external) >>>>> + etm4_os_unlock_csa(drvdata, csa); >>>>> + >>>>> /* >>>>> * If we are unable to detect the access mechanism, >>>>> * or unable to detect the trace unit type, fail >>>>> - * early. >>>>> + * early. Reset TRCOSLAR.OSLK if cleared. >>>>> */ >>>>> - if (!etm4_init_csdev_access(drvdata, csa)) >>>>> + if (!etm4_init_csdev_access(drvdata, csa)) { >>>> >>>> This call initialises csa according to sysreg / iomem access requirements >> >>> csa is initialized only when no drvdata->base exists. >> >> Not so - csa is initialised in both circumstances as described above. >> >>> Under what >>> circumstance would there be no ETM base given the recommended CoreSight >>> ACPI implementation? See the examples in ARM Document number: DEN0067. >> >> >> This will be used in the ETE devices (which share the etm4 driver), or >> any ETM4.6+ that uses the "arm,coresight-etm4x-sysreg" device tree >> binding (not sure what the ACPI equivalent is). >> >> So, either way, you need an init csa, before passing it to the driver calls. > Agreed. See my summary above. > >> >> Later in the initialisation sequence we generate a coresight_device >> object which the csa is bound to, and finally if all is well the >> coresight_device is bound to drvdata at which point the device is >> ready for use. >> >> It is unfortunate, but to handle the two methods of register access, >> the initilialisation process for the driver has become more >> complicated with ordering dependencies - to ensure that the rest of >> the driver remains simpler when accessing device registers. >> >> As Suzuki mentioned - moving this specific lock requirement into the >> _init function would be clearer and ensure that the initialisation >> sequences were observed. > Getting back to the etm4_init_csdev_access implementation, if a > drvdata->base exists, etm4_init_sysreg_access is never called. The > driver doesn't initialize sysreg access if a memory map exists by > design. The existing Coresight ACPI specification only has the option of > describing the manufacturer trace implementation using descriptions of > memory mapped components. As mentioned in my previous comments, this is only a matter of updating the spec. You should be able to use everything same for the ETM, excluding the "MMIO" region. i.e, Device(CPU0) { Name(_HID, "ACPI0010"), ... Device(ETM0) { Name (_HID, "ARMHC500") // ETM Name (_CID, "ARMHC500") // ETM /* No _CRS Memory Resource for sysreg access */ /* Graph Connections as usual, if any ATB is connected */ Name (_DSD , Package () { ... }) ... } // ETM0 } // CPU0 Suzuki > >> >> Regards >> >> Mike >> >>>> >>>> >>>> >>>>> + if (drvdata->mmio_external) >>>>> + etm4_os_lock(drvdata); >>>>> return; >>>>> + } >>>>> >>>>> - /* Detect the support for OS Lock before we actually use it */ >>>>> - etm_detect_os_lock(drvdata, csa); >>>>> + /* >>>>> + * Make sure all registers are accessible >>>>> + * TRCOSLAR.OSLK may already be clear >>>>> + */ >>>>> + if (!drvdata->mmio_external) >>>>> + etm4_os_unlock_csa(drvdata, csa); >>>>> >>>>> - /* Make sure all registers are accessible */ >>>>> - etm4_os_unlock_csa(drvdata, csa); >>>>> etm4_cs_unlock(drvdata, csa); >>>>> >>>>> etm4_check_arch_features(drvdata, init_arg->pid); >>>>> @@ -2027,6 +2042,14 @@ static int etm4_probe(struct device *dev, void __iomem *base, u32 etm_pid) >>>>> init_arg.csa = &access; >>>>> init_arg.pid = etm_pid; >>>>> >>>>> + /* >>>>> + * Ampere ETM v4.6 considers MMIO access as external. This mask >>>>> + * isolates the manufacturer JEP106 ID in the PID. >>>>> + * TRCPIDR2 (JEDC|DES_1) << 16 | TRCPIDR1 (DES_0) << 8) >>>>> + */ >>>>> + if ((init_arg.pid & 0x000FF000) == 0x00096000) >>>>> + drvdata->mmio_external = true; >>>>> + >>>>> /* >>>>> * Serialize against CPUHP callbacks to avoid race condition >>>>> * between the smp call and saving the delayed probe. >>>>> @@ -2192,6 +2215,7 @@ static const struct amba_id etm4_ids[] = { >>>>> CS_AMBA_ID(0x000bb95e), /* Cortex-A57 */ >>>>> CS_AMBA_ID(0x000bb95a), /* Cortex-A72 */ >>>>> CS_AMBA_ID(0x000bb959), /* Cortex-A73 */ >>>>> + CS_AMBA_UCI_ID(0x00096000, uci_id_etm4),/* Ampere ARMv8 */ >>>>> CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),/* Cortex-A35 */ >>>>> CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */ >>>>> CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */ >>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >>>>> index 4b21bb79f168..cf4f9f2e1807 100644 >>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >>>>> @@ -1015,6 +1015,7 @@ struct etmv4_save_state { >>>>> * @skip_power_up: Indicates if an implementation can skip powering up >>>>> * the trace unit. >>>>> * @arch_features: Bitmap of arch features of etmv4 devices. >>>>> + * @mmio_external: True if ETM considers MMIO an external access. >>>>> */ >>>>> struct etmv4_drvdata { >>>>> void __iomem *base; >>>>> @@ -1067,6 +1068,7 @@ struct etmv4_drvdata { >>>>> bool state_needs_restore; >>>>> bool skip_power_up; >>>>> DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); >>>> >>>> Rather than continue to add bools - is it not worthwhile adding to the >>>> bitmap above and extending the arch features API to allow a >>>> "has_feature" call? >>> I can look into this. I agree using a bool for every exception doesn't >>> scale well. Referring to one Suzuki Poulose review comment, his proposal >>> to clear TRCOSLAR.OSLK early for all parts would mean one of these bools >>> could go away. Otherwise, possibly add one (or more) bit definitions for >>> use by the etm4_disable_arch_specific call. The order of this call would >>> need to change, depending. >>> >>>> >>>>> + bool mmio_external; >>>>> }; >>>>> >>>>> /* Address comparator access types */ >>>>> -- >>>>> 2.25.1 >>>>> >>>> Regards >>>> >>>> Mike >> >> >>

2 years, 3 months

[PATCH] perf: cs-etm: Improve missing sink warning message

by James Clark

Make the sink error message more similar to the event error message that reminds about missing kernel support. The available sinks are also determined by the hardware so mention that too. Also, usually it's not necessary to specify the sink, so add that as a hint. Now the error for a made up sink looks like this: $ perf record -e cs_etm/@abc/ Couldn't find sink "abc" on event cs_etm/@abc/. Missing kernel or device support? Errno: 2 (No such file or directory) Hint: An appropriate sink will picked automatically if none is specified. Signed-off-by: James Clark <james.clark(a)arm.com> --- tools/perf/arch/arm/util/cs-etm.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 481e170cd3f1..c6195a7a3cbf 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -283,7 +283,9 @@ static int cs_etm_set_sink_attr(struct perf_pmu *pmu, ret = perf_pmu__scan_file(pmu, path, "%x", &hash); if (ret != 1) { - pr_err("failed to set sink \"%s\" on event %s with %d (%s)\n", + pr_err("Couldn't find sink \"%s\" on event %s\n" + "Missing kernel or device support? errno: %d (%s)\n\n" + "Hint: An appropriate sink will picked automatically if one isn't specified.\n", sink, evsel__name(evsel), errno, str_error_r(errno, msg, sizeof(msg))); return ret; base-commit: 5670ebf54bd26482f57a094c53bdc562c106e0a9 -- 2.39.1

2 years, 3 months

Re: [PATCH 2/3] coresight etm4x: Add 32-bit read/write option to split 64-bit words

by Suzuki K Poulose

On 22/01/2023 08:32, Steve Clevenger wrote: > > Hi Suzuki, > > Comments in-line. > > Steve > > On 1/20/2023 3:19 AM, Suzuki K Poulose wrote: >> On 20/01/2023 00:51, Steve Clevenger wrote: >>> Add 32-bit read/write access option for Ampere ETMv4.6 64-bit registers. >>> Ampere Computing erratum AC03_DEBUG_10 describes a design decision where >>> 64-bit read/write access is not supported for the ETMv4.6 implementation. >>> These 64-bit registers must be accessed as 2 ea. 32-bit registers. >>> AC03_DEBUG_10 is described in the AmpereOne Developer Errata: >>> https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-d… >> >> As with the previous comment, please : >> a) If this is because of the system instruction access support >> b) Document the erratum >> > I presume you're referring to your previous comment about adding these > errata to "Documentation/arm64/silicon-errata.rst". Let me see if > there's any heartburn with this internal to Ampere. I don't expect there > to be. > >>> >>> Fix drvdata->nr_addr_cmp for() loop range bug to drvdata->nr_addr_cmp * 2 >>> in etm_enable_hw. >> >> Good catch ! Please separate this out and send it as a fix. I can queue >> this. > I'll submit it as a separate patch. > >> >>> >>> Signed-off-by: Steve Clevenger <scclevenger(a)os.amperecomputing.com> >>> --- >>> .../coresight/coresight-etm4x-core.c | 81 ++++++++++++++----- >>> drivers/hwtracing/coresight/coresight-etm4x.h | 32 ++++++++ >>> 2 files changed, 93 insertions(+), 20 deletions(-) >>> >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> index 533be1928a09..bf4daa649cdf 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >>> @@ -452,18 +452,31 @@ static int etm4_enable_hw(struct etmv4_drvdata >>> *drvdata) >>> if (etm4x_sspcicrn_present(drvdata, i)) >>> etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], >>> TRCSSPCICRn(i)); >>> } >>> - for (i = 0; i < drvdata->nr_addr_cmp; i++) { >>> - etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); >>> - etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); >>> + for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { >>> + if (drvdata->no_quad_mmio) { >>> + etm4x_split_write64(csa, config->addr_val[i], TRCACVRn(i)); >>> + etm4x_split_write64(csa, config->addr_acc[i], TRCACATRn(i)); >>> + } else { >>> + etm4x_relaxed_write64(csa, config->addr_val[i], >>> TRCACVRn(i)); >>> + etm4x_relaxed_write64(csa, config->addr_acc[i], >>> TRCACATRn(i)); >>> + } >>> + } >> >> Something like this can be leave some places out. I think we could hide >> it under the generic helpers and handle it there. May be "struct >> csdev_access" can cache this "no_quad_mmio" and do the right thing ? > I'm not sure what you're suggesting here. Please be more specific. > e.g., struct csdev_access { bool no_64bit_access; } And use the csdev_*_ operations could : if (csa->no_64bit_access) { split access } else { } i.e., move the tracking of no_quad_mmio to "csa" from "drvdata" Suzuki >> >> >>> + for (i = 0; i < drvdata->numcidc; i++) { >>> + if (drvdata->no_quad_mmio) >>> + etm4x_split_write64(csa, config->ctxid_pid[i], >>> TRCCIDCVRn(i)); >>> + else >>> + etm4x_relaxed_write64(csa, config->ctxid_pid[i], >>> TRCCIDCVRn(i)); >>> } >>> - for (i = 0; i < drvdata->numcidc; i++) >>> - etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); >>> etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); >>> if (drvdata->numcidc > 4) >>> etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); >>> - for (i = 0; i < drvdata->numvmidc; i++) >>> - etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); >>> + for (i = 0; i < drvdata->numvmidc; i++) { >>> + if (drvdata->no_quad_mmio) >>> + etm4x_split_write64(csa, config->vmid_val[i], >>> TRCVMIDCVRn(i)); >>> + else >>> + etm4x_relaxed_write64(csa, config->vmid_val[i], >>> TRCVMIDCVRn(i)); >>> + } >>> etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); >>> if (drvdata->numvmidc > 4) >>> etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); >>> @@ -1670,8 +1683,13 @@ static int __etm4_cpu_save(struct etmv4_drvdata >>> *drvdata) >>> } >>> for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { >>> - state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); >>> - state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); >>> + if (drvdata->no_quad_mmio) { >>> + state->trcacvr[i] = etm4x_split_read64(csa, TRCACVRn(i)); >>> + state->trcacatr[i] = etm4x_split_read64(csa, TRCACATRn(i)); >>> + } else { >>> + state->trcacvr[i] = etm4x_read64(csa, TRCACVRn(i)); >>> + state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); >>> + } >>> } >>> /* >>> @@ -1681,11 +1699,19 @@ static int __etm4_cpu_save(struct >>> etmv4_drvdata *drvdata) >>> * unit") of ARM IHI 0064D. >>> */ >>> - for (i = 0; i < drvdata->numcidc; i++) >>> - state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); >>> + for (i = 0; i < drvdata->numcidc; i++) { >>> + if (drvdata->no_quad_mmio) >>> + state->trccidcvr[i] = etm4x_split_read64(csa, >>> TRCCIDCVRn(i)); >>> + else >>> + state->trccidcvr[i] = etm4x_read64(csa, TRCCIDCVRn(i)); >>> + } >>> - for (i = 0; i < drvdata->numvmidc; i++) >>> - state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); >>> + for (i = 0; i < drvdata->numvmidc; i++) { >>> + if (drvdata->no_quad_mmio) >>> + state->trcvmidcvr[i] = etm4x_split_read64(csa, >>> TRCVMIDCVRn(i)); >>> + else >>> + state->trcvmidcvr[i] = etm4x_read64(csa, TRCVMIDCVRn(i)); >>> + } >>> state->trccidcctlr0 = etm4x_read32(csa, TRCCIDCCTLR0); >>> if (drvdata->numcidc > 4) >>> @@ -1799,15 +1825,28 @@ static void __etm4_cpu_restore(struct >>> etmv4_drvdata *drvdata) >>> } >>> for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) { >>> - etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); >>> - etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); >>> + if (drvdata->no_quad_mmio) { >>> + etm4x_split_write64(csa, state->trcacvr[i], TRCACVRn(i)); >>> + etm4x_split_write64(csa, state->trcacatr[i], TRCACATRn(i)); >>> + } else { >>> + etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); >>> + etm4x_relaxed_write64(csa, state->trcacatr[i], >>> TRCACATRn(i)); >>> + } >>> } >>> - for (i = 0; i < drvdata->numcidc; i++) >>> - etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); >>> + for (i = 0; i < drvdata->numcidc; i++) { >>> + if (drvdata->no_quad_mmio) >>> + etm4x_split_write64(csa, state->trccidcvr[i], >>> TRCCIDCVRn(i)); >>> + else >>> + etm4x_relaxed_write64(csa, state->trccidcvr[i], >>> TRCCIDCVRn(i)); >>> + } >>> - for (i = 0; i < drvdata->numvmidc; i++) >>> - etm4x_relaxed_write64(csa, state->trcvmidcvr[i], >>> TRCVMIDCVRn(i)); >>> + for (i = 0; i < drvdata->numvmidc; i++) { >>> + if (drvdata->no_quad_mmio) >>> + etm4x_split_write64(csa, state->trcvmidcvr[i], >>> TRCVMIDCVRn(i)); >>> + else >>> + etm4x_relaxed_write64(csa, state->trcvmidcvr[i], >>> TRCVMIDCVRn(i)); >>> + } >>> etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); >>> if (drvdata->numcidc > 4) >>> @@ -2047,8 +2086,10 @@ static int etm4_probe(struct device *dev, void >>> __iomem *base, u32 etm_pid) >>> * isolates the manufacturer JEP106 ID in the PID. >>> * TRCPIDR2 (JEDC|DES_1) << 16 | TRCPIDR1 (DES_0) << 8) >>> */ >>> - if ((init_arg.pid & 0x000FF000) == 0x00096000) >>> + if ((init_arg.pid & 0x000FF000) == 0x00096000) { >>> drvdata->mmio_external = true; >>> + drvdata->no_quad_mmio = true; >>> + } >>> /* >>> * Serialize against CPUHP callbacks to avoid race condition >>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h >>> b/drivers/hwtracing/coresight/coresight-etm4x.h >>> index cf4f9f2e1807..0650bcdff410 100644 >>> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >>> @@ -1016,6 +1016,7 @@ struct etmv4_save_state { >>> * the trace unit. >>> * @arch_features: Bitmap of arch features of etmv4 devices. >>> * @mmio_external: True if ETM considers MMIO an external access. >>> + * @no_quad_mmio: True if ETM does not support 64-bit (quad) access. >>> */ >>> struct etmv4_drvdata { >>> void __iomem *base; >>> @@ -1069,6 +1070,7 @@ struct etmv4_drvdata { >>> bool skip_power_up; >>> DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); >>> bool mmio_external; >>> + bool no_quad_mmio; >>> }; >>> /* Address comparator access types */ >>> @@ -1093,6 +1095,36 @@ void etm4_config_trace_mode(struct etmv4_config >>> *config); >>> u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit); >>> void etm4x_sysreg_write(u64 val, u32 offset, bool _relaxed, bool >>> _64bit); >>> +/* 64-bit aligned to convert 64-bit access to 2 ea. 32-bit access */ >>> +#pragma pack(push, 8) >>> + >>> +struct etm_quad_split { >>> + u32 lsw; >>> + u32 msw; >>> +}; >>> + >>> +#pragma pack(pop) >>> + >>> +static inline u64 etm4x_split_read64(struct csdev_access *csa, >>> unsigned int offset) >>> +{ >>> + struct etm_quad_split container; >>> + >>> + container.lsw = etm4x_read32(csa, offset); >>> + container.msw = etm4x_read32(csa, offset + sizeof(u32)); >>> + >>> + return *(u64 *) &container; >> >> Wouldn't this break with the "endianness" flip ? (Not that we have BE >> implementations). Could we not combine the two values to a 64bit value >> and pass that instead ? > The split implementation writes/reads 32-bit words to/from 2 consecutive > 32-bit aligned memory addresses independent of endianness so it doesn't > care. I'm not sure I understand what you're getting at by combining the > 2 ea. 32-bit values into a 1 ea. 64-bit value. The etm4x_split_read64 > and etm4x_split_write64 calls both use 64-bit values in and out. > Internal to this code, both read and write accesses must use 32-bit values. > >> >> Similarly below. >> >> Suzuki >> >>> +} >>> + >>> +static inline void etm4x_split_write64(struct csdev_access *csa, u64 >>> quad, unsigned int offset) >>> +{ >>> + struct etm_quad_split container; >>> + >>> + *(u64 *) &container = quad; >>> + >>> + etm4x_relaxed_write32(csa, container.lsw, offset); >>> + etm4x_relaxed_write32(csa, container.msw, offset + sizeof(u32)); >>> +} >>> + >>> static inline bool etm4x_is_ete(struct etmv4_drvdata *drvdata) >>> { >>> return drvdata->arch >= ETM_ARCH_ETE; >>

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