CoreSight

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2387 discussions

Re: [PATCH] perf scripts python arm-cs-trace-disasm.py: Skip disasm if address continuity is broken

by James Clark

On 22/07/2024 11:02 am, Ganapatrao Kulkarni wrote: > > Hi James, > > On 19-07-2024 08:09 pm, James Clark wrote: >> >> >> On 19/07/2024 10:26 am, Ganapatrao Kulkarni wrote: >>> To generate the instruction tracing, script uses 2 contiguous packets >>> address range. If there a continuity brake due to discontiguous branch >>> address, it is required to reset the tracing and start tracing with the >>> new set of contiguous packets. >>> >>> Adding change to identify the break and complete the remaining tracing >>> of current packets and restart tracing from new set of packets, if >>> continuity is established. >>> >> >> Hi Ganapatrao, >> >> Can you add a before and after example of what's changed to the commit >> message? It wasn't immediately obvious to me if this is adding missing >> output, or it was correcting the tail end of the output that was >> previously wrong. > > It is adding tail end of the trace as well avoiding the segfault of the > perf application. With out this change the perf segfaults with as below log > > > ./perf script --script=python:./scripts/python/arm-cs-trace-disasm.py -- > -d objdump -k ../../vmlinux -v $* > dump > objdump: error: the stop address should be after the start address > Traceback (most recent call last): > File "./scripts/python/arm-cs-trace-disasm.py", line 271, in > process_event > print_disam(dso_fname, dso_vm_start, start_addr, stop_addr) > File "./scripts/python/arm-cs-trace-disasm.py", line 105, in print_disam > for line in read_disam(dso_fname, dso_start, start_addr, stop_addr): > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > File "./scripts/python/arm-cs-trace-disasm.py", line 99, in read_disam > disasm_output = check_output(disasm).decode('utf-8').split('\n') > ^^^^^^^^^^^^^^^^^^^^ > File "/usr/lib64/python3.12/subprocess.py", line 466, in check_output > return run(*popenargs, stdout=PIPE, timeout=timeout, check=True, > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > File "/usr/lib64/python3.12/subprocess.py", line 571, in run > raise CalledProcessError(retcode, process.args, > subprocess.CalledProcessError: Command '['objdump', '-d', '-z', > '--start-address=0xffff80008125b758', > '--stop-address=0xffff80008125a934', '../../vmlinux']' returned non-zero > exit status 1. > Fatal Python error: handler_call_die: problem in Python trace event handler > Python runtime state: initialized > > Current thread 0x0000ffffb05054e0 (most recent call first): > <no Python frame> > > Extension modules: perf_trace_context, systemd._journal, > systemd._reader, systemd.id128, report._py3report, _dbus_bindings, > problem._py3abrt (total: 7) > Aborted (core dumped) > >> >>> Signed-off-by: Ganapatrao Kulkarni <gankulkarni(a)os.amperecomputing.com> >>> --- >>> tools/perf/scripts/python/arm-cs-trace-disasm.py | 10 ++++++++++ >>> 1 file changed, 10 insertions(+) >>> >>> diff --git a/tools/perf/scripts/python/arm-cs-trace-disasm.py >>> b/tools/perf/scripts/python/arm-cs-trace-disasm.py >>> index d973c2baed1c..ad10cee2c35e 100755 >>> --- a/tools/perf/scripts/python/arm-cs-trace-disasm.py >>> +++ b/tools/perf/scripts/python/arm-cs-trace-disasm.py >>> @@ -198,6 +198,10 @@ def process_event(param_dict): >>> cpu_data[str(cpu) + 'addr'] = addr >>> return >>> + if (cpu_data.get(str(cpu) + 'ip') == None): >>> + cpu_data[str(cpu) + 'ip'] = ip >>> + >> >> Do you need to write into the global cpu_data here? Doesn't it get >> overwritten after you load it back into 'prev_ip' > > No, the logic is same as holding the addr of previous packet. > Saving the previous packet saved ip in to prev_ip before overwriting > with the current packet. It's not exactly the same logic as holding the addr of the previous sample. For addr, we return on the first None, with your change we now "pretend" that the second one is also the previous one: if (cpu_data.get(str(cpu) + 'addr') == None): cpu_data[str(cpu) + 'addr'] = addr return <----------------------------sample 0 return if (cpu_data.get(str(cpu) + 'ip') == None): cpu_data[str(cpu) + 'ip'] = ip <---- sample 1 save but no return Then for sample 1 'prev_ip' is actually now the 'current' IP: prev_ip = cpu_data[str(cpu) + 'ip'] This means that prev_ip is sometimes the previous sample's IP only sometimes (samples following 1), otherwise it's the current IP. Does your fix actually require this bit? Because we already save the 'real' previous one: cpu_data[str(cpu) + 'ip'] = stop_addr Also normally we save ip + 4 (stop_addr), where as you save ip. It's not clear why there is no need to add the 4? >> >> prev_ip = cpu_data[str(cpu) + 'ip'] >> >> ... then ... >> >> # Record for previous sample packet >> cpu_data[str(cpu) + 'addr'] = addr >> cpu_data[str(cpu) + 'ip'] = stop_addr >> >> Would a local variable not accomplish the same thing? > > No, We need global to hold the ip of previous packet. >> >>> + prev_ip = cpu_data[str(cpu) + 'ip'] >>> if (options.verbose == True): >>> print("Event type: %s" % name) >>> @@ -243,12 +247,18 @@ def process_event(param_dict): >>> # Record for previous sample packet >>> cpu_data[str(cpu) + 'addr'] = addr >>> + cpu_data[str(cpu) + 'ip'] = stop_addr >>> # Handle CS_ETM_TRACE_ON packet if start_addr=0 and stop_addr=4 >>> if (start_addr == 0 and stop_addr == 4): >>> print("CPU%d: CS_ETM_TRACE_ON packet is inserted" % cpu) >>> return >>> + if (stop_addr < start_addr): >>> + # Continuity of the Packets broken, set start_addr to previous >>> + # packet ip to complete the remaining tracing of the address >>> range. After looking a bit more I'm also not sure why stop_addr < start_addr signifies a discontinuity. What if the discontinuity ends up with stop_addr > start_addr? There's no reason it can't jump forwards as well as backwards. Can you share the 3 samples from the --verbose output to the script that cause the issue? I see discontinuities as having the branch source (ip) set to 0 which is what we do at the start: Sample = { cpu: 0000 addr: 0x0000ffffb807adac phys_addr: 0x0000000000000000 ip: 0x0000000000000000 pid: 28388 } Then the ending one has the branch target (addr) set to 0: Sample = { cpu: 0000 addr: 0x0000000000000000 phys_addr: 0x0000000000000000 ip: 0x0000ffffb7eee168 pid: 28388 } And it doesn't hit objdump because of the range check: Start address 0x0 is out of range ... So I don't see any missing disassembly or crashes for this. >>> + start_addr = prev_ip >>> + >>> if (start_addr < int(dso_start) or start_addr > int(dso_end)): >>> print("Start address 0x%x is out of range [ 0x%x .. 0x%x ] >>> for dso %s" % (start_addr, int(dso_start), int(dso_end), dso)) >>> return > > Thanks, > Ganapat

11 months, 2 weeks

Re: [PATCH v2 1/4] Coresight: Add trace_id function to collect trace ID

by Mike Leach

Hi, This patch has a number of issues:- 1) The new dynamic trace ID patchset to use per sink ID maps makes this set unusable. perf supplies a trace ID map for each sink used. - see https://lists.linaro.org/archives/list/coresight@lists.linaro.org/thread/JE… 2) See etm4_enable_perf() - in the perf context a locked version of the read trace ID cannot be used - therefore any path that calls etm4_read_alloc_trace_id() (or equivalent for other sources) in perf mode may result in lockdep issues. 3) on enable: given a cpu number, the trace ID can be read from the id maps rather than needing a new function in ops 4) on disable: trace id can be read directly from the source driver data - again removing need for a new trace_id function in ops. Regards Mike On Fri, 5 Jul 2024 at 10:01, Jie Gan <quic_jiegan(a)quicinc.com> wrote: > > Add 'trace_id' function pointer in ops. It's responsible for collect the > trace ID of the device. > > Add 'struct cs_sink_data' to store the data used by coresight_enable_path/ > coresight_disable_path. The structure will be transmitted to the helper and > sink device. > > Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 53 +++++++++++++++---- > drivers/hwtracing/coresight/coresight-etb10.c | 3 +- > .../hwtracing/coresight/coresight-etm-perf.c | 34 ++++++++++-- > .../coresight/coresight-etm3x-core.c | 14 +++++ > .../coresight/coresight-etm4x-core.c | 13 +++++ > drivers/hwtracing/coresight/coresight-priv.h | 12 ++++- > drivers/hwtracing/coresight/coresight-stm.c | 13 +++++ > drivers/hwtracing/coresight/coresight-sysfs.c | 24 +++++++-- > .../hwtracing/coresight/coresight-tmc-etf.c | 3 +- > .../hwtracing/coresight/coresight-tmc-etr.c | 6 ++- > drivers/hwtracing/coresight/coresight-tpda.c | 13 +++++ > drivers/hwtracing/coresight/coresight-trbe.c | 4 +- > drivers/hwtracing/coresight/ultrasoc-smb.c | 3 +- > include/linux/coresight.h | 4 ++ > 14 files changed, 174 insertions(+), 25 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 9fc6f6b863e0..f414e66f4cda 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -297,12 +297,12 @@ static int coresight_enable_helper(struct coresight_device *csdev, > return helper_ops(csdev)->enable(csdev, mode, data); > } > > -static void coresight_disable_helper(struct coresight_device *csdev) > +static void coresight_disable_helper(struct coresight_device *csdev, void *data) > { > - helper_ops(csdev)->disable(csdev, NULL); > + helper_ops(csdev)->disable(csdev, data); > } > > -static void coresight_disable_helpers(struct coresight_device *csdev) > +static void coresight_disable_helpers(struct coresight_device *csdev, void *data) > { > int i; > struct coresight_device *helper; > @@ -310,7 +310,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) > for (i = 0; i < csdev->pdata->nr_outconns; ++i) { > helper = csdev->pdata->out_conns[i]->dest_dev; > if (helper && coresight_is_helper(helper)) > - coresight_disable_helper(helper); > + coresight_disable_helper(helper, data); > } > } > > @@ -327,7 +327,7 @@ static void coresight_disable_helpers(struct coresight_device *csdev) > void coresight_disable_source(struct coresight_device *csdev, void *data) > { > source_ops(csdev)->disable(csdev, data); > - coresight_disable_helpers(csdev); > + coresight_disable_helpers(csdev, NULL); > } > EXPORT_SYMBOL_GPL(coresight_disable_source); > > @@ -337,7 +337,8 @@ EXPORT_SYMBOL_GPL(coresight_disable_source); > * disabled. > */ > static void coresight_disable_path_from(struct list_head *path, > - struct coresight_node *nd) > + struct coresight_node *nd, > + void *sink_data) > { > u32 type; > struct coresight_device *csdev, *parent, *child; > @@ -382,13 +383,13 @@ static void coresight_disable_path_from(struct list_head *path, > } > > /* Disable all helpers adjacent along the path last */ > - coresight_disable_helpers(csdev); > + coresight_disable_helpers(csdev, sink_data); > } > } > > -void coresight_disable_path(struct list_head *path) > +void coresight_disable_path(struct list_head *path, void *sink_data) > { > - coresight_disable_path_from(path, NULL); > + coresight_disable_path_from(path, NULL, sink_data); > } > EXPORT_SYMBOL_GPL(coresight_disable_path); > > @@ -468,10 +469,42 @@ int coresight_enable_path(struct list_head *path, enum cs_mode mode, > out: > return ret; > err: > - coresight_disable_path_from(path, nd); > + coresight_disable_path_from(path, nd, sink_data); > goto out; > } > > +int coresight_read_traceid(struct list_head *path) > +{ > + int trace_id, type; > + struct coresight_device *csdev; > + struct coresight_node *nd; > + > + list_for_each_entry(nd, path, link) { > + csdev = nd->csdev; > + type = csdev->type; > + > + switch(type) { > + case CORESIGHT_DEV_TYPE_SOURCE: > + if (source_ops(csdev)->trace_id != NULL) { > + trace_id = source_ops(csdev)->trace_id(csdev); > + if (trace_id > 0) > + return trace_id; > + } > + break; > + case CORESIGHT_DEV_TYPE_LINK: > + if (link_ops(csdev)->trace_id != NULL) { > + trace_id = link_ops(csdev)->trace_id(csdev); > + if (trace_id > 0) > + return trace_id; > + } > + break; > + default: > + break; > + } > + } > + return -EINVAL; > +} > + > struct coresight_device *coresight_get_sink(struct list_head *path) > { > struct coresight_device *csdev; > diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c > index 7edd3f1d0d46..05e620529c14 100644 > --- a/drivers/hwtracing/coresight/coresight-etb10.c > +++ b/drivers/hwtracing/coresight/coresight-etb10.c > @@ -173,7 +173,8 @@ static int etb_enable_perf(struct coresight_device *csdev, void *data) > pid_t pid; > unsigned long flags; > struct etb_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > - struct perf_output_handle *handle = data; > + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; > + struct perf_output_handle *handle = sink_data->handle; > struct cs_buffers *buf = etm_perf_sink_config(handle); > > spin_lock_irqsave(&drvdata->spinlock, flags); > diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c > index c0c60e6a1703..8b155765b959 100644 > --- a/drivers/hwtracing/coresight/coresight-etm-perf.c > +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c > @@ -452,6 +452,7 @@ static void etm_event_start(struct perf_event *event, int flags) > struct perf_output_handle *handle = &ctxt->handle; > struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu); > struct list_head *path; > + struct cs_sink_data *sink_data = NULL; > u64 hw_id; > > if (!csdev) > @@ -490,9 +491,18 @@ static void etm_event_start(struct perf_event *event, int flags) > if (WARN_ON_ONCE(!sink)) > goto fail_end_stop; > > + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); > + if (!sink_data) > + goto fail_end_stop; > + > + sink_data->sink = sink; > + sink_data->traceid = coresight_read_traceid(path); > + sink_data->handle = handle; > /* Nothing will happen without a path */ > - if (coresight_enable_path(path, CS_MODE_PERF, handle)) > + if (coresight_enable_path(path, CS_MODE_PERF, sink_data)) { > + kfree(sink_data); > goto fail_end_stop; > + } > > /* Finally enable the tracer */ > if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF)) > @@ -511,6 +521,7 @@ static void etm_event_start(struct perf_event *event, int flags) > perf_report_aux_output_id(event, hw_id); > } > > + kfree(sink_data); > out: > /* Tell the perf core the event is alive */ > event->hw.state = 0; > @@ -519,7 +530,8 @@ static void etm_event_start(struct perf_event *event, int flags) > return; > > fail_disable_path: > - coresight_disable_path(path); > + coresight_disable_path(path, sink_data); > + kfree(sink_data); > fail_end_stop: > /* > * Check if the handle is still associated with the event, > @@ -544,6 +556,7 @@ static void etm_event_stop(struct perf_event *event, int mode) > struct perf_output_handle *handle = &ctxt->handle; > struct etm_event_data *event_data; > struct list_head *path; > + struct cs_sink_data *sink_data = NULL; > > /* > * If we still have access to the event_data via handle, > @@ -588,6 +601,10 @@ static void etm_event_stop(struct perf_event *event, int mode) > if (!sink) > return; > > + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); > + if (!sink_data) > + return; > + > /* stop tracer */ > coresight_disable_source(csdev, event); > > @@ -601,12 +618,16 @@ static void etm_event_stop(struct perf_event *event, int mode) > * have to do anything here. > */ > if (handle->event && (mode & PERF_EF_UPDATE)) { > - if (WARN_ON_ONCE(handle->event != event)) > + if (WARN_ON_ONCE(handle->event != event)) { > + kfree(sink_data); > return; > + } > > /* update trace information */ > - if (!sink_ops(sink)->update_buffer) > + if (!sink_ops(sink)->update_buffer) { > + kfree(sink_data); > return; > + } > > size = sink_ops(sink)->update_buffer(sink, handle, > event_data->snk_config); > @@ -627,8 +648,11 @@ static void etm_event_stop(struct perf_event *event, int mode) > WARN_ON(size); > } > > + sink_data->sink = sink; > + sink_data->traceid = coresight_read_traceid(path); > /* Disabling the path make its elements available to other sessions */ > - coresight_disable_path(path); > + coresight_disable_path(path, sink_data); > + kfree(sink_data); > } > > static int etm_event_add(struct perf_event *event, int mode) > diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c > index 8b362605d242..27e973749050 100644 > --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c > @@ -696,10 +696,24 @@ static void etm_disable(struct coresight_device *csdev, > coresight_set_mode(csdev, CS_MODE_DISABLED); > } > > +static int etm_trace_id(struct coresight_device *csdev) > +{ > + struct etm_drvdata *drvdata; > + > + if (csdev == NULL) > + return -EINVAL; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return etm_read_alloc_trace_id(drvdata); > +} > + > + > static const struct coresight_ops_source etm_source_ops = { > .cpu_id = etm_cpu_id, > .enable = etm_enable, > .disable = etm_disable, > + .trace_id = etm_trace_id, > }; > > static const struct coresight_ops etm_cs_ops = { > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index bf01f01964cf..8c3e9bfb9a9c 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1024,10 +1024,23 @@ static void etm4_disable(struct coresight_device *csdev, > coresight_set_mode(csdev, CS_MODE_DISABLED); > } > > +static int etm4_trace_id(struct coresight_device *csdev) > +{ > + struct etmv4_drvdata *drvdata; > + > + if (csdev == NULL) > + return -EINVAL; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return etm4_read_alloc_trace_id(drvdata); > +} > + > static const struct coresight_ops_source etm4_source_ops = { > .cpu_id = etm4_cpu_id, > .enable = etm4_enable, > .disable = etm4_disable, > + .trace_id = etm4_trace_id, > }; > > static const struct coresight_ops etm4_cs_ops = { > diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h > index 61a46d3bdcc8..e2576531f796 100644 > --- a/drivers/hwtracing/coresight/coresight-priv.h > +++ b/drivers/hwtracing/coresight/coresight-priv.h > @@ -105,6 +105,15 @@ struct cs_buffers { > void **data_pages; > }; > > +/** > + * struct cs_sink_data - data used by coresight_enable_path/coresight_disable_path > + */ > +struct cs_sink_data { > + struct perf_output_handle *handle; > + struct coresight_device *sink; > + u32 traceid; > +}; > + > static inline void coresight_insert_barrier_packet(void *buf) > { > if (buf) > @@ -129,9 +138,10 @@ static inline void CS_UNLOCK(void __iomem *addr) > } while (0); > } > > -void coresight_disable_path(struct list_head *path); > +void coresight_disable_path(struct list_head *path, void *sink_data); > int coresight_enable_path(struct list_head *path, enum cs_mode mode, > void *sink_data); > +int coresight_read_traceid(struct list_head *path); > struct coresight_device *coresight_get_sink(struct list_head *path); > struct coresight_device *coresight_get_sink_by_id(u32 id); > struct coresight_device * > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > index 117dbb484543..3817743fc0c6 100644 > --- a/drivers/hwtracing/coresight/coresight-stm.c > +++ b/drivers/hwtracing/coresight/coresight-stm.c > @@ -280,9 +280,22 @@ static void stm_disable(struct coresight_device *csdev, > } > } > > +static int stm_trace_id(struct coresight_device *csdev) > +{ > + struct stm_drvdata *drvdata; > + > + if (csdev == NULL) > + return -EINVAL; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->traceid; > +} > + > static const struct coresight_ops_source stm_source_ops = { > .enable = stm_enable, > .disable = stm_disable, > + .trace_id = stm_trace_id, > }; > > static const struct coresight_ops stm_cs_ops = { > diff --git a/drivers/hwtracing/coresight/coresight-sysfs.c b/drivers/hwtracing/coresight/coresight-sysfs.c > index 1e67cc7758d7..a95afc890587 100644 > --- a/drivers/hwtracing/coresight/coresight-sysfs.c > +++ b/drivers/hwtracing/coresight/coresight-sysfs.c > @@ -167,6 +167,7 @@ int coresight_enable_sysfs(struct coresight_device *csdev) > int cpu, ret = 0; > struct coresight_device *sink; > struct list_head *path; > + struct cs_sink_data *sink_data; > enum coresight_dev_subtype_source subtype; > u32 hash; > > @@ -208,7 +209,14 @@ int coresight_enable_sysfs(struct coresight_device *csdev) > goto out; > } > > - ret = coresight_enable_path(path, CS_MODE_SYSFS, NULL); > + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); > + if (!sink_data) { > + ret = -ENOMEM; > + goto out; > + } > + sink_data->traceid = coresight_read_traceid(path); > + sink_data->sink = sink; > + ret = coresight_enable_path(path, CS_MODE_SYSFS, sink_data); > if (ret) > goto err_path; > > @@ -245,15 +253,17 @@ int coresight_enable_sysfs(struct coresight_device *csdev) > break; > } > > + kfree(sink_data); > out: > mutex_unlock(&coresight_mutex); > return ret; > > err_source: > - coresight_disable_path(path); > + coresight_disable_path(path, sink_data); > > err_path: > coresight_release_path(path); > + kfree(sink_data); > goto out; > } > EXPORT_SYMBOL_GPL(coresight_enable_sysfs); > @@ -262,6 +272,7 @@ void coresight_disable_sysfs(struct coresight_device *csdev) > { > int cpu, ret; > struct list_head *path = NULL; > + struct cs_sink_data *sink_data = NULL; > u32 hash; > > mutex_lock(&coresight_mutex); > @@ -273,6 +284,10 @@ void coresight_disable_sysfs(struct coresight_device *csdev) > if (!coresight_disable_source_sysfs(csdev, NULL)) > goto out; > > + sink_data = kzalloc(sizeof(*sink_data), GFP_KERNEL); > + if (!sink_data) > + goto out; > + > switch (csdev->subtype.source_subtype) { > case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: > cpu = source_ops(csdev)->cpu_id(csdev); > @@ -296,8 +311,11 @@ void coresight_disable_sysfs(struct coresight_device *csdev) > break; > } > > - coresight_disable_path(path); > + sink_data->sink = coresight_find_activated_sysfs_sink(csdev); > + sink_data->traceid = coresight_read_traceid(path); > + coresight_disable_path(path, sink_data); > coresight_release_path(path); > + kfree(sink_data); > > out: > mutex_unlock(&coresight_mutex); > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c > index d4f641cd9de6..7dc536eba3e2 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c > @@ -250,7 +250,8 @@ static int tmc_enable_etf_sink_perf(struct coresight_device *csdev, void *data) > pid_t pid; > unsigned long flags; > struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > - struct perf_output_handle *handle = data; > + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; > + struct perf_output_handle *handle = sink_data->handle; > struct cs_buffers *buf = etm_perf_sink_config(handle); > > spin_lock_irqsave(&drvdata->spinlock, flags); > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index e75428fa1592..0c24520645e2 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1253,7 +1253,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) > struct etr_buf *tmc_etr_get_buffer(struct coresight_device *csdev, > enum cs_mode mode, void *data) > { > - struct perf_output_handle *handle = data; > + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; > + struct perf_output_handle *handle = sink_data->handle; > struct etr_perf_buffer *etr_perf; > > switch (mode) { > @@ -1647,7 +1648,8 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) > pid_t pid; > unsigned long flags; > struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > - struct perf_output_handle *handle = data; > + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; > + struct perf_output_handle *handle = sink_data->handle; > struct etr_perf_buffer *etr_perf = etm_perf_sink_config(handle); > > spin_lock_irqsave(&drvdata->spinlock, flags); > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index bfca103f9f84..20f0ab73159c 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -232,9 +232,22 @@ static void tpda_disable(struct coresight_device *csdev, > dev_dbg(drvdata->dev, "TPDA inport %d disabled\n", in->dest_port); > } > > +static int tpda_trace_id(struct coresight_device *csdev) > +{ > + struct tpda_drvdata *drvdata; > + > + if (csdev == NULL) > + return -EINVAL; > + > + drvdata = dev_get_drvdata(csdev->dev.parent); > + > + return drvdata->atid; > +} > + > static const struct coresight_ops_link tpda_link_ops = { > .enable = tpda_enable, > .disable = tpda_disable, > + .trace_id = tpda_trace_id, > }; > > static const struct coresight_ops tpda_cs_ops = { > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 96a32b213669..7f4560b067a8 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -21,6 +21,7 @@ > > #include "coresight-self-hosted-trace.h" > #include "coresight-trbe.h" > +#include "coresight-priv.h" > > #define PERF_IDX2OFF(idx, buf) ((idx) % ((buf)->nr_pages << PAGE_SHIFT)) > > @@ -1012,7 +1013,8 @@ static int arm_trbe_enable(struct coresight_device *csdev, enum cs_mode mode, > { > struct trbe_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > struct trbe_cpudata *cpudata = dev_get_drvdata(&csdev->dev); > - struct perf_output_handle *handle = data; > + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; > + struct perf_output_handle *handle = sink_data->handle; > struct trbe_buf *buf = etm_perf_sink_config(handle); > > WARN_ON(cpudata->cpu != smp_processor_id()); > diff --git a/drivers/hwtracing/coresight/ultrasoc-smb.c b/drivers/hwtracing/coresight/ultrasoc-smb.c > index f9ebf20c91e6..92d8a9fb844e 100644 > --- a/drivers/hwtracing/coresight/ultrasoc-smb.c > +++ b/drivers/hwtracing/coresight/ultrasoc-smb.c > @@ -217,7 +217,8 @@ static void smb_enable_sysfs(struct coresight_device *csdev) > static int smb_enable_perf(struct coresight_device *csdev, void *data) > { > struct smb_drv_data *drvdata = dev_get_drvdata(csdev->dev.parent); > - struct perf_output_handle *handle = data; > + struct cs_sink_data *sink_data = (struct cs_sink_data *)data; > + struct perf_output_handle *handle = sink_data->handle; > struct cs_buffers *buf = etm_perf_sink_config(handle); > pid_t pid; > > diff --git a/include/linux/coresight.h b/include/linux/coresight.h > index f09ace92176e..fb1c225076a5 100644 > --- a/include/linux/coresight.h > +++ b/include/linux/coresight.h > @@ -344,6 +344,7 @@ struct coresight_ops_sink { > * Operations available for links. > * @enable: enables flow between iport and oport. > * @disable: disables flow between iport and oport. > + * @trace_id: Collect the traceid. > */ > struct coresight_ops_link { > int (*enable)(struct coresight_device *csdev, > @@ -352,6 +353,7 @@ struct coresight_ops_link { > void (*disable)(struct coresight_device *csdev, > struct coresight_connection *in, > struct coresight_connection *out); > + int (*trace_id)(struct coresight_device *csdev); > }; > > /** > @@ -361,6 +363,7 @@ struct coresight_ops_link { > * is associated to. > * @enable: enables tracing for a source. > * @disable: disables tracing for a source. > + * @trace_id: collect the traceid. > */ > struct coresight_ops_source { > int (*cpu_id)(struct coresight_device *csdev); > @@ -368,6 +371,7 @@ struct coresight_ops_source { > enum cs_mode mode); > void (*disable)(struct coresight_device *csdev, > struct perf_event *event); > + int (*trace_id)(struct coresight_device *csdev); > }; > > /** > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

11 months, 2 weeks

[PATCH v3 0/3] coresight: Add preferred trace id support

by Mao Jinlong

Some HW has static trace id which cannot be changed via software programming. For this case, configure the trace id in device tree with "arm,trace-id = <xxx>", and call coresight_trace_id_get_system_id with the trace id value in device probe function. The id will be reserved for the HW all the time if the device is probed. Changes since V2: 1. Change "trace-id" to "arm,trace-id". 2. Add trace id flag for getting preferred id or ODD id. Changes since V1: 1. Add argument to coresight_trace_id_get_system_id for preferred id instead of adding new function coresight_trace_id_reserve_system_id. 2. Add constraint to trace-id in dt-binding file. Mao Jinlong (3): dt-bindings: arm: Add arm,trace-id for coresight dummy source coresight: Add support to get preferred id for system trace sources coresight: dummy: Add reserve atid support for dummy source .../sysfs-bus-coresight-devices-dummy-source | 15 +++++ .../arm/arm,coresight-dummy-source.yaml | 6 ++ drivers/hwtracing/coresight/coresight-dummy.c | 59 +++++++++++++++++-- .../hwtracing/coresight/coresight-platform.c | 25 ++++++++ drivers/hwtracing/coresight/coresight-stm.c | 2 +- drivers/hwtracing/coresight/coresight-tpda.c | 2 +- .../hwtracing/coresight/coresight-trace-id.c | 35 +++++++---- .../hwtracing/coresight/coresight-trace-id.h | 11 +++- include/linux/coresight.h | 1 + 9 files changed, 137 insertions(+), 19 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source -- 2.41.0

11 months, 2 weeks

Re: [PATCH] perf scripts python arm-cs-trace-disasm.py: Skip disasm if address continuity is broken

by James Clark

On 19/07/2024 10:26 am, Ganapatrao Kulkarni wrote: > To generate the instruction tracing, script uses 2 contiguous packets > address range. If there a continuity brake due to discontiguous branch > address, it is required to reset the tracing and start tracing with the > new set of contiguous packets. > > Adding change to identify the break and complete the remaining tracing > of current packets and restart tracing from new set of packets, if > continuity is established. > Hi Ganapatrao, Can you add a before and after example of what's changed to the commit message? It wasn't immediately obvious to me if this is adding missing output, or it was correcting the tail end of the output that was previously wrong. > Signed-off-by: Ganapatrao Kulkarni <gankulkarni(a)os.amperecomputing.com> > --- > tools/perf/scripts/python/arm-cs-trace-disasm.py | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/tools/perf/scripts/python/arm-cs-trace-disasm.py b/tools/perf/scripts/python/arm-cs-trace-disasm.py > index d973c2baed1c..ad10cee2c35e 100755 > --- a/tools/perf/scripts/python/arm-cs-trace-disasm.py > +++ b/tools/perf/scripts/python/arm-cs-trace-disasm.py > @@ -198,6 +198,10 @@ def process_event(param_dict): > cpu_data[str(cpu) + 'addr'] = addr > return > > + if (cpu_data.get(str(cpu) + 'ip') == None): > + cpu_data[str(cpu) + 'ip'] = ip > + Do you need to write into the global cpu_data here? Doesn't it get overwritten after you load it back into 'prev_ip' prev_ip = cpu_data[str(cpu) + 'ip'] ... then ... # Record for previous sample packet cpu_data[str(cpu) + 'addr'] = addr cpu_data[str(cpu) + 'ip'] = stop_addr Would a local variable not accomplish the same thing? > + prev_ip = cpu_data[str(cpu) + 'ip'] > > if (options.verbose == True): > print("Event type: %s" % name) > @@ -243,12 +247,18 @@ def process_event(param_dict): > > # Record for previous sample packet > cpu_data[str(cpu) + 'addr'] = addr > + cpu_data[str(cpu) + 'ip'] = stop_addr > > # Handle CS_ETM_TRACE_ON packet if start_addr=0 and stop_addr=4 > if (start_addr == 0 and stop_addr == 4): > print("CPU%d: CS_ETM_TRACE_ON packet is inserted" % cpu) > return > > + if (stop_addr < start_addr): > + # Continuity of the Packets broken, set start_addr to previous > + # packet ip to complete the remaining tracing of the address range. > + start_addr = prev_ip > + > if (start_addr < int(dso_start) or start_addr > int(dso_end)): > print("Start address 0x%x is out of range [ 0x%x .. 0x%x ] for dso %s" % (start_addr, int(dso_start), int(dso_end), dso)) > return

11 months, 2 weeks

[PATCH v5 00/17] coresight: Use per-sink trace ID maps for Perf sessions

by James Clark

This will allow sessions with more than CORESIGHT_TRACE_IDS_MAX ETMs as long as there are fewer than that many ETMs connected to each sink. Each sink owns its own trace ID map, and any Perf session connecting to that sink will allocate from it, even if the sink is currently in use by other users. This is similar to the existing behavior where the dynamic trace IDs are constant as long as there is any concurrent Perf session active. It's not completely optimal because slightly more IDs will be used than necessary, but the optimal solution involves tracking the PIDs of each session and allocating ID maps based on the session owner. This is difficult to do with the combination of per-thread and per-cpu modes and some scheduling issues. The complexity of this isn't likely to worth it because even with multiple users they'd just see a difference in the ordering of ID allocations rather than hitting any limits (unless the hardware does have too many ETMs connected to one sink). Per-thread mode works but only until there are any overlapping IDs, at which point Perf will error out. Both per-thread mode and sysfs mode are left to future changes, but both can be added on top of this initial implementation and only sysfs mode requires further driver changes. The HW_ID version field hasn't been bumped in order to not break Perf which already has an error condition for other values of that field. Instead a new minor version has been added which signifies that there are new fields but the old fields are backwards compatible. Changes since v4: * Fix compilation failure when TRACE_ID_DEBUG is set * Expand comment about not freeing individual trace IDs in free_event_data() Changes since v3: * Fix issue where trace IDs were overwritten by possibly invalid ones by Perf in unformatted mode. Now the HW_IDs are also used for unformatted mode unless the kernel didn't emit any. * Add a commit to check the OpenCSD version. * Add a commit to not save invalid IDs in the Perf header. * Replace cs_etm_queue's formatted and formatted_set members with a single enum which is easier to use. * Drop CORESIGHT_TRACE_ID_UNUSED_FLAG as it's no longer needed. * Add a commit to print the queue number in the raw dump. * Don't assert on the number of unformatted decoders if decoders == 0. Changes since v2: * Rebase on coresight-next 6.10-rc2 (b9b25c8496). * Fix double free of csdev if device registration fails. * Fix leak of coresight_trace_id_perf_start() if trace ID allocation fails. * Don't resend HW_ID for sink changes in per-thread mode. The existing CPU field on AUX records can be used to track this instead. * Tidy function doc for coresight_trace_id_release_all() * Drop first two commits now that they are in coresight-next * Add a commit to make the trace ID spinlock local to the map Changes since V1: * Rename coresight_device.perf_id_map to perf_sink_id_map. * Instead of outputting a HW_ID for each reachable ETM, output the sink ID and continue to output only the HW_ID once for each mapping. * Keep the first two Perf patches so that it applies cleanly on coresight-next, although they have been applied on perf-tools-next * Add new *_map() functions to the trace ID public API instead of modifying existing ones. * Collapse "coresight: Pass trace ID map into source enable" into "coresight: Use per-sink trace ID maps for Perf sessions" because the first commit relied on the default map being accessible which is no longer necessary due to the previous bullet point. James Clark (17): perf: cs-etm: Create decoders after both AUX and HW_ID search passes perf: cs-etm: Allocate queues for all CPUs perf: cs-etm: Move traceid_list to each queue perf: cs-etm: Create decoders based on the trace ID mappings perf: cs-etm: Only save valid trace IDs into files perf: cs-etm: Support version 0.1 of HW_ID packets perf: cs-etm: Print queue number in raw trace dump perf: cs-etm: Add runtime version check for OpenCSD coresight: Remove unused ETM Perf stubs coresight: Clarify comments around the PID of the sink owner coresight: Move struct coresight_trace_id_map to common header coresight: Expose map arguments in trace ID API coresight: Make CPU id map a property of a trace ID map coresight: Use per-sink trace ID maps for Perf sessions coresight: Remove pending trace ID release mechanism coresight: Emit sink ID in the HW_ID packets coresight: Make trace ID map spinlock local to the map drivers/hwtracing/coresight/coresight-core.c | 37 +- drivers/hwtracing/coresight/coresight-dummy.c | 3 +- .../hwtracing/coresight/coresight-etm-perf.c | 43 +- .../hwtracing/coresight/coresight-etm-perf.h | 18 - .../coresight/coresight-etm3x-core.c | 9 +- .../coresight/coresight-etm4x-core.c | 9 +- drivers/hwtracing/coresight/coresight-priv.h | 1 + drivers/hwtracing/coresight/coresight-stm.c | 3 +- drivers/hwtracing/coresight/coresight-sysfs.c | 3 +- .../hwtracing/coresight/coresight-tmc-etr.c | 5 +- drivers/hwtracing/coresight/coresight-tmc.h | 5 +- drivers/hwtracing/coresight/coresight-tpdm.c | 3 +- .../hwtracing/coresight/coresight-trace-id.c | 138 ++-- .../hwtracing/coresight/coresight-trace-id.h | 70 +- include/linux/coresight-pmu.h | 17 +- include/linux/coresight.h | 21 +- tools/build/feature/test-libopencsd.c | 4 +- tools/include/linux/coresight-pmu.h | 17 +- tools/perf/Makefile.config | 2 +- tools/perf/arch/arm/util/cs-etm.c | 11 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.c | 49 +- .../perf/util/cs-etm-decoder/cs-etm-decoder.h | 3 +- .../util/cs-etm-decoder/cs-etm-min-version.h | 13 + tools/perf/util/cs-etm.c | 625 +++++++++++------- tools/perf/util/cs-etm.h | 12 +- 25 files changed, 645 insertions(+), 476 deletions(-) create mode 100644 tools/perf/util/cs-etm-decoder/cs-etm-min-version.h -- 2.34.1

11 months, 2 weeks

Re: [PATCH] kselftest/arm64: Add coresight test

by James Clark

+cc linux-kselftest(a)vger.kernel.org On 19/07/2024 11:21 am, Jeremy Szu wrote: > > > James Clark 於 7/17/24 10:48 PM 寫道: >> >> >> On 16/07/2024 3:06 am, Jeremy Szu wrote: >>> Hi James, >>> >>> Thank you for your reply. >>> >>> James Clark 於 7/12/24 5:01 PM 寫道: >>>> >>>> >>>> On 11/07/2024 7:03 pm, Catalin Marinas wrote: >>>>> On Wed, Jul 10, 2024 at 02:27:32PM +0800, Jeremy Szu wrote: >>>>>> Add a script to test the coresight functionalities by performing the >>>>>> perf test 'coresight'. >>>>>> >>>>>> The script checks the prerequisites and launches a bundle of >>>>>> Coresight-related tests with a 180-second timeout. >>>>>> >>>> >>>> Hi Jeremy, >>>> >>>> On the whole I'm not sure running the Perf tests under kself tests >>>> is a good fit. We're already running all the Perf tests in various >>>> CIs, so this is going to duplicate effort. Especially with setup and >>>> parsing of the results output. >>>> >>>> There is also no clean line between what's a kernel issue and whats >>>> a Perf issue when these fail. >>>> >>>> And thirdly why only run the Coresight tests? Most of the Perf tests >>>> test some part of the kernel, so if we were going to do this I think >>>> it would make sense to make some kind of proper harness and run them >>>> all. I have some recollection that someone said it might be >>>> something we could do, but I can't remember the discussion. >>> >>> The idea I'm trying to pursue is to use arm64 kselftest to run as >>> many test cases as possible for ARM SoCs across different designs and >>> distros. I believe it could provide an alert if there is an issue, >>> whether it originates from userspace or kernel, similar to how perf >>> is used in other categories. >>> >>> I'm not sure if all perf tests could be counted in soc >>> (selftests/arm64) category such as some tests may target to storage, >>> memory or devices. I >> >> Could we not put the Perf tests in .../selftests/perf.sh, then it >> doesn't really matter which subsystem they're targeting and we can run >> all the Perf tests? >> > > The .../sefltests/ seems for the kselftest framework only, not sure if > having a new .../selftests/perf will make more sense? > Yeah that sounds better, but it probably requires changing the title of the patch to "[RFC] kselftest: Run Perf tests under kselftest" or something like that. >>> could replace 'arm64/coresight' with 'arm64/perf' if it makes more >>> sense. I believe it could help users verify functionality more >>> conveniently. >>> >>>> >>>> Ignoring the main issue above I've left some comments about this >>>> patch inline below: >>>> >>>>>> Signed-off-by: Jeremy Szu <jszu(a)nvidia.com> >>>>> >>>>> I have not idea how to test coresight, so adding Suzuki as well. >>>>> >>>>>> --- >>>>>> tools/testing/selftests/arm64/Makefile | 2 +- >>>>>> .../selftests/arm64/coresight/Makefile | 5 +++ >>>>>> .../selftests/arm64/coresight/coresight.sh | 40 >>>>>> +++++++++++++++++++ >>>>>> .../selftests/arm64/coresight/settings | 1 + >>>>>> 4 files changed, 47 insertions(+), 1 deletion(-) >>>>>> create mode 100644 tools/testing/selftests/arm64/coresight/Makefile >>>>>> create mode 100755 >>>>>> tools/testing/selftests/arm64/coresight/coresight.sh >>>>>> create mode 100644 tools/testing/selftests/arm64/coresight/settings >>>>>> >>>>>> diff --git a/tools/testing/selftests/arm64/Makefile >>>>>> b/tools/testing/selftests/arm64/Makefile >>>>>> index 28b93cab8c0dd..2b788d7bab22d 100644 >>>>>> --- a/tools/testing/selftests/arm64/Makefile >>>>>> +++ b/tools/testing/selftests/arm64/Makefile >>>>>> @@ -4,7 +4,7 @@ >>>>>> ARCH ?= $(shell uname -m 2>/dev/null || echo not) >>>>>> ifneq (,$(filter $(ARCH),aarch64 arm64)) >>>>>> -ARM64_SUBTARGETS ?= tags signal pauth fp mte bti abi >>>>>> +ARM64_SUBTARGETS ?= tags signal pauth fp mte bti abi coresight >>>>>> else >>>>>> ARM64_SUBTARGETS := >>>>>> endif >>>>>> diff --git a/tools/testing/selftests/arm64/coresight/Makefile >>>>>> b/tools/testing/selftests/arm64/coresight/Makefile >>>>>> new file mode 100644 >>>>>> index 0000000000000..1cc8c1f2a997e >>>>>> --- /dev/null >>>>>> +++ b/tools/testing/selftests/arm64/coresight/Makefile >>>>>> @@ -0,0 +1,5 @@ >>>>>> +# SPDX-License-Identifier: GPL-2.0 >>>>>> + >>>>>> +TEST_PROGS := coresight.sh >>>>>> + >>>>>> +include ../../lib.mk >>>>>> diff --git a/tools/testing/selftests/arm64/coresight/coresight.sh >>>>>> b/tools/testing/selftests/arm64/coresight/coresight.sh >>>>>> new file mode 100755 >>>>>> index 0000000000000..e550957cf593b >>>>>> --- /dev/null >>>>>> +++ b/tools/testing/selftests/arm64/coresight/coresight.sh >>>>>> @@ -0,0 +1,40 @@ >>>>>> +#!/bin/bash >>>>>> +# SPDX-License-Identifier: GPL-2.0 >>>>>> + >>>>>> +skip() { >>>>>> + echo "SKIP: $1" >>>>>> + exit 4 >>>>>> +} >>>>>> + >>>>>> +fail() { >>>>>> + echo "FAIL: $1" >>>>>> + exit 255 >>>>>> +} >>>>>> + >>>>>> +is_coresight_supported() { >>>>>> + if [ -d "/sys/bus/coresight/devices" ]; then >>>>>> + return 0 >>>>>> + fi >>>>>> + return 255 >>>>>> +} >>>> >>>> The Perf coresight tests already have a skip mechanism built in so >>>> can we rely on that instead of duplicating it here? There are also >>>> other scenarios for skipping like Perf not linked with OpenCSD which >>>> aren't covered here. >>>> >>> >>> Will it return the different error code to indicate if it's failed to >>> be executed or the coresight is not supported? >>> >> >> I think the exit code is only used for more serious errors. For things >> like missing tests, SKIP and FAIL it still exits with 0 but you have >> to grep for the strings. Actually for a missing test it prints nothing >> and exits 0. >> >>>>> + >>>>>> +if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then >>>>>> + [ "$(id -u)" -ne 0 ] && \ >>>>>> + skip "this test must be run as root." >>>>>> + which perf >/dev/null 2>&1 || \ >>>>>> + skip "perf is not installed." >>>>>> + perf test list 2>&1 | grep -qi 'coresight' || \ >>>>>> + skip "perf doesn't support testing coresight." >>>> >>>> Can this be an error instead? The coresight tests were added in 5.10 >>>> and I don't think new kselftest needs to support such old kernels. >>>> This skip risks turning an error with installing the tests into a >>>> silent failure. >>>> >>>> Also as far as I know a lot of distros will refuse to open Perf >>>> unless it matches the kernel version if it was installed from the >>>> package manager, so we don't need to worry about old versions. >>>> >>> >>> The idea to skip it here is because I thought either a distro >>> (custom) kernel doesn't enable the kconfig or the distro built the >>> perf with CORESIGHT=0. >>> >>> I could make it as an error and put it after "is_coresight_support" >>> if it makes more sense. >>> >> >> But the Coresight test already checks these things, which is my point. >> You can grep for "SKIP" which it will print for any case where the >> coresight test can't be run due to some missing config. >> > > Oh, I guess you mean to rely on something like the `perf list cs_etm | > grep -q cs_etm || exit 2`. Yes, that makes more sense. > If we're leaning towards running all the Perf tests then none of this is required anymore. This is another example of why it's better to run them all. We can't realistically hard code a kself test with loads of logic for each Perf subtest when Perf will happily run all the tests on it's own without any extra work. >>>>>> + is_coresight_supported || \ >>>>>> + skip "coresight is not supported." >>>>>> + >>>>>> + cmd_output=$(perf test -vv 'coresight' 2>&1) >>>>>> + perf_ret=$? >>>>>> + >>>>>> + if [ $perf_ret -ne 0 ]; then >>>>>> + fail "perf command returns non-zero." >>>>>> + elif [[ $cmd_output == *"FAILED!"* ]]; then >>>>>> + echo $cmd_output >>>> >>>> It's probably helpful to print cmd_output in both failure cases. >>>> >>> >>> ok, will do. >>> >>>>>> + fail "perf test 'arm coresight' test failed!" > > I think I should remove the `is_coresight_supported` there and checks > the output as a "else" to see if the test is PASS or SKIP. Does it make > sense to you? > Same as above applies, the only thing that's really required is parsing for "FAILED". >>>>>> + fi >>>>>> +fi >>>>>> diff --git a/tools/testing/selftests/arm64/coresight/settings >>>>>> b/tools/testing/selftests/arm64/coresight/settings >>>>>> new file mode 100644 >>>>>> index 0000000000000..a953c96aa16e1 >>>>>> --- /dev/null >>>>>> +++ b/tools/testing/selftests/arm64/coresight/settings >>>>>> @@ -0,0 +1 @@ >>>>>> +timeout=180 >>>> >>>> I timed 331 seconds on n1sdp, and probably even longer on Juno. >>>> >>>> It doesn't need to run for this long and it's an issue with the >>>> tests, but currently that's how long it takes so the timeout needs >>>> to be longer. >>>> >>> >>> ok, will extend it to 600. >>> >>>>>> -- >>>>>> 2.34.1 >>>>>

11 months, 2 weeks

Re: [PATCH] kselftest/arm64: Add coresight test

by James Clark

On 16/07/2024 3:06 am, Jeremy Szu wrote: > Hi James, > > Thank you for your reply. > > James Clark 於 7/12/24 5:01 PM 寫道: >> >> >> On 11/07/2024 7:03 pm, Catalin Marinas wrote: >>> On Wed, Jul 10, 2024 at 02:27:32PM +0800, Jeremy Szu wrote: >>>> Add a script to test the coresight functionalities by performing the >>>> perf test 'coresight'. >>>> >>>> The script checks the prerequisites and launches a bundle of >>>> Coresight-related tests with a 180-second timeout. >>>> >> >> Hi Jeremy, >> >> On the whole I'm not sure running the Perf tests under kself tests is >> a good fit. We're already running all the Perf tests in various CIs, >> so this is going to duplicate effort. Especially with setup and >> parsing of the results output. >> >> There is also no clean line between what's a kernel issue and whats a >> Perf issue when these fail. >> >> And thirdly why only run the Coresight tests? Most of the Perf tests >> test some part of the kernel, so if we were going to do this I think >> it would make sense to make some kind of proper harness and run them >> all. I have some recollection that someone said it might be something >> we could do, but I can't remember the discussion. > > The idea I'm trying to pursue is to use arm64 kselftest to run as many > test cases as possible for ARM SoCs across different designs and > distros. I believe it could provide an alert if there is an issue, > whether it originates from userspace or kernel, similar to how perf is > used in other categories. > > I'm not sure if all perf tests could be counted in soc (selftests/arm64) > category such as some tests may target to storage, memory or devices. I Could we not put the Perf tests in .../selftests/perf.sh, then it doesn't really matter which subsystem they're targeting and we can run all the Perf tests? > could replace 'arm64/coresight' with 'arm64/perf' if it makes more > sense. I believe it could help users verify functionality more > conveniently. > >> >> Ignoring the main issue above I've left some comments about this patch >> inline below: >> >>>> Signed-off-by: Jeremy Szu <jszu(a)nvidia.com> >>> >>> I have not idea how to test coresight, so adding Suzuki as well. >>> >>>> --- >>>> tools/testing/selftests/arm64/Makefile | 2 +- >>>> .../selftests/arm64/coresight/Makefile | 5 +++ >>>> .../selftests/arm64/coresight/coresight.sh | 40 >>>> +++++++++++++++++++ >>>> .../selftests/arm64/coresight/settings | 1 + >>>> 4 files changed, 47 insertions(+), 1 deletion(-) >>>> create mode 100644 tools/testing/selftests/arm64/coresight/Makefile >>>> create mode 100755 >>>> tools/testing/selftests/arm64/coresight/coresight.sh >>>> create mode 100644 tools/testing/selftests/arm64/coresight/settings >>>> >>>> diff --git a/tools/testing/selftests/arm64/Makefile >>>> b/tools/testing/selftests/arm64/Makefile >>>> index 28b93cab8c0dd..2b788d7bab22d 100644 >>>> --- a/tools/testing/selftests/arm64/Makefile >>>> +++ b/tools/testing/selftests/arm64/Makefile >>>> @@ -4,7 +4,7 @@ >>>> ARCH ?= $(shell uname -m 2>/dev/null || echo not) >>>> ifneq (,$(filter $(ARCH),aarch64 arm64)) >>>> -ARM64_SUBTARGETS ?= tags signal pauth fp mte bti abi >>>> +ARM64_SUBTARGETS ?= tags signal pauth fp mte bti abi coresight >>>> else >>>> ARM64_SUBTARGETS := >>>> endif >>>> diff --git a/tools/testing/selftests/arm64/coresight/Makefile >>>> b/tools/testing/selftests/arm64/coresight/Makefile >>>> new file mode 100644 >>>> index 0000000000000..1cc8c1f2a997e >>>> --- /dev/null >>>> +++ b/tools/testing/selftests/arm64/coresight/Makefile >>>> @@ -0,0 +1,5 @@ >>>> +# SPDX-License-Identifier: GPL-2.0 >>>> + >>>> +TEST_PROGS := coresight.sh >>>> + >>>> +include ../../lib.mk >>>> diff --git a/tools/testing/selftests/arm64/coresight/coresight.sh >>>> b/tools/testing/selftests/arm64/coresight/coresight.sh >>>> new file mode 100755 >>>> index 0000000000000..e550957cf593b >>>> --- /dev/null >>>> +++ b/tools/testing/selftests/arm64/coresight/coresight.sh >>>> @@ -0,0 +1,40 @@ >>>> +#!/bin/bash >>>> +# SPDX-License-Identifier: GPL-2.0 >>>> + >>>> +skip() { >>>> + echo "SKIP: $1" >>>> + exit 4 >>>> +} >>>> + >>>> +fail() { >>>> + echo "FAIL: $1" >>>> + exit 255 >>>> +} >>>> + >>>> +is_coresight_supported() { >>>> + if [ -d "/sys/bus/coresight/devices" ]; then >>>> + return 0 >>>> + fi >>>> + return 255 >>>> +} >> >> The Perf coresight tests already have a skip mechanism built in so can >> we rely on that instead of duplicating it here? There are also other >> scenarios for skipping like Perf not linked with OpenCSD which aren't >> covered here. >> > > Will it return the different error code to indicate if it's failed to be > executed or the coresight is not supported? > I think the exit code is only used for more serious errors. For things like missing tests, SKIP and FAIL it still exits with 0 but you have to grep for the strings. Actually for a missing test it prints nothing and exits 0. >>>> + >>>> +if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then >>>> + [ "$(id -u)" -ne 0 ] && \ >>>> + skip "this test must be run as root." >>>> + which perf >/dev/null 2>&1 || \ >>>> + skip "perf is not installed." >>>> + perf test list 2>&1 | grep -qi 'coresight' || \ >>>> + skip "perf doesn't support testing coresight." >> >> Can this be an error instead? The coresight tests were added in 5.10 >> and I don't think new kselftest needs to support such old kernels. >> This skip risks turning an error with installing the tests into a >> silent failure. >> >> Also as far as I know a lot of distros will refuse to open Perf unless >> it matches the kernel version if it was installed from the package >> manager, so we don't need to worry about old versions. >> > > The idea to skip it here is because I thought either a distro (custom) > kernel doesn't enable the kconfig or the distro built the perf with > CORESIGHT=0. > > I could make it as an error and put it after "is_coresight_support" if > it makes more sense. > But the Coresight test already checks these things, which is my point. You can grep for "SKIP" which it will print for any case where the coresight test can't be run due to some missing config. >>>> + is_coresight_supported || \ >>>> + skip "coresight is not supported." >>>> + >>>> + cmd_output=$(perf test -vv 'coresight' 2>&1) >>>> + perf_ret=$? >>>> + >>>> + if [ $perf_ret -ne 0 ]; then >>>> + fail "perf command returns non-zero." >>>> + elif [[ $cmd_output == *"FAILED!"* ]]; then >>>> + echo $cmd_output >> >> It's probably helpful to print cmd_output in both failure cases. >> > > ok, will do. > >>>> + fail "perf test 'arm coresight' test failed!" >>>> + fi >>>> +fi >>>> diff --git a/tools/testing/selftests/arm64/coresight/settings >>>> b/tools/testing/selftests/arm64/coresight/settings >>>> new file mode 100644 >>>> index 0000000000000..a953c96aa16e1 >>>> --- /dev/null >>>> +++ b/tools/testing/selftests/arm64/coresight/settings >>>> @@ -0,0 +1 @@ >>>> +timeout=180 >> >> I timed 331 seconds on n1sdp, and probably even longer on Juno. >> >> It doesn't need to run for this long and it's an issue with the tests, >> but currently that's how long it takes so the timeout needs to be longer. >> > > ok, will extend it to 600. > >>>> -- >>>> 2.34.1 >>>

11 months, 3 weeks

Re: [PATCH] kselftest/arm64: Add coresight test

by James Clark

On 11/07/2024 7:03 pm, Catalin Marinas wrote: > On Wed, Jul 10, 2024 at 02:27:32PM +0800, Jeremy Szu wrote: >> Add a script to test the coresight functionalities by performing the >> perf test 'coresight'. >> >> The script checks the prerequisites and launches a bundle of >> Coresight-related tests with a 180-second timeout. >> Hi Jeremy, On the whole I'm not sure running the Perf tests under kself tests is a good fit. We're already running all the Perf tests in various CIs, so this is going to duplicate effort. Especially with setup and parsing of the results output. There is also no clean line between what's a kernel issue and whats a Perf issue when these fail. And thirdly why only run the Coresight tests? Most of the Perf tests test some part of the kernel, so if we were going to do this I think it would make sense to make some kind of proper harness and run them all. I have some recollection that someone said it might be something we could do, but I can't remember the discussion. Ignoring the main issue above I've left some comments about this patch inline below: >> Signed-off-by: Jeremy Szu <jszu(a)nvidia.com> > > I have not idea how to test coresight, so adding Suzuki as well. > >> --- >> tools/testing/selftests/arm64/Makefile | 2 +- >> .../selftests/arm64/coresight/Makefile | 5 +++ >> .../selftests/arm64/coresight/coresight.sh | 40 +++++++++++++++++++ >> .../selftests/arm64/coresight/settings | 1 + >> 4 files changed, 47 insertions(+), 1 deletion(-) >> create mode 100644 tools/testing/selftests/arm64/coresight/Makefile >> create mode 100755 tools/testing/selftests/arm64/coresight/coresight.sh >> create mode 100644 tools/testing/selftests/arm64/coresight/settings >> >> diff --git a/tools/testing/selftests/arm64/Makefile b/tools/testing/selftests/arm64/Makefile >> index 28b93cab8c0dd..2b788d7bab22d 100644 >> --- a/tools/testing/selftests/arm64/Makefile >> +++ b/tools/testing/selftests/arm64/Makefile >> @@ -4,7 +4,7 @@ >> ARCH ?= $(shell uname -m 2>/dev/null || echo not) >> >> ifneq (,$(filter $(ARCH),aarch64 arm64)) >> -ARM64_SUBTARGETS ?= tags signal pauth fp mte bti abi >> +ARM64_SUBTARGETS ?= tags signal pauth fp mte bti abi coresight >> else >> ARM64_SUBTARGETS := >> endif >> diff --git a/tools/testing/selftests/arm64/coresight/Makefile b/tools/testing/selftests/arm64/coresight/Makefile >> new file mode 100644 >> index 0000000000000..1cc8c1f2a997e >> --- /dev/null >> +++ b/tools/testing/selftests/arm64/coresight/Makefile >> @@ -0,0 +1,5 @@ >> +# SPDX-License-Identifier: GPL-2.0 >> + >> +TEST_PROGS := coresight.sh >> + >> +include ../../lib.mk >> diff --git a/tools/testing/selftests/arm64/coresight/coresight.sh b/tools/testing/selftests/arm64/coresight/coresight.sh >> new file mode 100755 >> index 0000000000000..e550957cf593b >> --- /dev/null >> +++ b/tools/testing/selftests/arm64/coresight/coresight.sh >> @@ -0,0 +1,40 @@ >> +#!/bin/bash >> +# SPDX-License-Identifier: GPL-2.0 >> + >> +skip() { >> + echo "SKIP: $1" >> + exit 4 >> +} >> + >> +fail() { >> + echo "FAIL: $1" >> + exit 255 >> +} >> + >> +is_coresight_supported() { >> + if [ -d "/sys/bus/coresight/devices" ]; then >> + return 0 >> + fi >> + return 255 >> +} The Perf coresight tests already have a skip mechanism built in so can we rely on that instead of duplicating it here? There are also other scenarios for skipping like Perf not linked with OpenCSD which aren't covered here. >> + >> +if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then >> + [ "$(id -u)" -ne 0 ] && \ >> + skip "this test must be run as root." >> + which perf >/dev/null 2>&1 || \ >> + skip "perf is not installed." >> + perf test list 2>&1 | grep -qi 'coresight' || \ >> + skip "perf doesn't support testing coresight." Can this be an error instead? The coresight tests were added in 5.10 and I don't think new kselftest needs to support such old kernels. This skip risks turning an error with installing the tests into a silent failure. Also as far as I know a lot of distros will refuse to open Perf unless it matches the kernel version if it was installed from the package manager, so we don't need to worry about old versions. >> + is_coresight_supported || \ >> + skip "coresight is not supported." >> + >> + cmd_output=$(perf test -vv 'coresight' 2>&1) >> + perf_ret=$? >> + >> + if [ $perf_ret -ne 0 ]; then >> + fail "perf command returns non-zero." >> + elif [[ $cmd_output == *"FAILED!"* ]]; then >> + echo $cmd_output It's probably helpful to print cmd_output in both failure cases. >> + fail "perf test 'arm coresight' test failed!" >> + fi >> +fi >> diff --git a/tools/testing/selftests/arm64/coresight/settings b/tools/testing/selftests/arm64/coresight/settings >> new file mode 100644 >> index 0000000000000..a953c96aa16e1 >> --- /dev/null >> +++ b/tools/testing/selftests/arm64/coresight/settings >> @@ -0,0 +1 @@ >> +timeout=180 I timed 331 seconds on n1sdp, and probably even longer on Juno. It doesn't need to run for this long and it's an issue with the tests, but currently that's how long it takes so the timeout needs to be longer. >> -- >> 2.34.1 >

11 months, 3 weeks

Re: [PATCH v2 2/4] dt-bindings: arm: Add binding document for Coresight Control Unit device.

by Suzuki K Poulose

On 11/07/2024 09:36, JieGan wrote: > On Tue, Jul 09, 2024 at 02:00:25PM +0800, JieGan wrote: >> On Mon, Jul 08, 2024 at 01:50:11PM +0100, Suzuki K Poulose wrote: >>> On 08/07/2024 11:25, JieGan wrote: >>>> On Mon, Jul 08, 2024 at 06:10:28PM +0800, JieGan wrote: >>>>> On Mon, Jul 08, 2024 at 10:41:55AM +0100, Suzuki K Poulose wrote: >>>>>> On 05/07/2024 10:00, Jie Gan wrote: >>>>>>> Add binding document for Coresight Control Unit device. >>>>>> >>>>>> nit: This is again too generic ? corsight-tmc-control-unit ? After all >>>>>> thats what it is and not a *generic* coresight control unit ? >>>>>> >>>>> coresight-tmc-control-unit is much better. We will check it. >>>>>>> >>>>>>> Signed-off-by: Jie Gan <quic_jiegan(a)quicinc.com> >>>>>>> --- >>>>>>> .../bindings/arm/qcom,coresight-ccu.yaml | 87 +++++++++++++++++++ >>>>>>> 1 file changed, 87 insertions(+) >>>>>>> create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-ccu.yaml >>>>>>> >>>>>>> diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ccu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ccu.yaml >>>>>>> new file mode 100644 >>>>>>> index 000000000000..9bb8ced393a7 >>>>>>> --- /dev/null >>>>>>> +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ccu.yaml >>>>>>> @@ -0,0 +1,87 @@ >>>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>>>>>> +%YAML 1.2 >>>>>>> +--- >>>>>>> +$id: http://devicetree.org/schemas/arm/qcom,coresight-ccu.yaml# >>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>>>>> + >>>>>>> +title: CoreSight Control Unit >>>>>>> + >>>>>>> +maintainers: >>>>>>> + - Yuanfang Zhang <quic_yuanfang(a)quicinc.com> >>>>>>> + - Mao Jinlong <quic_jinlmao(a)quicinc.com> >>>>>>> + - Jie Gan <quic_jiegan(a)quicinc.com> >>>>>>> + >>>>>>> +description: >>>>>>> + The Coresight Control unit controls various Coresight behaviors. >>>>>>> + Used to enable/disable ETR’s data filter function based on trace ID. >>>>>>> + >>>>>>> +properties: >>>>>>> + compatible: >>>>>>> + const: qcom,coresight-ccu >>>>>>> + >>>>>>> + reg: >>>>>>> + maxItems: 1 >>>>>>> + >>>>>>> + clocks: >>>>>>> + maxItems: 1 >>>>>>> + >>>>>>> + clock-names: >>>>>>> + items: >>>>>>> + - const: apb_pclk >>>>>>> + >>>>>>> + reg-names: >>>>>>> + items: >>>>>>> + - const: ccu-base >>>>>>> + >>>>>>> + in-ports: >>>>>>> + $ref: /schemas/graph.yaml#/properties/ports >>>>>>> + >>>>>>> + unevaluatedProperties: >>>>>>> + patternProperties: >>>>>>> + '^port(@[0-7])?$': >>>>>>> + description: Input connections from CoreSight Trace bus >>>>>>> + $ref: /schemas/graph.yaml#/properties/port >>>>>>> + >>>>>>> + properties: >>>>>>> + qcom,ccu-atid-offset: >>>>>> >>>>>> Why do we need this atid offset ? Couldn't this be mapped to the "port" >>>>>> number ? >>>>>> >>>>>> e.g, input-port 0 on CCU => Offset x >>>>>> input-port 1 on CCU => (Offset x + Size of 1 region) >>>>> If the first ATID offset remains constant, it appears to be feasible. >>>>> We will consider the possibility of this solution. >>>> We just checked the ATID offset varies across different hardware platforms. >>>> It defined as 0xf4 on some platforms, and some others defined as 0xf8. >>> >>> What do you mean ? The offset where you apply the filter changes across >>> different platforms ? or different "tmc-control-unit" implementations ? >>> Is this discoverable from the device ? We could use different >>> compatibles for different "types" of the "devices". Simply adding >>> something in the DT is not the right way. >> >> I got your point here. I believe we should consult our hardware engineers first to check it. >> We need to figure out the design of ATID offset from hardware perspective. Then we can >> propose an alternative approach, such as associating the offset with a compitable value, >> to resolve this issue. >> >>> >>>> >>>> So I think it should be better to define it in device tree node. >>> >>> No. See above. > > > Hi Suzuki > > There is a new solution for CCU device. We would like to separate one CCU device into several helper > devices, each responsible for one feature of the CCU device. > > For the data filter feature, we will define the address of the AITD Register that included by CCU in DT > as base address of the helper node. So the driver code can easily program the register field with the base address. > With this solution, we may need define several helper nodes in DT file to support different features for CCU and each > helper device needs a driver to support its behavior. > > for example, ATID register for ETR0 with base address 0x10000f8: (tmp name used, TDFU for tmc data filter unit) That looks like a hack to me and don't prefer that and there would be multiple mappings for a single device and that could complicate device resource accounting. > > TDFU@10000f8 { > ... > } > > ATID register for ETR1 with base address 0x1000108: > TDFU@1000108 { > ... > } > > The CCU device supports various features and the data filter feature for ETR is one of those features. How to support > those features with one helper_enable function is a serious challenge. That's why we would like to separate it. > Meanwhile, This solution can also resolve the offset issue. > > We are looking forward your opinions with this proposal. We need to know what other functionalities are supported and how that will be used ? In the worst case, you could define register bases for each port in the CCU device node. TDFU@.. { reg = <base-address 4K> <I don't know the standard property name for> = List of { <port number>, <Offset from base>, } } Suzuki

11 months, 4 weeks

[PATCH v1 0/3] Add source filtering for multi-port output

by Tao Zhang

In our hardware design, by combining a funnel and a replicator, it implement a hardware device with one-to-one correspondence between output ports and input ports. The programming usage on this device is the same as funnel. The software uses a funnel and a static replicator to implement the driver of this device. Since original funnels only support a single output connection and original replicator only support a single input connection, the code needs to be modified to support this new feature. The following is a typical topology diagram of multi-port output mechanism. |----------| |---------| |----------| |---------| | TPDM 0 | | Source0 | | Source 1 | | TPDM 1 | |----------| |---------| |----------| |---------| | | | | | | | | | --------- | | | | | | | | | | | | | | | \-------------/ ---------------------- | \ Funnel 0 / | | ----------- | ------------------------------ | | | | | | \------------------/ \ Funnel 1 / ----| \--------------/ | | |----> Combine a funnel and a | | static replicator /-----------------\ | / replicator 0 \ ----| /---------------------\ | | | | | |-----------| | |---------| | | |TPDM0 |TPDM1 | \-----------------/ | \ TPDA 0 / | \-------------/ | | | | |Source0/1 | \-------------------------------/ \ Funnel 2 / \---------------------------/ Changes in V1: 1. Add a static replicator connect to a funnel to implement the correspondence between the output ports and the input ports on funnels. -- Suzuki K Poulose 2. Add filter_src_dev and filter_src_dev phandle to "coresight_connection" struct, and populate them if there is one. -- Suzuki K Poulose 3. To look at the phandle and then fixup/remove the filter_src device in fixup/remove connections. -- Suzuki K Poulose 4. When TPDA reads DSB/CMB element size, it is implemented by looking up filter src device in the connections. -- Suzuki K Poulose Tao Zhang (3): dt-bindings: arm: qcom,coresight-static-replicator: Add property for source filtering coresight: Add source filtering for multi-port output coresight-tpda: Optimize the function of reading element size .../arm/arm,coresight-static-replicator.yaml | 18 +++- drivers/hwtracing/coresight/coresight-core.c | 89 ++++++++++++++++--- .../hwtracing/coresight/coresight-platform.c | 13 +++ drivers/hwtracing/coresight/coresight-tpda.c | 6 +- include/linux/coresight.h | 5 ++ 5 files changed, 115 insertions(+), 16 deletions(-) -- 2.17.1

11 months, 4 weeks

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