CoreSight

coresight@lists.linaro.org

9 participants
2400 discussions

by Ajith Kurian Issac

Hi, We are trying to us the Open CSD for decoding a onchip trace in our ETB. The trace was enabled and is captured in the ETB. We read the trace back and dumped it into a text file. I am attaching it. How can I use the CSD tool to decode it? Thanks Ajith

6 years, 8 months

[RFC v3 0/2] perf: Support for Arm A32/T32 instruction sets

by Robert Walker

Hi, I'm taking this back to the linaro coresight list so we can get the OpenCSD library versioning sorted out. The first patch splits the OpenCSD feature check into two parts. The original check is left as is - this just checks for the presence of an OpenCSD library. A new check (libopencsd-numinstr) is added that checks for the new OpenCSD (>0.9.0) that has the num_instr_range member in the ocsd_generic_trace_elem struct. This feature is then used to set a flag used in cs-etm-decoder.c to select which versions of 2 functions are used to get the instruction count / last instruction size of each instruction block - if the flag is not set, then the previous assumptions of a 4 byte instruction size are used. It was suggested that OpenCSD should export a version header - I agree this is a good idea, but this will require a new release of the library, so we would miss support for the instruction sizes when OpenCSD 0.9.{0,1,2} is installed - hence why I've kept the version check using the presence of num_instr_range. The second patch adds support for finding the T32 instruction counts when the OpenCSD library doesn't report the instruction counts. As this involves iterating through the block of instructions and examining each instruction, there is a significant peformance hit (about 5x slower than using the OpenCSD library to report the instruction counts), so I'm not sure this patch should go into upstream. Regards Rob Robert Walker (2): perf: Support for Arm A32/T32 instruction sets in CoreSight trace perf: Full support for Arm T32 instructions with older version of OpenCSD tools/build/Makefile.feature | 3 +- tools/build/feature/Makefile | 4 + tools/build/feature/test-libopencsd-numinstr.c | 15 ++++ tools/perf/Makefile.config | 3 + tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 106 ++++++++++++++++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 10 +++ tools/perf/util/cs-etm.c | 71 +++++++--------- 7 files changed, 171 insertions(+), 41 deletions(-) create mode 100644 tools/build/feature/test-libopencsd-numinstr.c -- 2.7.4

6 years, 8 months

[PATCH] coresight: tmc: Fix bad register address for CLAIM

by Leo Yan

Commit 4d3ebd3658d8 ("coreisght: tmc: Claim device before use") uses CLAIM tag to validate if the device is available, it needs to pass the device base address to access related registers. In the function tmc_etb_disable_hw() it wrongly passes the driver data pointer as register base address, thus it's easily to produce the kernel warning info like below: [ 83.579898] WARNING: CPU: 4 PID: 2970 at drivers/hwtracing/coresight/coresight.c:207 coresight_disclaim_device_unlocked+0x44/0x80 [ 83.591448] Modules linked in: [ 83.594485] CPU: 4 PID: 2970 Comm: uname Not tainted 4.19.0-rc6-00417-g721b509 #110 [ 83.602067] Hardware name: ARM Juno development board (r2) (DT) [ 83.607932] pstate: 80000085 (Nzcv daIf -PAN -UAO) [ 83.612681] pc : coresight_disclaim_device_unlocked+0x44/0x80 [ 83.618375] lr : coresight_disclaim_device_unlocked+0x44/0x80 [ 83.624064] sp : ffff00000fe3ba20 [ 83.627347] x29: ffff00000fe3ba20 x28: ffff80002d430dc0 [ 83.632618] x27: ffff800033177c00 x26: ffff80002eb44480 [ 83.637889] x25: 0000000000000001 x24: ffff800033c72600 [ 83.643160] x23: ffff0000099b11f8 x22: ffff0000099b11c8 [ 83.648430] x21: 0000000000000002 x20: ffff800033a90418 [ 83.653701] x19: ffff0000099b11c8 x18: 0000000000000000 [ 83.658971] x17: 0000000000000000 x16: 0000000000000000 [ 83.664241] x15: 0000000000000000 x14: 0000000000000000 [ 83.669511] x13: 0000000000000000 x12: 0000000000000000 [ 83.674782] x11: 0000000000000000 x10: 0000000000000000 [ 83.680052] x9 : 0000000000000000 x8 : 0000000000000001 [ 83.685322] x7 : 0000000000010000 x6 : ffff800033ebab18 [ 83.690593] x5 : ffff800033ebab18 x4 : ffff800033e6c698 [ 83.695862] x3 : 0000000000000001 x2 : 0000000000000000 [ 83.701133] x1 : 0000000000000000 x0 : 0000000000000001 [ 83.706404] Call trace: [ 83.708830] coresight_disclaim_device_unlocked+0x44/0x80 [ 83.714180] coresight_disclaim_device+0x34/0x48 [ 83.718756] tmc_disable_etf_sink+0xc4/0xf0 [ 83.722902] coresight_disable_path_from+0xc8/0x240 [ 83.727735] coresight_disable_path+0x24/0x30 [ 83.732053] etm_event_stop+0x130/0x170 [ 83.735854] etm_event_del+0x24/0x30 [ 83.739399] event_sched_out.isra.51+0xcc/0x1e8 [ 83.743887] group_sched_out.part.53+0x44/0xb0 [ 83.748291] ctx_sched_out+0x298/0x2b8 [ 83.752005] task_ctx_sched_out+0x74/0xa8 [ 83.755980] perf_event_exit_task+0x140/0x418 [ 83.760298] do_exit+0x3f4/0xcf0 [ 83.763497] do_group_exit+0x5c/0xc0 [ 83.767041] __arm64_sys_exit_group+0x24/0x28 [ 83.771359] el0_svc_common+0x110/0x178 [ 83.775160] el0_svc_handler+0x94/0xe8 [ 83.778875] el0_svc+0x8/0xc [ 83.781728] ---[ end trace 02d8d8eac46db9e5 ]--- This patch is to fix this bug by using 'drvdata->base' as the register base address for CLAIM related operation. Fixes: 4d3ebd3658d8 ("coreisght: tmc: Claim device before use") Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Robert Walker <robert.walker(a)arm.com> Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- drivers/hwtracing/coresight/coresight-tmc-etf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 53fc83b..5864ac5 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -86,7 +86,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvdata) static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) { - coresight_disclaim_device(drvdata); + coresight_disclaim_device(drvdata->base); __tmc_etb_disable_hw(drvdata); } -- 2.7.4

6 years, 9 months

[PATCH v2 0/4] opencsd: Update to instruction information supplied.

by Mike Leach

This patchset adds more information about the final instuction in the Instruction Range generic packet. i) A flag is set if the last instruction is conditional [last_instr_cond]. ii) for A32/T32 ISA, the instruction subtype will be set to 'Implied Return' [OCSD_S_INSTR_V7_IMPLIED_RET] if it is one of the instructions: mov pc,lr bx r14 pop {...,pc} ldr pc,[sp], #offset These are used by the CPU return predictor and in general by compilers when a return is required. The patchset also removes the uint32_t casts in the version #define OCSD_VER_NUM to enable correct use with pre-processor. updates for v2: i) Instruction matching for implied return tightened to focus correctly on specific instructions ii) Typos in help / printed text corrected. Mike Leach (4): opencsd: Generic output packet - add additional instruction info opencsd: Typo Fixes. opencsd: docs: Update documents for new generic packet field opencsd: Update README etc for version 0.10.0 README.md | 6 ++- decoder/docs/doxygen_config.dox | 2 +- decoder/docs/prog_guide/prog_guide_generic_pkts.md | 3 +- decoder/include/common/trc_gen_elem.h | 1 + .../include/opencsd/etmv4/trc_pkt_decode_etmv4i.h | 2 + decoder/include/opencsd/ocsd_if_types.h | 1 + decoder/include/opencsd/ocsd_if_version.h | 8 ++-- decoder/include/opencsd/trc_gen_elem_types.h | 1 + decoder/source/etmv3/trc_pkt_decode_etmv3.cpp | 1 + decoder/source/etmv4/trc_pkt_decode_etmv4i.cpp | 29 ++++++-------- decoder/source/i_dec/trc_i_decode.cpp | 1 + decoder/source/i_dec/trc_idec_arminst.cpp | 46 +++++++++++----------- decoder/source/ocsd_dcd_tree.cpp | 1 - decoder/source/ptm/trc_pkt_decode_ptm.cpp | 2 + decoder/source/trc_gen_elem.cpp | 7 +++- decoder/tests/source/trc_pkt_lister.cpp | 2 +- 16 files changed, 61 insertions(+), 52 deletions(-) -- 2.14.2

6 years, 9 months

Coresight support on Cavium ThunderX2

by Mike Bazov

Greetings, I'm trying to find an ARM server dedicated for high-computing and parallelism, that also supports Coresight. The Cavium ThunderX2 fits perfectly for the performance requirements, but i'm not quite sure Coresight is supported. This isn't documented anywhere, so i thought it's best to ask this here. Is Coresight supported on ThunderX2? Thank you, Mike.

6 years, 9 months

[RFC PATCH] perf cs-etm: Set sample flags for A64 trace data

by Leo Yan

The perf sample data contains flags to indicate the hardware trace data is belonging to which type branch instruction, thus this can be used to print out the human readable string. Arm CoreSight ETM sample data is missed to set flags and it is always set to zeros, this results in perf tool skips to print string for instruction types. Arm CoreSight ETM supports different kind instruction of A64, A32 and T32; as the first step, this patch is to set sample flags for A64 instructions. The brief idea for implementation is describe as below: - For element with OCSD_GEN_TRC_ELEM_TRACE_ON type, it is taken as trace beginning packet; for element with OCSD_GEN_TRC_ELEM_NO_SYNC or OCSD_GEN_TRC_ELEM_EO_TRACE, these two kinds elements are used to set for trace end; - For instruction range packet, mainly base on three factors to decide the branch instruction types: elem->last_i_type elem->last_i_subtype elem->last_instr_cond If the instruction is immediate branch but without link and return flag, we consider it as function internal branch; in fact the immediate branch also can be used to invoke the function entry, usually this is only used in assembly code to directly call a symbol and don't expect to return back; after reviewing kernel normal functions and user space programs, both of them are very seldom to use immediate branch for function call. On the other hand, if we want to decide the immediate branch is for function branch jumping or for function calling, we need to rely on the start address of next packet and check the symbol offset for the start address, this will introduce much complexity in the implementation. So for this version we simply consider immediate branch as function internal branch. If the instruction is immediate branch with link, it's instruction 'BL' and which is used for function call. If the instruction is indirect branch without link, this is corresponding to instruction 'BR', this instruction usually is used for dynamic link lib with below usage; so we think it's a return instruction. 0000000000000680 <.plt>: 680: a9bf7bf0 stp x16, x30, [sp, #-16]! 684: 90000090 adrp x16, 10000 <__FRAME_END__+0xf630> 688: f947fe11 ldr x17, [x16, #4088] 68c: 913fe210 add x16, x16, #0xff8 690: d61f0220 br x17 If the instruction is indirect branch with link, e.g BLR, we think it's a function call. For function return, ARMv8 introduces a dedicated instruction 'ret', which has flag of OCSD_S_INSTR_V8_RET. - For exception packets, this patch divides into three types: The first type of exception is caused by external logics like bus, interrupt controller, debug module or PE reset or halt; this is corresponding to flags "bcyi" which defined in doc perf-script.txt; The second type is for system call, this is set as "bcs" by following definition in the doc; The third type is for CPU trap, data and instruction prefetch abort, alignment abort; usually these exceptions are synchronous for CPU, so set them as "bci" type. This part is not very certain that this patch has set right flags for them, the reason is the instruction trace decoding flags is original from Intel PT and it's briefly defined in the document: tools/perf/Documentation/perf-script.txt. But there have no more detailed information to explain these flags and their corresponding instructions. This patch set exception related flags based on the literal meaning which described in the doc, and should refine according to reviewing. Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Robert Walker <robert.walker(a)arm.com> Cc: Al Grant <Al.Grant(a)arm.com> Cc: Andi Kleen <andi(a)firstfloor.org> Cc: Adrian Hunter <adrian.hunter(a)intel.com> Cc: Arnaldo Carvalho de Melo <acme(a)redhat.com> Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 158 ++++++++++++++++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 + tools/perf/util/cs-etm.c | 4 +- 3 files changed, 161 insertions(+), 2 deletions(-) diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c index 938def6..b7cb962 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c @@ -347,6 +347,162 @@ cs_etm_decoder__buffer_trace_on(struct cs_etm_decoder *decoder, CS_ETM_TRACE_ON); } +static void cs_etm_decoder__set_sample_flags( + const void *context, + const ocsd_generic_trace_elem *elem) +{ + struct cs_etm_decoder *decoder = (struct cs_etm_decoder *) context; + struct cs_etm_packet *packet; + static u32 exc_num; + + packet = &decoder->packet_buffer[decoder->tail]; + + switch (elem->elem_type) { + case OCSD_GEN_TRC_ELEM_TRACE_ON: + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_TRACE_BEGIN; + break; + + case OCSD_GEN_TRC_ELEM_NO_SYNC: + case OCSD_GEN_TRC_ELEM_EO_TRACE: + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_TRACE_END; + break; + + case OCSD_GEN_TRC_ELEM_INSTR_RANGE: + /* + * Immediate branch instruction without neither link nor + * return flag, it's normal branch instruction within + * the function. + */ + if (elem->last_i_type == OCSD_INSTR_BR && + elem->last_i_subtype == OCSD_S_INSTR_NONE) { + packet->flags = PERF_IP_FLAG_BRANCH; + + if (elem->last_instr_cond) + packet->flags |= PERF_IP_FLAG_CONDITIONAL; + } + + /* + * Immediate branch instruction with link (e.g. BL), this is + * branch instruction for function call. + */ + if (elem->last_i_type == OCSD_INSTR_BR && + elem->last_i_subtype == OCSD_S_INSTR_BR_LINK) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_CALL; + + /* + * Indirect branch instruction without link (e.g. BR), usually + * this is used for function return, especially for functions + * within dynamic link lib. + */ + if (elem->last_i_type == OCSD_INSTR_BR_INDIRECT && + elem->last_i_subtype == OCSD_S_INSTR_NONE) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_RETURN; + + /* + * Indirect branch instruction with link (e.g. BLR), this is + * branch instruction for function call. + */ + if (elem->last_i_type == OCSD_INSTR_BR_INDIRECT && + elem->last_i_subtype == OCSD_S_INSTR_BR_LINK) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_CALL; + + /* Return instruction for function return. */ + if (elem->last_i_type == OCSD_INSTR_BR_INDIRECT && + elem->last_i_subtype == OCSD_S_INSTR_V8_RET) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_RETURN; + + break; + + case OCSD_GEN_TRC_ELEM_EXCEPTION: + +#define OCSD_EXC_RESET 0 +#define OCSD_EXC_DEBUG_HALT 1 +#define OCSD_EXC_CALL 2 +#define OCSD_EXC_TRAP 3 +#define OCSD_EXC_SYSTEM_ERROR 4 +#define OCSD_EXC_INST_DEBUG 6 +#define OCSD_EXC_DATA_DEBUG 7 +#define OCSD_EXC_ALIGNMENT 10 +#define OCSD_EXC_INST_FAULT 11 +#define OCSD_EXC_DATA_FAULT 12 +#define OCSD_EXC_IRQ 14 +#define OCSD_EXC_FIQ 15 + + /* + * Exception number is saved and can be used for return + * instruction analysis. + */ + exc_num = elem->exception_number; + + /* + * The exceptions are triggered by external signals + * from bus, interrupt controller, debug module, + * PE reset or halt. + */ + if (exc_num == OCSD_EXC_RESET || + exc_num == OCSD_EXC_DEBUG_HALT || + exc_num == OCSD_EXC_SYSTEM_ERROR || + exc_num == OCSD_EXC_INST_DEBUG || + exc_num == OCSD_EXC_DATA_DEBUG || + exc_num == OCSD_EXC_IRQ || + exc_num == OCSD_EXC_FIQ) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_CALL | + PERF_IP_FLAG_ASYNC | + PERF_IP_FLAG_INTERRUPT; + + /* The exception is for system call. */ + if (exc_num == OCSD_EXC_CALL) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_CALL | + PERF_IP_FLAG_SYSCALLRET; + + /* + * The exception is introduced by trap, instruction & + * data fault or alignment errors. + */ + if (exc_num == OCSD_EXC_TRAP || + exc_num == OCSD_EXC_ALIGNMENT || + exc_num == OCSD_EXC_INST_FAULT || + exc_num == OCSD_EXC_DATA_FAULT) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_CALL | + PERF_IP_FLAG_INTERRUPT; + + break; + + case OCSD_GEN_TRC_ELEM_EXCEPTION_RET: + if (exc_num == OCSD_EXC_CALL) + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_RETURN | + PERF_IP_FLAG_SYSCALLRET; + else + packet->flags = PERF_IP_FLAG_BRANCH | + PERF_IP_FLAG_RETURN | + PERF_IP_FLAG_INTERRUPT; + exc_num = -1; + break; + + case OCSD_GEN_TRC_ELEM_UNKNOWN: + case OCSD_GEN_TRC_ELEM_PE_CONTEXT: + case OCSD_GEN_TRC_ELEM_ADDR_NACC: + case OCSD_GEN_TRC_ELEM_TIMESTAMP: + case OCSD_GEN_TRC_ELEM_CYCLE_COUNT: + case OCSD_GEN_TRC_ELEM_ADDR_UNKNOWN: + case OCSD_GEN_TRC_ELEM_EVENT: + case OCSD_GEN_TRC_ELEM_SWTRACE: + case OCSD_GEN_TRC_ELEM_CUSTOM: + default: + break; + } +} + static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer( const void *context, const ocsd_trc_index_t indx __maybe_unused, @@ -390,6 +546,8 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer( break; } + cs_etm_decoder__set_sample_flags(context, elem); + return resp; } diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h index 612b575..9d5f65a 100644 --- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h +++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h @@ -36,6 +36,7 @@ struct cs_etm_packet { u8 exc; u8 exc_ret; int cpu; + u32 flags; }; struct cs_etm_queue; diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c index 3b37d66..bf66eb6 100644 --- a/tools/perf/util/cs-etm.c +++ b/tools/perf/util/cs-etm.c @@ -663,7 +663,7 @@ static int cs_etm__synth_instruction_sample(struct cs_etm_queue *etmq, sample.stream_id = etmq->etm->instructions_id; sample.period = period; sample.cpu = etmq->packet->cpu; - sample.flags = 0; + sample.flags = etmq->prev_packet->flags; sample.insn_len = 1; sample.cpumode = event->header.misc; @@ -719,7 +719,7 @@ static int cs_etm__synth_branch_sample(struct cs_etm_queue *etmq) sample.stream_id = etmq->etm->branches_id; sample.period = 1; sample.cpu = etmq->packet->cpu; - sample.flags = 0; + sample.flags = etmq->prev_packet->flags; sample.cpumode = PERF_RECORD_MISC_USER; /* -- 2.7.4

6 years, 9 months

OpenCSD v0.9.3 Released

by Mike Leach

-Moves ocsd_if_version.h into include/opencsd and adds to headers used as part of installation. -Fixes bug in snapshot reader library used by test programs to handle 'offset' parameter in [dump] sections correctly. -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

6 years, 9 months

[PATCH 0/3] opencsd: Update to instruction information supplied.

by Mike Leach

This patchset adds more information about the final instuction in the Instruction Range generic packet. i) A flag is set if the last instruction is conditional [last_instr_cond]. ii) for A32/T32 ISA, the instruction subtype will be set to 'Implied Return' [OCSD_S_INSTR_V7_IMPLIED_RET] if it is one of the instructions: mov pc,lr bx r14 pop {...,pc} ldr pc,[sp], #offset These are used by the CPU return predictor and in general by compilers when a return is required. The patchset also removes the uint32_t casts in the version #define OCSD_VER_NUM to enable correct use with pre-processor. Mike Leach (3): opencsd: Generic output packet - add additional instruction info opencsd: docs: Update documents for new generic packet field opencsd: Update README etc for version 0.10.0 README.md | 6 +++-- decoder/docs/doxygen_config.dox | 2 +- decoder/docs/prog_guide/prog_guide_generic_pkts.md | 3 ++- decoder/include/common/trc_gen_elem.h | 1 + .../include/opencsd/etmv4/trc_pkt_decode_etmv4i.h | 2 ++ decoder/include/opencsd/ocsd_if_types.h | 1 + decoder/include/opencsd/ocsd_if_version.h | 8 +++--- decoder/include/opencsd/trc_gen_elem_types.h | 1 + decoder/source/etmv3/trc_pkt_decode_etmv3.cpp | 1 + decoder/source/etmv4/trc_pkt_decode_etmv4i.cpp | 29 ++++++++++------------ decoder/source/i_dec/trc_i_decode.cpp | 1 + decoder/source/i_dec/trc_idec_arminst.cpp | 16 ++++++++++++ decoder/source/ocsd_dcd_tree.cpp | 1 - decoder/source/ptm/trc_pkt_decode_ptm.cpp | 2 ++ decoder/source/trc_gen_elem.cpp | 5 +++- 15 files changed, 53 insertions(+), 26 deletions(-) -- 2.14.2

6 years, 9 months

[Questions] perf sample flags for CoreSight

by leo.yan＠linaro.org

Hi Mathieu, Mike, [ + CoreSight list ] When reviewed Andi's patch 'tools, perf, script: Add --call-trace and --call-ret-trace' [1], I found after applying this patch with CoreSight, perf fails to output two fields: one is missing to output the sample flags (e.g. 'call', 'return', 'jmp', etc) [2], another missing is failed to output the symbols [3]. The cause for the issues is CoreSight doesn't set sample flags and simply set it to zero [4]. If I understand correctly (Mathieu also mentioned to me at connect), I think before you guys have awared for this. So want to check if you have existed fixing for this in case I am doing duplicate works at here? :) Or there have some discussion and known issues so cannot enable sample flags before? I did some investigation for these, CoreSight can set partial sample flags for A64 branch instructions with packet infos: - ocsd_generic_trace_elem::last_i_type can be used to check if the instruction is immediate branch instruction or indirect branch instruction; - ocsd_generic_trace_elem::last_i_subtype can be used to distinguish if it's link branch instruction (OCSD_S_INSTR_BR_LINK), if it's link branch instruction then this means this branch insturction is for function call; if it's return branch instruction (OCSD_S_INSTR_V8_RET), then it's return instruction; Otherwise (OCSD_S_INSTR_NONE), it's a simple branch instruction within the function. But there still have several things are not clear for me: - How can we distinguish the exception is for system call, or interrupt. The reason is we can see Intel-pt set sample flags for different values for different exception types: PERF_IP_FLAG_INTERRUPT PERF_IP_FLAG_SYSCALLRET I think we might can use ocsd_generic_trace_elem::exception_number to distinguish the different exception types, but I don't find any doc to clear define for this value. - I don't know if there have any info or hints in CoreSight packet can be used to indicate the branch is conditional branch or not. For Intel-pt, it can set the conditional branch instruction with flag: PERF_IP_FLAG_CONDITIONAL. - I understand it's low priority to support A32 and T32 instructions, but just note here I also don't have no idea for this part. Could you give some suggestion and guidance for this? Thanks in advance. Thanks, Leo Yan [1] https://lore.kernel.org/patchwork/patch/987916/ [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/too… [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/too… [4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/too…

6 years, 9 months

[PATCH v2 00/11] dts: Update coresight device tree bindings

by Suzuki K Poulose

Coresight DT bindings have been updated to obey the DTS rules for label/address matching for graph nodes. The changes are in coresight/next tree scheduled for v4.20. This series updates the in kernel dts to match the new bindings along with updating a couple of new examples (e.,g CATU) in the Documentation (which were missed as they were still in flight when we created the series). Please note that this should not be pulled for v4.19, which I think is a safe assumption. But please do pull it for v4.20. The dt updates for the Juno boards were sent earlier with the original DT update series and has been queued for v4.20. Applies on coresight/next (which is based on v4.19) and should apply cleanly on v4.19-rc3. Changes since V1: - Avoid "avoid_unnecessary_addr_size" warnings by removing #address-cells/#size-cells for single port with address 0. - Fix TPIU inport for qcom msm8196. (Leo Yan) - Fix documentation example for TPIU (Leo Yan) - Fix subject tags (as pointed out by Leo and Shawn) - Drop patch for TC2, which has been queued by Sudeep Cc: Alexandre Belloni <alexandre.belloni(a)bootlin.com> Cc: Andy Gross <andy.gross(a)linaro.org> Cc: Benoît Cousson <bcousson(a)baylibre.com> Cc: David Brown <david.brown(a)linaro.org> Cc: Fabio Estevam <fabio.estevam(a)nxp.com> Cc: Frank Rowand <frowand.list(a)gmail.com> Cc: Ivan T. Ivanov <ivan.ivanov(a)linaro.org> Cc: Linus Walleij <linus.walleij(a)linaro.org> Cc: linux-omap(a)vger.kernel.org Cc: lipengcheng8(a)huawei.com Cc: Liviu Dudau <liviu.dudau(a)arm.com> Cc: Lorenzo Pieralisi <lorenzo.pieralisi(a)arm.com> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Nicolas Ferre <nicolas.ferre(a)microchip.com> Cc: orsonzhai(a)gmail.com Cc: Pengutronix Kernel Team <kernel(a)pengutronix.de> Cc: Rob Herring <robh(a)kernel.org> Cc: Sascha Hauer <s.hauer(a)pengutronix.de> Cc: Shawn Guo <shawnguo(a)kernel.org> Cc: Sudeep Holla <sudeep.holla(a)arm.com> Cc: Tony Lindgren <tony(a)atomide.com> Cc: Wei Xu <xuwei5(a)hisilicon.com> Cc: xuwei5(a)hisilicon.com Cc: zhang.lyra(a)gmail.com Cc: arm(a)kernel.org Suzuki K Poulose (11): coresight: dts: binding: Fix example for TPIU component coresight: dts: binding: Update coresight binding examples arm64: dts: hi6220: Update coresight bindings for hardware ports arm64: dts: sc9836/sc9860: Update coresight bindings for hardware ports arm64: dts: msm8916: Update coresight bindings for hardware ports arm: dts: hip04: Update coresight bindings for hardware ports arm: dts: imx7: Update coresight binding for hardware ports arm: dts: omap: Update coresight bindings for hardware ports arm: dts: qcom: Update coresight bindings for hardware ports arm: dts: sama5d2: Update coresight bindings for hardware ports arm: dts: ste-dbx5x0: Update coresight bindings for hardware port .../devicetree/bindings/arm/coresight.txt | 27 +- arch/arm/boot/dts/hip04.dtsi | 346 +++++++++--------- arch/arm/boot/dts/imx7d.dtsi | 14 +- arch/arm/boot/dts/imx7s.dtsi | 82 ++--- arch/arm/boot/dts/omap3-beagle-xm.dts | 17 +- arch/arm/boot/dts/omap3-beagle.dts | 17 +- arch/arm/boot/dts/qcom-apq8064.dtsi | 71 ++-- arch/arm/boot/dts/qcom-msm8974.dtsi | 104 +++--- arch/arm/boot/dts/sama5d2.dtsi | 17 +- arch/arm/boot/dts/ste-dbx5x0.dtsi | 65 ++-- .../boot/dts/hisilicon/hi6220-coresight.dtsi | 181 +++++---- arch/arm64/boot/dts/qcom/msm8916.dtsi | 95 ++--- arch/arm64/boot/dts/sprd/sc9836.dtsi | 82 +++-- arch/arm64/boot/dts/sprd/sc9860.dtsi | 215 +++++------ 14 files changed, 682 insertions(+), 651 deletions(-) -- 2.19.0

6 years, 9 months

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