CoreSight

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2389 discussions

[PATCH 0/3] perf tools: Add support for ETMv3/PTM1.1 decoding

by Mathieu Poirier

This set _should_ add support for ETMv3/PTM1.1 trace decoding. It was produced close to two years ago on top of a code base that no longer exist. At the time though, it did work. So I've rebased the work to the current coresight next branch. It apply and compiles cleanly but other than that, I can't offer any guarantee of proper operation. I am currently traveling and don't have access to a platform where it can be tested. Even if I was, I do not have the bandwidth to work on the feature. As such I am releasing it on this list, in the hope that it can help someone get started with trace decoding on ETMv3/PTM1.1. Let me know how bad it crashes. Mathieu Mathieu Poirier (3): perf tools: Add configuration for ETMv3 trace protocol perf tools: Add support for ETMv3 trace decoding perf tools: Add support for PTMv1.1 decoding tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 31 +++++++++++ tools/perf/util/cs-etm-decoder/cs-etm-decoder.h | 9 +++ tools/perf/util/cs-etm.c | 73 ++++++++++++++++++++----- 3 files changed, 99 insertions(+), 14 deletions(-) -- 2.7.4

6 years, 9 months

Re: Coresight traces of the same application decode differently.

by Mike Bazov

Hello, Sorry for the delay. I appreciate your posts. I have recorded a different program now("ping 8.8.8.8"), and it seems that decoding the trace using the "ping" ELF file gives no issues now. I cannot explain how "ls" is the only corrupt trace(i rerecorded, same results). Perhaps the image is indeed wrong. I will check it further. Thank you very much! On Thu, Sep 20, 2018 at 10:42 AM, Mike Bazov <mike(a)perception-point.io> wrote: > Hello, > > Sorry for the delay. I appreciate your posts. > > I have recorded a different program now("ping 8.8.8.8"), and it seems that > decoding > the trace using the "ping" ELF file gives no issues now. I cannot explain > how "ls" > is the only corrupt trace(i rerecorded, same results). Perhaps the image > is indeed wrong. > I will check it further. > > Thank you very much! > > Mike. > > > On Thu, Sep 20, 2018 at 1:28 AM, Mike Leach <mike.leach(a)linaro.org> wrote: > >> Hi Mike, >> >> I have looked into this issue further, found my previous assumption to >> be wrong, and unfortunately have come to the conclusion that the >> generated trace is somehow wrong / corrupt, or the supplied image is >> not what was run when the trace was generated. >> >> If you look at the attached analysis of the trace generated from the >> ls_api.cs data [analysis001.txt] This is at the very start of the >> traced image. >> >> The first few packets [raw packets (0)] show the sync and start at >> 00000000004003f0 <_start>: >> followed by the first 'E' atom that marks the branch to 0x41a158. The >> next two 'E' atoms get us to 0x41a028. >> >> At this point we get an exception packet, followed by a preferred >> return address packet [ raw packets (2)]. >> This return address is 0x400630. >> >> The rules from the ETM architecture specification 4.0-4.4 p6-242 state:- >> >> "The Exception packet contains an address. This means that execution >> has continued from the target of the most >> recent P0 element, up to, but not including, that address, and a trace >> analyzer must analyze each instruction in this >> range." >> >> Thus the decoder is required to analyze from the previous P0 element - >> the 'E' atom that marked the branch to 0x41a028, until the preferred >> return address. >> This is actually lower than the start address, which results in a huge >> range seen here, and also seen by you in the example you described. >> The decoder effectively runs off the end of the memory image before it >> stops. >> >> The trace should be indicating an address after but relatively close >> to 0x41a028 - as otherwise an atom would have been emitted by the cbnz >> 41a054. >> >> If I examine the start of the perf_ls.cs decode, I see the same 3 'E' >> atoms followed by the odd data fault exception. >> >> So for the first few branches at least, the perf and api captures go >> in the same direction. >> >> Given the it is unlikely that the generated trace packets are >> incorrect - it seems more likely that the 'ls' image being used for >> decode is not what is generating this trace. Since we have to analyze >> opcodes to follow the 'E' and 'N' atoms, decode relies on accurate >> memory images being fed into the decoder. The only actual addresses we >> have explicitly stated in the trace are the start: 0x4003f0, and the >> exception return address 0x400360. The others are synthesized from the >> supplied image. >> >> There may be a case for checking when decoding the exception packet >> that the address is not behind the current location and throwing an >> error, but beyond that I do not at this point believe that the decoder >> is at fault. >> >> Regards >> >> Mike >> >> >> >> On 18 September 2018 at 19:32, Mike Leach <mike.leach(a)linaro.org> wrote: >> > Hi Mike, >> > >> > I've looked further at this today, and can see a location where a >> > large block appears in both the api and perf trace data on decode >> > using the library test program. >> > >> > There does appear to be an issue if the decoder is in a "waiting for >> > address state" i.e. it has lost track usually because an area of >> > memory is unavailable, and an exception packet is seen - the exception >> > address appears to be used twice - both to complete an address range >> > and as an exception return - hence in this case the improbable large >> > block. I need to look into this in more detail and fix it up. >> > >> > However - I am seeing before this the api and perf decodes have >> > diverged, which suggests an issue elsewhere too perhaps. I do need to >> > look deeper into this as well. >> > I am not 100% certain that using the ls.bin as a full memory image at >> > 0x400000 is necessarily working in the snapshot tests - there might be >> > another offset needed to access the correct opcodes for the trace. >> > >> > I'll let you know if I make further progress. >> > >> > >> > On 17 September 2018 at 16:53, Mike Leach <mike.leach(a)linaro.org> >> wrote: >> >> Hi Mike, >> >> >> >> I've looked at the data you supplied. >> >> >> >> I created test snapshot directories so that I could run each of the >> >> trace data files through the trc_pkt_lister test program (the attached >> >> .tgz file contains these, plus the results). >> >> >> >> Now the two trace files are different sizes - this is explained by the >> >> fact that the api trace run had cycle counts switched on, whereas the >> >> perf run did not - plus the perf run turned off the trace while in >> >> kernel calls - the api left the trace on, though filtering out the >> >> kernel - but a certain amount of sync packets have come through adding >> >> to the size. >> >> >> >> Now looking at the results I cannot see the 0x4148f4 location in >> >> either trace dump (perf_ls2.ppl and api_ls2.ppl in the .tgz). >> >> >> >> There are no obvious differences I could detect in the results, though >> >> they are difficult to compare given the difference in output. >> >> >> >> The effect you are seeing does look like some sort of runaway - with >> >> the decoder searching for opcodes - possibly in a section of the ls >> >> binary file that does not contain executable code - till it happens >> >> upon something that looks like an opcode. >> >> >> >> At this point I cannot explain the difference you and I are seeing >> >> given the data provided. Can you look at the snapshot results, and see >> >> if there is anything there? You can re-run the tests I ran if you >> >> rename ls to ls.bin and put on level up from the ss-perf or ss-api >> >> snapshot directories where the file is referenced to. >> >> >> >> Regards >> >> >> >> Mike >> >> >> >> >> >> >> >> >> >> On 17 September 2018 at 13:44, Mike Bazov <mike(a)perception-point.io> >> wrote: >> >>> Greetings, >> >>> >> >>> I recorded the program "ls" (statically linked to provide a single >> >>> executable as a memory accesses file). >> >>> >> >>> I recorded the program using perf, and then extracted the actual raw >> trace >> >>> data from the perf.data file using a little tool i wrote. I can use >> OpenCSD >> >>> to fully decode the trace produced by perf. >> >>> >> >>> I also recorded the "ls" util using an API i wrote from kernel mode. I >> >>> published the API here as an [RFC]. Basically, i start recording and >> stop >> >>> recording whenever the __process__ of my interest is scheduling in. >> >>> This post is not much about requesting a review for my API.. but i do >> have >> >>> some issues with the trace that is produced by this API, and i'm not >> quite >> >>> sure why. >> >>> >> >>> I use the OpenCSD directly in my code, and register a decoder >> callback for >> >>> every generic trace element. When my callback is called, i simply >> print the >> >>> element string representation(e.g. OCSD_GEN_TRC_ELEM_INSTR_RANGE). >> >>> >> >>> Now, the weird thing is the perf and API produce the same generic >> elements >> >>> until a certain element: >> >>> >> >>> OCSD_GEN_TRC_ELEM_TRACE_ON() >> >>> ... >> >>> ... >> >>> ... same elements... >> >>> ... same elements... >> >>> ... same elements... >> >>> ... >> >>> ... >> >>> >> >>> And eventually diverge from each other. I assume the perf trace is >> going in >> >>> the right direction, but my trace simply starts going nuts. The last >> >>> __common__ generic element is the following: >> >>> >> >>> OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x4148f4:[0x414910] >> (ISA=A64) E iBR >> >>> A64:ret ) >> >>> >> >>> After this element, perf trace goes in a different route, and the API >> right >> >>> afterwards produced a very weird instruction range element: >> >>> >> >>> OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x414910:[0x498a20] >> (ISA=A64) E --- >> >>> ) >> >>> >> >>> There is no way this 0x498a20 address was reached, and i cannot see >> any >> >>> proof for it in the trace itself(using ptm2human). It seems that the >> decoder >> >>> keeps decoding and disassembling opcodes until it reaches 0x498a20... >> my >> >>> memory callback(callback that is called if the decoder needs memory >> that >> >>> isn't present) is called for the address 0x498a20. From the on, the >> trace >> >>> just goes into a very weird path. I can't explain the address >> branches that >> >>> are taken from here on. >> >>> >> >>> >> >>> Any ideas on how to approach this? OpenCSD experts would be >> appreciated. >> >>> I have attached the perf and API trace, and the "ls" executable which >> is >> >>> loaded into address 0x400000. I also attached the ETMv4 config for >> every >> >>> trace(trace id, etc..). There is no need to create multiple decoders >> for >> >>> different trace ids, theres only a single ID for a single decoder. >> >>> >> >>> Thanks, >> >>> Mike. >> >>> >> >>> _______________________________________________ >> >>> CoreSight mailing list >> >>> CoreSight(a)lists.linaro.org >> >>> https://lists.linaro.org/mailman/listinfo/coresight >> >>> >> >> >> >> >> >> >> >> -- >> >> Mike Leach >> >> Principal Engineer, ARM Ltd. >> >> Manchester Design Centre. UK >> > >> > >> > >> > -- >> > Mike Leach >> > Principal Engineer, ARM Ltd. >> > Manchester Design Centre. UK >> >> >> >> -- >> Mike Leach >> Principal Engineer, ARM Ltd. >> Manchester Design Centre. UK >> > >

6 years, 9 months

New OpenCSD library release v0.9.2

by Mike Leach

Updated library: - fixes bug with generic exception packets being set with wrong exception number in ETMv4 - updates docs with latest AutoFDO instructions, and record.sh script -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

6 years, 9 months

Coresight traces of the same application decode differently.

by Mike Bazov

Greetings, I recorded the program "ls" (statically linked to provide a single executable as a memory accesses file). I recorded the program using perf, and then extracted the actual raw trace data from the perf.data file using a little tool i wrote. I can use OpenCSD to fully decode the trace produced by perf. I also recorded the "ls" util using an API i wrote from kernel mode. I published the API here as an* [RFC]*. Basically, i start recording and stop recording whenever the __process__ of my interest is scheduling in. This post is not much about requesting a review for my API.. but i do have some issues with the trace that is produced by this API, and i'm not quite sure why. I use the OpenCSD directly in my code, and register a decoder callback for every generic trace element. When my callback is called, i simply print the element string representation(e.g. OCSD_GEN_TRC_ELEM_INSTR_RANGE). Now, the weird thing is the perf and API produce the same generic elements until a certain element: OCSD_GEN_TRC_ELEM_TRACE_ON() ... ... ... same elements... ... same elements... ... same elements... ... ... And eventually diverge from each other. I assume the perf trace is going in the right direction, but my trace simply starts going nuts. The last *__common__* generic element is the following: OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x4148f4:[0x414910] (ISA=A64) E iBR A64:ret ) After this element, perf trace goes in a different route, and the API right afterwards produced a very *weird *instruction range element: OCSD_GEN_TRC_ELEM_INSTR_RANGE(exec range=0x414910:[0x498a20] (ISA=A64) E --- ) There is no way this 0x498a20 address was reached, and i cannot see any proof for it in the trace itself(using ptm2human). It seems that the decoder keeps decoding and disassembling opcodes until it reaches 0x498a20... my memory callback(callback that is called if the decoder needs memory that isn't present) is called for the address 0x498a20. From the on, the trace just goes into a very weird path. I can't explain the address branches that are taken from here on. Any ideas on how to approach this? OpenCSD experts would be appreciated. I have attached the perf and API trace, and the "ls" executable which is loaded into address 0x400000. I also attached the ETMv4 config for every trace(trace id, etc..). There is no need to create multiple decoders for different trace ids, theres only a single ID for a single decoder. Thanks, Mike.

6 years, 9 months

CoreSight trace decoding for ARMv7

by Stefan Agner

Hi, Attending the Hardware Trace on Linux talk at Linaro Connect the topic of ARMv7 support for trace decoding came up. What is the current state and are there patches available somewhere? -- Stefan

6 years, 9 months

[RFC 1/4] coresight: tmc-etr: Introduce CS_MODE_API and prepare the ground for it

by mike＠perception-point.io

From: Mike Bazov <mike(a)perception-point.io> Introducing a new mode: CS_MODE_API. This mode shall be used by the etm-api framework to expose coresight functionality to kernel mode clients. This commit makes tmc-etr aware of it. The set_buffer()/alloc_buffer()/free_buffer() sink operations are now turned to be mode-oriented. Up to this commit they were perf-specific, because only the perf framework used it. They are now extended to also be used with CS_MODE_API, in the hope of giving a kernel mode client the power of allocating and using a coresight buffer. tmc-etr forbids using the sink for CS_MODE_API mode concurrently with other session modes(perf/sysfs). The implementation doesn't forbid using the sink multiple times if the requested mode is CS_MODE_API. This commit also makes the perf framework aware of the sink operations function signature changes. Signed-off-by: Mike Bazov <mike(a)perception-point.io> --- drivers/hwtracing/coresight/coresight-etb10.c | 13 ++- drivers/hwtracing/coresight/coresight-etm-perf.c | 7 +- drivers/hwtracing/coresight/coresight-priv.h | 1 + drivers/hwtracing/coresight/coresight-tmc-etf.c | 16 ++- drivers/hwtracing/coresight/coresight-tmc-etr.c | 124 +++++++++++++++++++---- drivers/hwtracing/coresight/coresight-tmc.h | 3 +- include/linux/coresight.h | 10 +- 7 files changed, 139 insertions(+), 35 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c index 08fa660098f8..4fbc8af7851a 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -323,12 +323,15 @@ static void etb_disable(struct coresight_device *csdev) dev_dbg(drvdata->dev, "ETB disabled\n"); } -static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, +static void *etb_alloc_buffer(struct coresight_device *csdev, u32 mode, int cpu, void **pages, int nr_pages, bool overwrite) { int node; struct cs_buffers *buf; + if (mode != CS_MODE_PERF) + return NULL; + if (cpu == -1) cpu = smp_processor_id(); node = cpu_to_node(cpu); @@ -344,11 +347,13 @@ static void *etb_alloc_buffer(struct coresight_device *csdev, int cpu, return buf; } -static void etb_free_buffer(void *config) +static void etb_free_buffer(u32 mode, void *config) { - struct cs_buffers *buf = config; + if (mode != CS_MODE_API) { + struct cs_buffers *buf = config; - kfree(buf); + kfree(buf); + } } static int etb_set_buffer(struct coresight_device *csdev, diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index abe8249b893b..563f4b47e977 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -119,7 +119,8 @@ static void free_event_data(struct work_struct *work) cpu = cpumask_first(mask); sink = coresight_get_sink(etm_event_cpu_path(event_data, cpu)); if (sink_ops(sink)->free_buffer) - sink_ops(sink)->free_buffer(event_data->snk_config); + sink_ops(sink)->free_buffer(CS_MODE_PERF, + event_data->snk_config); } for_each_cpu(cpu, mask) { @@ -250,7 +251,8 @@ static void *etm_setup_aux(int event_cpu, void **pages, /* Allocate the sink buffer for this session */ event_data->snk_config = - sink_ops(sink)->alloc_buffer(sink, cpu, pages, + sink_ops(sink)->alloc_buffer(sink, CS_MODE_PERF, + cpu, pages, nr_pages, overwrite); if (!event_data->snk_config) goto err; @@ -284,6 +286,7 @@ static void etm_event_start(struct perf_event *event, int flags) goto fail; path = etm_event_cpu_path(event_data, cpu); + /* We need a sink, no need to continue without one */ sink = coresight_get_sink(path); if (WARN_ON_ONCE(!sink)) diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h index c11da5564a67..174e6f1fab3e 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -72,6 +72,7 @@ enum cs_mode { CS_MODE_DISABLED, CS_MODE_SYSFS, CS_MODE_PERF, + CS_MODE_API }; /** diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c index 4156c95ce1bb..897dfc1bcbaa 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -307,12 +307,16 @@ static void tmc_disable_etf_link(struct coresight_device *csdev, dev_dbg(drvdata->dev, "TMC-ETF disabled\n"); } -static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, int cpu, - void **pages, int nr_pages, bool overwrite) +static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, u32 mode, + int cpu, void **pages, int nr_pages, + bool overwrite) { int node; struct cs_buffers *buf; + if (mode == CS_MODE_API) + return NULL; + if (cpu == -1) cpu = smp_processor_id(); node = cpu_to_node(cpu); @@ -329,11 +333,13 @@ static void *tmc_alloc_etf_buffer(struct coresight_device *csdev, int cpu, return buf; } -static void tmc_free_etf_buffer(void *config) +static void tmc_free_etf_buffer(u32 mode, void *config) { - struct cs_buffers *buf = config; + if (mode != CS_MODE_API) { + struct cs_buffers *buf = config; - kfree(buf); + kfree(buf); + } } static int tmc_set_etf_buffer(struct coresight_device *csdev, diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 56fea4ff947e..6ffcaaf76680 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1176,32 +1176,35 @@ tmc_etr_setup_perf_buf(struct tmc_drvdata *drvdata, int node, int nr_pages, return etr_perf; } - -static void *tmc_alloc_etr_buffer(struct coresight_device *csdev, - int cpu, void **pages, int nr_pages, - bool snapshot) +static void *tmc_etr_alloc_api_buffer(struct tmc_drvdata *drvdata, int cpu, + int nr_pages, void **pages, bool snapshot) { - struct etr_perf_buffer *etr_perf; - struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + ssize_t size = 0; - if (cpu == -1) - cpu = smp_processor_id(); + size = nr_pages << PAGE_SHIFT; - etr_perf = tmc_etr_setup_perf_buf(drvdata, cpu_to_node(cpu), - nr_pages, pages, snapshot); - if (IS_ERR(etr_perf)) { - dev_dbg(drvdata->dev, "Unable to allocate ETR buffer\n"); - return NULL; - } + return tmc_alloc_etr_buf(drvdata, size, 0, cpu_to_node(0), pages); +} - etr_perf->snapshot = snapshot; - etr_perf->nr_pages = nr_pages; - etr_perf->pages = pages; +void *tmc_alloc_etr_buffer(struct coresight_device *csdev, u32 mode, + int cpu, void **pages, int nr_pages, bool snapshot) +{ + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); - return etr_perf; + switch (mode) { + case CS_MODE_PERF: + return tmc_etr_setup_perf_buf(drvdata, cpu, nr_pages, + pages, snapshot); + case CS_MODE_API: + return tmc_etr_alloc_api_buffer(drvdata, cpu, nr_pages, + pages, snapshot); + default: + /* We shouldn't get here. */ + return ERR_PTR(-EINVAL); + } } -static void tmc_free_etr_buffer(void *config) +static void tmc_etr_free_perf_buffer(void *config) { struct etr_perf_buffer *etr_perf = config; @@ -1210,6 +1213,61 @@ static void tmc_free_etr_buffer(void *config) kfree(etr_perf); } +static void tmc_etr_free_api_buffer(void *buffer) +{ + if (buffer) + tmc_free_etr_buf(buffer); +} + +static void tmc_free_etr_buffer(u32 mode, void *buffer) +{ + switch (mode) { + case CS_MODE_PERF: + tmc_etr_free_perf_buffer(buffer); + break; + case CS_MODE_API: + tmc_etr_free_api_buffer(buffer); + default: + break; + } +} + +static int tmc_etr_set_api_buffer(struct coresight_device *csdev, void *buffer) +{ + struct etr_buf *etr_buf = buffer; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + unsigned long flags; + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* + * Disable the etr if it's running. The user must pause any playing + * sources if it doesn't want to lose data. + */ + if (drvdata->mode == CS_MODE_API && drvdata->api_buf != NULL) + tmc_etr_disable_hw(drvdata); + + drvdata->api_buf = etr_buf; + + if (drvdata->mode == CS_MODE_API && drvdata->api_buf != NULL) + tmc_etr_enable_hw(drvdata, drvdata->api_buf); + + spin_unlock_irqrestore(&drvdata->spinlock, flags); + + return 0; +} + +static int tmc_etr_set_buffer(struct coresight_device *csdev, u32 mode, + struct perf_output_handle *handle, void *buffer) +{ + switch (mode) { + case CS_MODE_API: + return tmc_etr_set_api_buffer(csdev, buffer); + default: + return -EINVAL; + } +} + /* * tmc_etr_sync_perf_buffer: Copy the actual trace data from the hardware * buffer to the perf ring buffer. @@ -1350,6 +1408,29 @@ static int tmc_enable_etr_sink_perf(struct coresight_device *csdev, void *data) return rc; } +static int tmc_enable_etr_sink_api(struct coresight_device *csdev) +{ + int rc = 0; + unsigned long flags; + struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); + + spin_lock_irqsave(&drvdata->spinlock, flags); + + /* + * If the sink is already being used by someone, we cannot interfere. + */ + if (drvdata->mode != CS_MODE_DISABLED && + drvdata->mode != CS_MODE_API) { + rc = -EBUSY; + goto out; + } + + drvdata->mode = CS_MODE_API; +out: + spin_unlock_irqrestore(&drvdata->spinlock, flags); + return rc; +} + static int tmc_enable_etr_sink(struct coresight_device *csdev, u32 mode, void *data) { @@ -1358,13 +1439,15 @@ static int tmc_enable_etr_sink(struct coresight_device *csdev, return tmc_enable_etr_sink_sysfs(csdev); case CS_MODE_PERF: return tmc_enable_etr_sink_perf(csdev, data); + case CS_MODE_API: + return tmc_enable_etr_sink_api(csdev); } /* We shouldn't be here */ return -EINVAL; } -static void tmc_disable_etr_sink(struct coresight_device *csdev) +void tmc_disable_etr_sink(struct coresight_device *csdev) { unsigned long flags; struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); @@ -1391,6 +1474,7 @@ static const struct coresight_ops_sink tmc_etr_sink_ops = { .disable = tmc_disable_etr_sink, .alloc_buffer = tmc_alloc_etr_buffer, .update_buffer = tmc_update_etr_buffer, + .set_buffer = tmc_etr_set_buffer, .free_buffer = tmc_free_etr_buffer, }; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h index 487c53701e9c..39c6646c82d3 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -172,6 +172,7 @@ struct etr_buf { * device configuration register (DEVID) * @perf_data: PERF buffer for ETR. * @sysfs_data: SYSFS buffer for ETR. + * @api_buf: API buffer for ETR. */ struct tmc_drvdata { void __iomem *base; @@ -193,6 +194,7 @@ struct tmc_drvdata { u32 etr_caps; struct etr_buf *sysfs_buf; void *perf_data; + struct etr_buf *api_buf; }; struct etr_buf_operations { @@ -257,7 +259,6 @@ extern const struct coresight_ops tmc_etr_cs_ops; ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos, size_t len, char **bufpp); - #define TMC_REG_PAIR(name, lo_off, hi_off) \ static inline u64 \ tmc_read_##name(struct tmc_drvdata *drvdata) \ diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 53535821dc25..8f7f98570afd 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -183,16 +183,20 @@ struct coresight_device { * Operations available for sinks * @enable: enables the sink. * @disable: disables the sink. - * @alloc_buffer: initialises perf's ring buffer for trace collection. + * @alloc_buffer: allocates the trace buffer. * @free_buffer: release memory allocated in @get_config. + * @set_buffer: set the trace buffer. * @update_buffer: update buffer pointers after a trace session. */ struct coresight_ops_sink { int (*enable)(struct coresight_device *csdev, u32 mode, void *data); void (*disable)(struct coresight_device *csdev); - void *(*alloc_buffer)(struct coresight_device *csdev, int cpu, + void *(*alloc_buffer)(struct coresight_device *csdev, u32 mode, int cpu, void **pages, int nr_pages, bool overwrite); - void (*free_buffer)(void *config); + void (*free_buffer)(u32 mode, void *buffer); + int (*set_buffer)(struct coresight_device *csdev, u32 mode, + struct perf_output_handle *handle, + void *buffer); unsigned long (*update_buffer)(struct coresight_device *csdev, struct perf_output_handle *handle, void *sink_config); -- 2.16.2

6 years, 9 months

[PATCH v5 0/6] Coresight: Support panic kdump

by Leo Yan

This patch set is to explore Coresight tracing data for postmortem debugging. When kernel panic happens, the Coresight panic kdump can help to save on-chip tracing data and tracer metadata into DRAM, later relies on kdump and crash/perf tools to recovery tracing data for "offline" analysis. Comparing the patch series v4 and previous series, this patch series has heavily refactored the implementation after investigated Intel PT for kdump support. Intel PT calls one function for emergency stopping trace when kernel panic occurs, in the function it reuses perf operation to dump trace data into ring buffer, later crash tool extracts trace data from perf ring buffer. This patch series takes Intel PT as an example to use the same way to stop ETM trace with perf mode. So far the related work is primarily to focus on to support Coresight kdump with perf mode and we can add support SysFS mode if later there have more clear requirement. Comparing to previous series, this patch series also simplifies the handling for tracer metadata. The old series introduced extra data structure and two double link lists to maintain CoreSignt kdump components; in the old implementation, one list was used to track tracer metadata and another list was used to trace dump buffers, later these two lists can be used to retrieve metadata and trace data buffer from vmcore file. In this patch series it directly relies on CoreSight driver global variables to retrieve related info, e.g. for perf mode we can rely on per CPU pointer 'ctx_handle' to get perf ring buffer related info and 'csdev_src' is for per CPU tracer device structure for metadata. The crash extension program now has been enhanced to parse the data structures in the kernel and use them to extract metadata and dump trace data [1]; the crash extension program is updated to build with OpenCSD decoder so this can simplize the decoding process, rather than before needs to use perf to help decoding trace data. This patch series has been verified on 96boards DB410c with below steps, the 'long_loop' is a pretty simple program to only execute big number loops so can generate big amount number of branch instructions. Enable trace on the target board: $ perf record -e cs_etm/(a)825000.etf/ --per-thread ./long_loop & $ sleep 3 $ echo c > /proc/sysrq-trigger Use crash tool for post analysis: $ crash vmcore vmlinux crash> extend arm_cs_dump.so crash> arm_cs_dump -o out [1] https://git.linaro.org/people/leo.yan/crash.git/log/?h=arm_cs_dump_etm_perf Changes from v4: * Support for CoreSight ETM with perf mode; * Add API for crash stop; * Simplized implementation with removing kdump dedicated data structures and functions; Changes from v3: * Following Mathieu suggestion, reworked the panic kdump framework, used kdump array to maintain source and sink device handlers; * According to Mathieu suggestion, optimized panic notifier to firstly dump panic CPU tracing data and then dump other CPUs tracing data; * Refined doc to reflect these implementation changes; * Changed ETMv4 driver to add source device handler at probe phase; * Refactored crash extension program to reflect kernel changes. Changes from v2: * Add the two patches for documentation. * Following Mathieu suggestion, reworked the panic kdump framework, removed the useless flag "PRE_PANIC". * According to comment, changed to add and delete kdump node operations in sink enable/disable functions; * According to Mathieu suggestion, handle kdump node addition/deletion/updating separately for sysFS interface and perf method. Changes from v1: * Add support to dump ETMv4 meta data. * Wrote 'crash' extension csdump.so so rely on it to generate 'perf' format compatible file. * Refactored panic dump driver to support pre & post panic dump. Changes from RFC: * Follow Mathieu's suggestion, use general framework to support dump functionality. * Changed to use perf to analyse trace data. Leo Yan (6): doc: Add Coresight documentation directory doc: Add documentation for Coresight panic kdump coresight: etm4x: Save ID values in config structure coresight: tmc: Update latest value for page index and offset coresight: etm-perf: Add interface to stop etm trace arm64: smp: Stop CoreSight trace for kdump .../trace/{ => coresight}/coresight-cpu-debug.txt | 0 .../trace/coresight/coresight-panic-kdump.txt | 99 ++++++++++++++++++++++ Documentation/trace/{ => coresight}/coresight.txt | 0 MAINTAINERS | 5 +- arch/arm64/kernel/smp.c | 5 ++ drivers/hwtracing/coresight/Kconfig | 10 +++ drivers/hwtracing/coresight/coresight-etm-perf.c | 10 +++ drivers/hwtracing/coresight/coresight-etm4x.c | 7 ++ drivers/hwtracing/coresight/coresight-etm4x.h | 8 ++ drivers/hwtracing/coresight/coresight-tmc-etf.c | 8 ++ include/linux/coresight.h | 6 ++ 11 files changed, 156 insertions(+), 2 deletions(-) rename Documentation/trace/{ => coresight}/coresight-cpu-debug.txt (100%) create mode 100644 Documentation/trace/coresight/coresight-panic-kdump.txt rename Documentation/trace/{ => coresight}/coresight.txt (100%) -- 2.7.4

6 years, 9 months

[PATCH] crash: arm_cs_dump: Support Coresight trace dump with perf mode

by Leo Yan

This patch is to add support Coresight trace dump with perf mode from vmcore file. After kernel panic we can get kernel dump file vmcore and after enabling kernel configuration CONFIG_CORESIGHT_KDUMP the ETM trace data will be stored into vmcore file; this patch is to extract CoreSight ETM metadata from ETM driver data structure and config structure and use OpenCSD lib to decode ETM trace data. It checks perf ring buffer and if the ring buffer is wrap around yet, the code firstly dump the tail of aux pages and then continue to dump data from the head of aux page. So finally we can merge the complete trace data from ring buffer. If the ring buffer isn't wrap around, then it's straightforward to dump data from the head of pages to the last writing point. This is the initial version to only support ETMv4 trace data, later can extend this program to support more tracers. To let this version for easily applying for users, the command is pretty simple: crash> extend arm_cs_dump.so crash> arm_cs_dump -o output_dir Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Signed-off-by: Leo Yan <leo.yan(a)linaro.org> --- extensions/arm_cs_dump.c | 955 ++++++++++++++++++++++++++++++++ extensions/arm_cs_dump.mk | 39 ++ extensions/arm_cs_dump/arm_cs_decoder.c | 319 +++++++++++ extensions/arm_cs_dump/arm_cs_decoder.h | 40 ++ 4 files changed, 1353 insertions(+) create mode 100644 extensions/arm_cs_dump.c create mode 100644 extensions/arm_cs_dump.mk create mode 100644 extensions/arm_cs_dump/arm_cs_decoder.c create mode 100644 extensions/arm_cs_dump/arm_cs_decoder.h diff --git a/extensions/arm_cs_dump.c b/extensions/arm_cs_dump.c new file mode 100644 index 0000000..a0f46b0 --- /dev/null +++ b/extensions/arm_cs_dump.c @@ -0,0 +1,955 @@ +/* + * Extension module to extract dump buffer of ARM Coresight Trace + * + * Copyright (C) 2017, 2018 Linaro Ltd + * Author: Leo Yan <leo.yan(a)linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define _GNU_SOURCE +#include "defs.h" +#include <sys/file.h> +#include <sys/types.h> +#include "arm_cs_dump/arm_cs_decoder.h" + +#ifdef DEBUG +#define dbgprintf(...) fprintf(__VA_ARGS__) +#else +#define dbgprintf(...) {} +#endif + +#define INPUT_BLOCK_SIZE 1024 + +#define CS_MODE_NONE 0 +#define CS_MODE_PERF 1 + +struct arm_cs_info { + int mode; + + ulong aux_pages; + int aux_nr_pages; + ulong etm_event_data; + + ulong *buffer_ptr; + int curr_buf_idx; + ulong curr_buf_off; + ulong curr_data_sz; +} *arm_cs_info_list; + + +#define koffset(struct, member) struct##_##member##_offset + +/* at = ((struct *)ptr)->member */ +#define read_value(at, ptr, struct, member) \ +do { \ + readmem(ptr + koffset(struct, member), KVADDR, \ + &at, sizeof(at), #struct "'s " #member, \ + RETURN_ON_ERROR); \ +} while (0) + +#define init_offset(struct, member) \ +do { \ + koffset(struct, member) = MEMBER_OFFSET(#struct, #member); \ + if (koffset(struct, member) < 0) { \ + fprintf(fp, "failed to init the offset, struct:" \ + #struct ", member:" #member); \ + fprintf(fp, "\n"); \ + return -1; \ + } \ +} while (0) + + +static int koffset(perf_output_handle, event); +static int koffset(perf_output_handle, rb); + +static int koffset(ring_buffer, aux_pages); +static int koffset(ring_buffer, aux_nr_pages); +static int koffset(ring_buffer, aux_priv); + +static int koffset(etm_event_data, snk_config); + +static int koffset(cs_buffers, cur); +static int koffset(cs_buffers, offset); +static int koffset(cs_buffers, data_size); + +static int koffset(coresight_device, dev); +static int koffset(coresight_device, type); +static int koffset(coresight_device, subtype); + +static int koffset(device, parent); +static int koffset(device, driver_data); + +static int koffset(etmv4_drvdata, config); +static int koffset(etmv4_drvdata, trcid); + +static int koffset(etmv4_config, cfg); +static int koffset(etmv4_config, idr0); +static int koffset(etmv4_config, idr1); +static int koffset(etmv4_config, idr2); +static int koffset(etmv4_config, idr8); + +/* + * Thanks for Intel PT dump code ptdump.c giving good example for perf + * ring buffer dump. In this file the most perf ring buffer dump code + * reuses Intel PT dump code with minor changes for checking the last + * writing point of ring buffer; it supports to check if wrap around or + * not and copy trace data from perf ring buffer and save into a file. + */ +static inline int is_zero_page(ulong page, int offset) +{ + ulong read_addr = page + offset; + ulong read_size = PAGESIZE() - offset; + char *buf = malloc(PAGESIZE()); + int i; + + if (buf == NULL) { + fprintf(fp, "malloc failed\n"); + return FALSE; + } + + memset(buf, 0, PAGESIZE()); + dbgprintf(fp, "zero page chk: 0x%016lx, %lu\n", read_addr, read_size); + readmem(read_addr, KVADDR, buf, read_size, "zero page check", + FAULT_ON_ERROR); + + for (i = 0; i < PAGESIZE() - offset; i++) { + if (buf[i]) { + free(buf); + return FALSE; + } + } + + free(buf); + return TRUE; +} + +int check_wrap_around(int cpu) +{ + struct arm_cs_info *cs_info_ptr = arm_cs_info_list + cpu; + int wrapped = 0, i, page_idx; + ulong offset, mask, page; + + mask = (((ulong)1)<<PAGESHIFT()) - 1; + offset = cs_info_ptr->curr_buf_off & mask; + page_idx = cs_info_ptr->curr_buf_idx + + (cs_info_ptr->curr_buf_off >> PAGESHIFT()); + + dbgprintf(fp, "[%d] buf: mask=0x%lx\n", cpu, mask); + dbgprintf(fp, "[%d] buf: offset=0x%lx\n", cpu, offset); + dbgprintf(fp, "[%d] buf: page_idx=%d\n", cpu, page_idx); + + for (i=page_idx; i<cs_info_ptr->aux_nr_pages; i++) { + page = cs_info_ptr->buffer_ptr[i]; + + if (!is_zero_page(page, offset)) { + wrapped = 1; + break; + } + + offset = 0; + } + + return wrapped; +} + +int write_buffer_wrapped(int cpu, FILE *out_fp) +{ + struct arm_cs_info *cs_info_ptr = arm_cs_info_list + cpu; + int start_idx, idx, len, ret; + ulong mask, offset, page; + char *buf = malloc(PAGESIZE()); + + if (buf == NULL) { + fprintf(fp, "malloc failed\n"); + return FALSE; + } + + mask = (((ulong)1)<<PAGESHIFT()) - 1; + offset = cs_info_ptr->curr_buf_off & mask; + + start_idx = cs_info_ptr->curr_buf_idx + + (cs_info_ptr->curr_buf_off >> PAGESHIFT()); + + for (idx = start_idx; idx<cs_info_ptr->aux_nr_pages; idx++) { + page = cs_info_ptr->buffer_ptr[idx]; + len = PAGESIZE() - offset; + + readmem(page + offset, KVADDR, buf, len, "read page for write", + FAULT_ON_ERROR); + + dbgprintf(fp, "[%d] R/W1 buff: p=0x%lx, i=%d, o=%lu, l=%d\n", + cpu, page + offset, idx, offset, len); + + ret = fwrite(buf, len, 1, out_fp); + if (!ret) { + fprintf(fp, "[%d] Cannot write file\n", cpu); + free(buf); + return FALSE; + } + + offset = 0; + } + + for (idx = 0; idx < start_idx; idx++) { + page = cs_info_ptr->buffer_ptr[idx]; + len = PAGESIZE() - offset; + + readmem(page + offset, KVADDR, buf, len, "read page for write", + FAULT_ON_ERROR); + + dbgprintf(fp, "[%d] R/W2 buff: p=0x%lx, i=%d, o=%lu, l=%d\n", + cpu, page + offset, idx, offset, len); + + ret = fwrite(buf, len, 1, out_fp); + if (!ret) { + fprintf(fp, "[%d] Cannot write file\n", cpu); + free(buf); + return FALSE; + } + } + + idx = start_idx; + page = cs_info_ptr->buffer_ptr[idx]; + offset = cs_info_ptr->curr_buf_off & mask; + len = offset; + + if (len) { + readmem(page, KVADDR, buf, len, "read page for write", + FAULT_ON_ERROR); + + dbgprintf(fp, "[%d] R/W3 buff: p=0x%lx, i=%d, o=%lu, l=%d\n", cpu, + page, idx, offset, len); + + ret = fwrite(buf, len, 1, out_fp); + if (!ret) { + fprintf(fp, "[%d] Cannot write file\n", cpu); + free(buf); + return FALSE; + } + } + + free(buf); + return TRUE; +} + +int write_buffer_nowrapped(int cpu, FILE *out_fp) +{ + struct arm_cs_info *cs_info_ptr = arm_cs_info_list + cpu; + int last_idx, idx, len, ret; + ulong mask, page; + char *buf = malloc(PAGESIZE()); + + if (buf == NULL) { + fprintf(fp, "malloc failed\n"); + return FALSE; + } + + mask = (((ulong)1)<<PAGESHIFT()) - 1; + last_idx = cs_info_ptr->curr_buf_idx + + (cs_info_ptr->curr_buf_off >> PAGESHIFT()); + + for (idx = 0; idx < last_idx; idx++) { + page = cs_info_ptr->buffer_ptr[idx]; + len = PAGESIZE(); + + readmem(page, KVADDR, buf, len, "read page for write", + FAULT_ON_ERROR); + + dbgprintf(fp, "[%d] R/W1 buff: p=0x%lx, i=%d, o=%lu, l=%d\n", + cpu, page, idx, (ulong)0, len); + + ret = fwrite(buf, len, 1, out_fp); + if (!ret) { + fprintf(fp, "[%d] Cannot write file\n", cpu); + free(buf); + return FALSE; + } + } + + idx = last_idx; + page = cs_info_ptr->buffer_ptr[idx]; + len = cs_info_ptr->curr_buf_off & mask; + + readmem(page, KVADDR, buf, len, "read page for write", + FAULT_ON_ERROR); + + dbgprintf(fp, "[%d] R/W2 buff: p=0x%lx, i=%d, o=%lu, l=%d\n", cpu, + page, idx, (ulong)0, len); + + ret = fwrite(buf, len, 1, out_fp); + if (!ret) { + fprintf(fp, "[%d] Cannot write file\n", cpu); + free(buf); + return FALSE; + } + + free(buf); + return TRUE; +} + +int write_pt_log_buffer_cpu(int cpu, char *fname) +{ + int wrapped, ret; + FILE *out_fp; + + wrapped = check_wrap_around(cpu); + + if ((out_fp = fopen(fname, "w")) == NULL) { + fprintf(fp, "[%d] Cannot open file: %s\n", cpu, fname); + return FALSE; + } + dbgprintf(fp, "[%d] Open file: %s\n", cpu, fname); + + /* + * Write buffer to file + * + * Case 1: Not wrapped around + * + * start end + * | | + * v v + * +------+ +------+ +------+ +------+ + * |buffer| |buffer| ... |buffer| |buffer| + * +------+ +------+ +------+ +------+ + * + * In this case, just write data between 'start' and 'end' + * + * Case 2: Wrapped around + * + * end start + * | | + * v v + * +------+ +------+ +------+ +------+ + * |buffer| |buffer| ... |buffer| |buffer| + * +------+ +------+ +------+ +------+ + * + * In this case, at first write data between 'start' and end of last + * buffer, and then write data between beginning of first buffer and + * 'end'. + */ + if (wrapped) { + dbgprintf(fp, "[%d] wrap around: true\n", cpu); + ret = write_buffer_wrapped(cpu, out_fp); + } else { + dbgprintf(fp, "[%d] wrap around: false\n", cpu); + ret = write_buffer_nowrapped(cpu, out_fp); + } + + fclose(out_fp); + return ret; +} + +static int arm_cs_save_perf_ring_buffer(int cpu) +{ + char trace_file[sizeof("cstrace.9999999.bin")]; + ulong struct_ctx_handle; + ulong struct_ring_buffer; + ulong aux_pages, aux_priv; + ulong struct_cs_buffers; + uint cur; + ulong offset, data_size; + int i, aux_nr_pages, buf_len; + struct arm_cs_info *cs_info_ptr = arm_cs_info_list + cpu; + + /* Get pointer to struct ctx_handle for etm perf */ + if (!symbol_exists("ctx_handle")) { + fprintf(fp, "[CPU%d] symbol not found: pt_ctx\n", cpu); + return FALSE; + } + + struct_ctx_handle = symbol_value("ctx_handle") + kt->__per_cpu_offset[cpu]; + dbgprintf(fp, "struct_ctx_handle 0x%lx\n", struct_ctx_handle); + + read_value(struct_ring_buffer, struct_ctx_handle, + perf_output_handle, rb); + dbgprintf(fp, "struct_ring_buffer 0x%lx\n", struct_ring_buffer); + + if (!struct_ring_buffer) { + fprintf(fp, "No ring buffer\n"); + return FALSE; + } + + /* symbol access check */ + if (STRUCT_EXISTS("ring_buffer") && + !MEMBER_EXISTS("ring_buffer", "aux_pages")) { + fprintf(fp, "[CPU%d] invalid ring_buffer\n", cpu); + return FALSE; + } + + /* array of struct pages for pt buffer */ + read_value(aux_pages, struct_ring_buffer, ring_buffer, aux_pages); + + /* number of pages */ + read_value(aux_nr_pages, struct_ring_buffer, ring_buffer, aux_nr_pages); + + /* private data (struct etm_event_data) */ + read_value(aux_priv, struct_ring_buffer, ring_buffer, aux_priv); + + if (!aux_nr_pages) { + fprintf(fp, "No aux pages\n"); + return FALSE; + } + + cs_info_ptr->aux_pages = aux_pages; + cs_info_ptr->aux_nr_pages = aux_nr_pages; + cs_info_ptr->etm_event_data = aux_priv; + + dbgprintf(fp, "[CPU%d] rb.aux_pages=0x%016lx\n", cpu, aux_pages); + dbgprintf(fp, "[CPU%d] rb.aux_nr_pages=0x%d\n", cpu, aux_nr_pages); + dbgprintf(fp, "[CPU%d] rb.aux_priv=0x%016lx\n", cpu, aux_priv); + + /* Get address of pt buffer */ + buf_len = sizeof(void*)*aux_nr_pages; + cs_info_ptr->buffer_ptr = (ulong *)malloc(buf_len); + if (cs_info_ptr->buffer_ptr == NULL) { + fprintf(fp, "malloc failed\n"); + return FALSE; + } + memset(cs_info_ptr->buffer_ptr, 0, buf_len); + + for (i = 0; i < aux_nr_pages; i++) { + ulong pgaddr = aux_pages + i*sizeof(void*); + ulong page; + + if (!readmem(pgaddr, KVADDR, &page, sizeof(ulong), + "struct page", FAULT_ON_ERROR)) + continue; + + cs_info_ptr->buffer_ptr[i] = page; + + if (!i) + dbgprintf(fp, "[CPU%d] Dump aux pages\n", cpu); + dbgprintf(fp, " %d: 0x%016lx\n", i, page); + } + + read_value(struct_cs_buffers, cs_info_ptr->etm_event_data, + etm_event_data, snk_config); + + dbgprintf(fp, "struct_cs_buffers:0x%016lx\n", struct_cs_buffers); + + read_value(cur, struct_cs_buffers, cs_buffers, cur); + read_value(offset, struct_cs_buffers, cs_buffers, offset); + read_value(data_size, struct_cs_buffers, cs_buffers, data_size); + + cs_info_ptr->curr_buf_idx = cur; + cs_info_ptr->curr_buf_off = offset; + cs_info_ptr->curr_data_sz = data_size; + dbgprintf(fp, "[CPU%d] current bufidx=%d\n", cpu, cur); + dbgprintf(fp, "[CPU%d] current buf offset=%ld\n", cpu, offset); + dbgprintf(fp, "[CPU%d] current data size=%ld\n", cpu, data_size); + + for (i = 0; i < cpu; i++) { + struct arm_cs_info *ptr = arm_cs_info_list + i; + + if (ptr->aux_pages == cs_info_ptr->aux_pages) { + fprintf(fp, "[CPU%d] skip duplicate buffer with [%d]\n", + cpu, i); + cs_info_ptr->mode = CS_MODE_PERF; + return TRUE; + } + } + + sprintf(trace_file, "cstrace.%d.bin", cpu); + + if (write_pt_log_buffer_cpu(cpu, trace_file)) + fprintf(fp, "[CPU%d] buffer dump: %s\n", cpu, trace_file); + + cs_info_ptr->mode = CS_MODE_PERF; + + return TRUE; +} + +static int arm_cs_save_tracedata(void) +{ + int online_cpus, cpu; + int ret; + + dbgprintf(fp, "Extract raw trace data...\n"); + + online_cpus = get_cpus_online(); + switch (protocol) { + case OCSD_PROTOCOL_ETMV4I: + for (cpu = 0; cpu < online_cpus; cpu++) { + /* Firstly try perf ring buffer */ + ret = arm_cs_save_perf_ring_buffer(cpu); + if (ret) + continue; + + /* Return for failure */ + return ret; + } + break; + default: + /* Protocol isn't supported yet */ + return FALSE; + } + + return TRUE; +} + +static ulong arm_cs_get_perf_source_handler(int cpu) +{ + ulong struct_csdev, struct_csdev_ptr; + + /* Get pointer to struct ctx_handle for etm perf */ + if (!symbol_exists("csdev_src")) { + fprintf(fp, "[CPU0] symbol not found: pt_ctx\n"); + return 0; + } + + struct_csdev_ptr = symbol_value("csdev_src") + kt->__per_cpu_offset[cpu]; + dbgprintf(fp, "struct_csdev_ptr=0x%lx\n", struct_csdev_ptr); + + readmem(struct_csdev_ptr, KVADDR, &struct_csdev, + sizeof(struct_csdev), "read csdev", RETURN_ON_ERROR); + dbgprintf(fp,"struct_csdev=0x%lx\n", struct_csdev); + + return struct_csdev; +} + +static ulong arm_cs_get_drvdata_handle(ulong struct_csdev) +{ + ulong struct_dev, struct_parent_dev; + ulong struct_drvdata; + + struct_dev = struct_csdev + koffset(coresight_device, dev); + dbgprintf(fp,"struct_dev=0x%lx\n", struct_dev); + + read_value(struct_parent_dev, struct_dev, device, parent); + dbgprintf(fp,"struct_parent_dev=0x%lx\n", struct_parent_dev); + + read_value(struct_drvdata, struct_parent_dev, device, driver_data); + dbgprintf(fp,"struct_drvdata=0x%lx\n", struct_drvdata); + + return struct_drvdata; +} + +static ocsd_err_t arm_cs_create_etmv4_decoder(dcd_tree_handle_t dcd_tree_h, + int cpu) +{ + ulong csdev, etmv4_driverdata, etmv4_config; + ocsd_etmv4_cfg trace_config; + char trcid; + struct arm_cs_info *cs_info_ptr = arm_cs_info_list + cpu; + + switch (cs_info_ptr->mode) { + case CS_MODE_PERF: + csdev = arm_cs_get_perf_source_handler(cpu); + break; + default: + csdev = 0; + break; + } + + if (!csdev) { + fprintf(fp, "Failed to read csdev device handle\n"); + return OCSD_ERR_FAIL; + } + + etmv4_driverdata = arm_cs_get_drvdata_handle(csdev); + if (!etmv4_driverdata) { + fprintf(fp, "Failed to read etmv4 drvdata\n"); + return OCSD_ERR_FAIL; + } + + etmv4_config = etmv4_driverdata + koffset(etmv4_drvdata, config); + dbgprintf(fp,"etmv4_config=0x%lx\n", etmv4_config); + + read_value(trcid, etmv4_driverdata, etmv4_drvdata, trcid); + + /* + * Populate the ETMv4 configuration structure with hard coded + * values from snapshot .ini files. + */ + trace_config.arch_ver = ARCH_V8; + trace_config.core_prof = profile_CortexA; + trace_config.reg_traceidr = trcid; + trace_config.reg_idr9 = 0x0; + trace_config.reg_idr10 = 0x0; + trace_config.reg_idr11 = 0x0; + trace_config.reg_idr12 = 0x0; + trace_config.reg_idr13 = 0x0; + + read_value(trace_config.reg_configr, etmv4_config, etmv4_config, cfg); + read_value(trace_config.reg_idr0, etmv4_config, etmv4_config, idr0); + read_value(trace_config.reg_idr1, etmv4_config, etmv4_config, idr1); + read_value(trace_config.reg_idr2, etmv4_config, etmv4_config, idr2); + read_value(trace_config.reg_idr8, etmv4_config, etmv4_config, idr8); + + dbgprintf(fp, "reg_configr=0x%x\n", trace_config.reg_configr); + dbgprintf(fp, "reg_traceidr=0x%x\n", trace_config.reg_traceidr); + dbgprintf(fp, "reg_idr0=0x%x\n", trace_config.reg_idr0); + dbgprintf(fp, "reg_idr1=0x%x\n", trace_config.reg_idr1); + dbgprintf(fp, "reg_idr2=0x%x\n", trace_config.reg_idr2); + dbgprintf(fp, "reg_idr8=0x%x\n", trace_config.reg_idr8); + dbgprintf(fp, "reg_idr9=0x%x\n", trace_config.reg_idr9); + dbgprintf(fp, "reg_idr10=0x%x\n", trace_config.reg_idr10); + dbgprintf(fp, "reg_idr11=0x%x\n", trace_config.reg_idr11); + dbgprintf(fp, "reg_idr12=0x%x\n", trace_config.reg_idr12); + dbgprintf(fp, "reg_idr13=0x%x\n", trace_config.reg_idr13); + + /* + * create an ETMV4 decoder - no context needed as we have a + * single stream to a single handler. + */ + return arm_cs_create_generic_decoder(dcd_tree_h, + OCSD_BUILTIN_DCD_ETMV4I, + (void *)&trace_config, 0); +} + +/* Create a decoder according to options */ +static ocsd_err_t arm_cs_create_decoder(dcd_tree_handle_t dcd_tree_h) +{ + ocsd_err_t err; + int online_cpus, i; + + online_cpus = get_cpus_online(); + + switch (protocol) { + case OCSD_PROTOCOL_ETMV4I: + for (i = 0; i < online_cpus; i++) { + err = arm_cs_create_etmv4_decoder(dcd_tree_h, i); + if (err != OCSD_OK) + return err; + } + break; + default: + err = OCSD_ERR_NO_PROTOCOL; + break; + } + + return err; +} + +/* Process buffer until done or error */ +static ocsd_err_t arm_cs_process_data_block(dcd_tree_handle_t dcd_tree_h, + int block_index, + uint8_t *p_block, + const uint32_t block_size) +{ + ocsd_err_t ret = OCSD_OK; + ocsd_datapath_resp_t dp_ret = OCSD_RESP_CONT; + uint32_t total_sz = 0; + uint32_t sz = 0; + + while (total_sz < block_size) { + + if (OCSD_DATA_RESP_IS_CONT(dp_ret)) { + + dp_ret = ocsd_dt_process_data(dcd_tree_h, + OCSD_OP_DATA, + block_index + total_sz, + block_size - total_sz, + p_block+ total_sz, + &sz); + total_sz += sz; + + } else if (OCSD_DATA_RESP_IS_WAIT(dp_ret)) { + + dp_ret = ocsd_dt_process_data(dcd_tree_h, + OCSD_OP_FLUSH, + 0, 0, NULL, NULL); + } else { + ret = OCSD_ERR_DATA_DECODE_FATAL; + break; + } + } + + return ret; +} + +static int arm_cs_process_trace_data(FILE *pf) +{ + ocsd_err_t ret = OCSD_OK; + dcd_tree_handle_t dcdtree_handle = C_API_INVALID_TREE_HANDLE; + uint8_t data_buffer[INPUT_BLOCK_SIZE]; + ocsd_trc_index_t index = 0; + size_t data_read; + + /* + * Create a decode tree for this source data. Source data is frame + * formatted, memory aligned from an ETR (no frame syncs) so create + * tree accordingly. + */ + dcdtree_handle = ocsd_create_dcd_tree(OCSD_TRC_SRC_FRAME_FORMATTED, + OCSD_DFRMTR_FRAME_MEM_ALIGN | + OCSD_DFRMTR_RESET_ON_4X_FSYNC); + if (dcdtree_handle == C_API_INVALID_TREE_HANDLE) { + fprintf(fp, "Failed to create dcd tree\n"); + return FALSE; + } + + ret = arm_cs_create_decoder(dcdtree_handle); + if (ret != OCSD_OK) { + fprintf(fp, "Failed to create decoder\n"); + return FALSE; + } + + ret = arm_cs_create_test_memory_acc(dcdtree_handle); + if (ret != OCSD_OK) { + fprintf(fp, "Failed to create memory accessing\n"); + return FALSE; + } + + ocsd_tl_log_mapped_mem_ranges(dcdtree_handle); + + ret = ocsd_dt_set_gen_elem_outfn(dcdtree_handle, + arm_cs_gen_trace_elem_print, 0); + if (ret != OCSD_OK) { + fprintf(fp, "Failed to set elem outfn\n"); + return FALSE; + } + + /* Now push the trace data through the packet processor */ + while (!feof(pf)) { + + /* Read from file */ + data_read = fread(data_buffer, 1, INPUT_BLOCK_SIZE, pf); + if (data_read <= 0) { + if (ferror(pf)) + ret = OCSD_ERR_FILE_ERROR; + break; + } + + /* + * Process a block of data - any packets from the trace stream + * we have configured will appear at the callback. + */ + ret = arm_cs_process_data_block(dcdtree_handle, index, + data_buffer, data_read); + if (ret != OCSD_OK) + break; + + index += data_read; + } + + if (ret != OCSD_OK) { + fprintf(fp, "Failed to process data block.\n"); + return FALSE; + } + + ocsd_dt_process_data(dcdtree_handle, OCSD_OP_EOT, 0, 0, NULL, NULL); + + /* Shut down the mem acc CB if in use. */ + arm_cs_destroy_mem_acc_cb(dcdtree_handle); + + /* + * Dispose of the decode tree - which will dispose of any packet + * processors we created. + */ + ocsd_destroy_dcd_tree(dcdtree_handle); + return TRUE; +} + +static int arm_cs_decode_etmv4_trace_data(int cpu) +{ + FILE *trace_data; + char trace_file[sizeof("cstrace.9999999.bin")]; + char log_file[sizeof("cstrace.9999999.log")]; + int ret; + char message[512]; + + /* Trace file cstrace.X.bin, X is CPU number */ + sprintf(trace_file, "cstrace.%d.bin", cpu); + + trace_data = fopen(trace_file, "rb"); + if (!trace_data) { + fprintf(fp, "Trace file %s doesn't exist\n", trace_file); + return TRUE; + } + + /* + * Set up the logging in the library - enable the error logger, + * with an output printer. + */ + ret = ocsd_def_errlog_init(OCSD_ERR_SEV_INFO, 1); + if (ret != 0) + return FALSE; + + /* Log file cstrace.X.bin, X is CPU number */ + sprintf(log_file, "cstrace.%d.log", cpu); + + /* Set up the output - to file and stdout, set custom logfile name */ + ret = ocsd_def_errlog_config_output(C_API_MSGLOGOUT_FLG_FILE | + C_API_MSGLOGOUT_FLG_STDOUT, + log_file); + + /* Print sign-on message in log */ + sprintf(message, "C-API packet print test\nLibrary Version %s\n\n", + ocsd_get_version_str()); + ocsd_def_errlog_msgout(message); + + /* Process the trace data */ + ret = arm_cs_process_trace_data(trace_data); + if (!ret) + fprintf(fp,"Failed to process trace data.\n"); + + /* Close the data file */ + fclose(trace_data); + return TRUE; +} + +static int arm_cs_decode_tracedata(void) +{ + int online_cpus, cpu; + int ret; + + dbgprintf(fp, "Decode raw trace data...\n"); + + online_cpus = get_cpus_online(); + switch (protocol) { + case OCSD_PROTOCOL_ETMV4I: + for (cpu = 0; cpu < online_cpus; cpu++) { + ret = arm_cs_decode_etmv4_trace_data(cpu); + if (!ret) + return ret; + } + break; + default: + /* Protocol isn't supported yet */ + return FALSE; + } + + return TRUE; +} + +static int arm_cs_dump_prepare(void) +{ + int list_len, online_cpus; + + init_offset(perf_output_handle, event); + init_offset(perf_output_handle, rb); + + init_offset(ring_buffer, aux_pages); + init_offset(ring_buffer, aux_nr_pages); + init_offset(ring_buffer, aux_priv); + + init_offset(etm_event_data, snk_config); + + init_offset(cs_buffers, cur); + init_offset(cs_buffers, offset); + init_offset(cs_buffers, data_size); + + init_offset(coresight_device, dev); + init_offset(coresight_device, type); + init_offset(coresight_device, subtype); + + init_offset(device, parent); + init_offset(device, driver_data); + + init_offset(etmv4_drvdata, config); + init_offset(etmv4_drvdata, trcid); + + init_offset(etmv4_config, cfg); + init_offset(etmv4_config, idr0); + init_offset(etmv4_config, idr1); + init_offset(etmv4_config, idr2); + init_offset(etmv4_config, idr8); + + online_cpus = get_cpus_online(); + list_len = sizeof(struct arm_cs_info) * online_cpus; + arm_cs_info_list = malloc(list_len); + if (arm_cs_info_list == NULL) { + fprintf(fp, "Cannot alloc arm_cs_info_list\n"); + return FALSE; + } + memset(arm_cs_info_list, 0, list_len); + + return TRUE; +} + +int arm_cs_main(void) +{ + int ret; + + ret = arm_cs_save_tracedata(); + if (!ret) + return ret; + + ret = arm_cs_decode_tracedata(); + if (!ret) + return ret; + + return TRUE; +} + +void arm_cs_dump_cmd(void) +{ + char* outdir = NULL; + mode_t mode = S_IRUSR | S_IWUSR | S_IXUSR | + S_IRGRP | S_IXGRP | + S_IROTH | S_IXOTH; /* 0755 */ + int c, ret; + + /* Parse command line option */ + while ((c = getopt(argcnt, args, "t:o:")) != EOF) { + switch(c) { + case 't': + if (!strcmp(optarg, "etmv4")) + protocol = OCSD_PROTOCOL_ETMV4I; + else + argerrs++; + break; + case 'o': + outdir = optarg; + break; + default: + argerrs++; + break; + } + } + + if (argerrs || !outdir) + cmd_usage(pc->curcmd, SYNOPSIS); + + ocsd_def_errlog_init(OCSD_ERR_SEV_INFO, 1); + + if (!arm_cs_dump_prepare()) + return; + + if ((ret = mkdir(outdir, mode))) { + fprintf(fp, "Cannot create directory %s: %d\n", outdir, ret); + return; + } + + if ((ret = chdir(outdir))) { + fprintf(fp, "Cannot chdir %s: %d\n", outdir, ret); + return; + } + + arm_cs_main(); + + chdir(".."); + return; +} + +static char *arm_cs_dump_help[] = { + "arm_cs_dump", + "Dump log buffer of Coresight Trace", + "-o <output-dir>", + " This command extracts coresight trace to the output directory", + NULL +}; + +static struct command_table_entry command_table[] = { + { "arm_cs_dump", arm_cs_dump_cmd, arm_cs_dump_help, 0}, + { NULL }, +}; + +void __attribute__((constructor)) +arm_cs_dump_init(void) +{ + register_extension(command_table); +} + +void __attribute__((destructor)) +arm_cs_dump_fini(void) { } diff --git a/extensions/arm_cs_dump.mk b/extensions/arm_cs_dump.mk new file mode 100644 index 0000000..afe96dc --- /dev/null +++ b/extensions/arm_cs_dump.mk @@ -0,0 +1,39 @@ +# +# Copyright (C) 2018 Linaro Ltd. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(shell /bin/ls /usr/include/crash/defs.h 2>/dev/null), /usr/include/crash/defs.h) + INCDIR=/usr/include/crash +endif +ifeq ($(shell /bin/ls ./defs.h 2> /dev/null), ./defs.h) + INCDIR=. +endif +ifeq ($(shell /bin/ls ../defs.h 2> /dev/null), ../defs.h) + INCDIR=.. +endif + +SUBDIR=arm_cs_dump +TARGET_CFILES=arm_cs_dump.c $(SUBDIR)/arm_cs_decoder.c + +COMMON_CFLAGS=-Wall -I$(INCDIR) -fPIC -D$(TARGET) + +all: arm_cs_dump.so + +arm_cs_dump.so: $(TARGET_CFILES) $(INCDIR)/defs.h + gcc $(RPM_OPT_FLAGS) $(CFLAGS) $(TARGET_CFLAGS) $(COMMON_CFLAGS) -nostartfiles -shared -rdynamic -o $@ $(TARGET_CFILES) -lelf -lopencsd -lopencsd_c_api + +debug: COMMON_CFLAGS+=-DDEBUG +debug: all + +clean: + rm -f *.so *.o diff --git a/extensions/arm_cs_dump/arm_cs_decoder.c b/extensions/arm_cs_dump/arm_cs_decoder.c new file mode 100644 index 0000000..9281bc5 --- /dev/null +++ b/extensions/arm_cs_dump/arm_cs_decoder.c @@ -0,0 +1,319 @@ +/* + * Extension module to extract dump buffer of ARM Coresight Trace + * + * Copyright (C) 2017, 2018 Linaro Ltd + * Author: Leo Yan <leo.yan(a)linaro.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define _GNU_SOURCE +#include "defs.h" +#include <sys/file.h> +#include <sys/types.h> + +#include "arm_cs_decoder.h" + +#define INPUT_BLOCK_SIZE 1024 + +/* buffer to handle a packet string */ +#define PACKET_STR_LEN 1024 +static char packet_str[PACKET_STR_LEN]; + +test_op_t op_type = TEST_PKT_DECODE; +ocsd_trace_protocol_t protocol = OCSD_PROTOCOL_ETMV4I; + +uint32_t arm_cs_mem_acc_cb(const void *p_context, + const ocsd_vaddr_t address, + const ocsd_mem_space_acc_t mem_space, + const uint32_t size, + uint8_t *buffer) +{ + return 0; +} + +/* + * Create the memory accessor using the callback function + * and attach to decode tree + */ +ocsd_err_t arm_cs_create_mem_acc_cb(dcd_tree_handle_t dcd_tree_h) +{ + ocsd_err_t err; + + err = ocsd_dt_add_callback_mem_acc(dcd_tree_h, + 0x0L, ((uint64_t) -1L), + OCSD_MEM_SPACE_ANY, + &arm_cs_mem_acc_cb, 0); + return err; +} + +/* Remove the callback memory accessor from decode tree */ +void arm_cs_destroy_mem_acc_cb(dcd_tree_handle_t dcd_tree_h) +{ + ocsd_dt_remove_mem_acc(dcd_tree_h, 0x0L, OCSD_MEM_SPACE_ANY); +} + +/* + * Create and attach the memory accessor according to + * required test parameters. + */ +ocsd_err_t arm_cs_create_test_memory_acc(dcd_tree_handle_t handle) +{ + ocsd_err_t ret; + + /* + * Decide how to handle the file - test the normal memory accessor + * (contiguous binary file), a callback accessor or a multi-region + * file (e.g. similar to using the code region in a .so). + * + * The same memory dump file is used in each case, we just present + * it differently to test the API functions. + */ + + ret = arm_cs_create_mem_acc_cb(handle); + return ret; +} + +/* + * Callback function to process the packets in the packet processor + * output stream - simply print them out in this case to the + * library message/error logger. + */ +ocsd_datapath_resp_t arm_cs_packet_handler(void *context, + const ocsd_datapath_op_t op, + const ocsd_trc_index_t index_sop, + const void *p_packet_in) +{ + ocsd_err_t ret; + int offset = 0; + + switch (op) { + case OCSD_OP_DATA: + sprintf(packet_str, "Idx:%" OCSD_TRC_IDX_STR "; ", index_sop); + offset = strlen(packet_str); + + /* + * Got a packet - convert to string and use the libraries' + * message output to print to file and stdoout since the + * test always prints a single ID, we know the protocol type. + */ + ret = ocsd_pkt_str(protocol, p_packet_in, packet_str + offset, + PACKET_STR_LEN - offset); + if (ret != OCSD_OK) + return OCSD_RESP_FATAL_INVALID_PARAM; + + /* Add in <CR> */ + if (strlen(packet_str) == PACKET_STR_LEN - 1) /* max length */ + packet_str[PACKET_STR_LEN-2] = '\n'; + else + strcat(packet_str,"\n"); + + /* Print it using the library output logger. */ + ocsd_def_errlog_msgout(packet_str); + break; + + case OCSD_OP_EOT: + sprintf(packet_str, "*** END OF TRACE ***\n"); + ocsd_def_errlog_msgout(packet_str); + break; + + default: + break; + } + + return OCSD_RESP_CONT; +} + +/* + * Print an array of hex data - used by the packet monitor + * to print hex data from packet. + */ +int arm_cs_print_data_array(const uint8_t *p_array, + const int array_size, + char *buffer, int size) +{ + int printed = 0; + int idx; + + buffer[0] = 0; + + if (size > 9) { + /* set up the header */ + strcat(buffer,"[ "); + printed += 2; + + for (idx = 0; idx < array_size; idx++) { + sprintf(buffer + printed,"0x%02X ", p_array[idx]); + printed += 5; + if ((printed + 5) > size) + break; + } + + strcat(buffer, "];"); + printed += 2; + + } else if (size >= 4) { + sprintf(buffer,"[];"); + printed += 3; + } + + return printed; +} + +/* + * Callback function to process packets and packet data from + * the monitor output of the packet processor. Again print + * them to the library error logger. + */ +void arm_cs_packet_monitor(void *context, const ocsd_datapath_op_t op, + const ocsd_trc_index_t index_sop, + const void *p_packet_in, const uint32_t size, + const uint8_t *p_data) +{ + int offset = 0; + ocsd_err_t ret; + + switch(op) { + case OCSD_OP_DATA: + sprintf(packet_str, "Idx:%" OCSD_TRC_IDX_STR ";", index_sop); + offset = strlen(packet_str); + offset += arm_cs_print_data_array(p_data, size, + packet_str + offset, + PACKET_STR_LEN - offset); + + /* + * Got a packet - convert to string and use the libraries + * message output to print to file and stdoout. + */ + ret = ocsd_pkt_str(protocol, p_packet_in, + packet_str + offset, + PACKET_STR_LEN - offset); + if (ret != OCSD_OK) { + fprintf(fp,"Failed to get packet string.\n"); + return; + } + + /* Add in <CR> */ + if (strlen(packet_str) == PACKET_STR_LEN - 1) /* max length */ + packet_str[PACKET_STR_LEN-2] = '\n'; + else + strcat(packet_str,"\n"); + + /* Print it using the library output logger. */ + ocsd_def_errlog_msgout(packet_str); + break; + + case OCSD_OP_EOT: + sprintf(packet_str, "*** END OF TRACE ***\n"); + ocsd_def_errlog_msgout(packet_str); + break; + + default: + break; + } + + return; +} + +/* Output generic trace elements */ +ocsd_datapath_resp_t arm_cs_gen_trace_elem_print(const void *p_context, + const ocsd_trc_index_t index_sop, + const uint8_t trc_chan_id, + const ocsd_generic_trace_elem *elem) +{ + int offset = 0; + ocsd_err_t ret; + + sprintf(packet_str, "Idx:%" OCSD_TRC_IDX_STR "; TrcID:0x%02X; ", + index_sop, trc_chan_id); + + offset = strlen(packet_str); + + ret = ocsd_gen_elem_str(elem, packet_str + offset, + PACKET_STR_LEN - offset); + if (ret != OCSD_OK) { + strcat(packet_str,"Unable to create element string\n"); + } else { + /* Add in <CR> */ + if (strlen(packet_str) == PACKET_STR_LEN - 1) /* max length */ + packet_str[PACKET_STR_LEN-2] = '\n'; + else + strcat(packet_str,"\n"); + } + + /* Print it using the library output logger. */ + ocsd_def_errlog_msgout(packet_str); + + return OCSD_RESP_CONT; +} + +ocsd_err_t arm_cs_create_generic_decoder(dcd_tree_handle_t handle, + const char *p_name, + const void *p_cfg, + const void *p_context) +{ + ocsd_err_t ret = OCSD_OK; + uint8_t csid = 0; + + if (op_type == TEST_PKT_PRINT) { + /* + * Create a packet processor on the decode tree for the + * configuration we have. We need to supply the configuration. + */ + ret = ocsd_dt_create_decoder(handle, p_name, + OCSD_CREATE_FLG_PACKET_PROC, + p_cfg, &csid); + if (ret != OCSD_OK) { + fprintf(fp,"Failed to create decoder for PKT_PRINT\n"); + return ret; + } + + ret = ocsd_dt_attach_packet_callback(handle, csid, + OCSD_C_API_CB_PKT_SINK, + &arm_cs_packet_handler, + p_context); + if (ret != OCSD_OK) { + fprintf(fp,"Failed to attach CB for PKT_PRINT\n"); + ocsd_dt_remove_decoder(handle, csid); + return ret; + } + } else { + /* + * Full decode - need decoder, and memory dump; + * create the packet decoder and packet processor pair + * from the supplied name. + */ + ret = ocsd_dt_create_decoder(handle, p_name, + OCSD_CREATE_FLG_FULL_DECODER, + p_cfg, &csid); + if (ret != OCSD_OK) { + fprintf(fp,"Failed to create decoder for PKT_DECODE{ONLY}\n"); + return ret; + } + + if (op_type == TEST_PKT_DECODE) { + /* + * Print the packets as well as the decode - use the + * packet processors monitor output this time, as the + * main output is attached to the packet decoder. + */ + ret = ocsd_dt_attach_packet_callback(handle, csid, + OCSD_C_API_CB_PKT_MON, + arm_cs_packet_monitor, p_context); + if (ret != OCSD_OK) { + fprintf(fp,"Failed to attach CB for printing packet\n"); + return ret; + } + } + } + + return OCSD_OK; +} diff --git a/extensions/arm_cs_dump/arm_cs_decoder.h b/extensions/arm_cs_dump/arm_cs_decoder.h new file mode 100644 index 0000000..d8202b4 --- /dev/null +++ b/extensions/arm_cs_dump/arm_cs_decoder.h @@ -0,0 +1,40 @@ +#include <opencsd/c_api/opencsd_c_api.h> + +typedef enum test_op { + TEST_PKT_PRINT, /* Process discrete packets and print */ + TEST_PKT_DECODE, /* Decode and generic output */ + TEST_PKT_DECODEONLY /* Decode and output packets only */ +} test_op_t; + +extern test_op_t op_type; +extern ocsd_trace_protocol_t protocol; + +extern uint32_t arm_cs_mem_acc_cb(const void *p_context, + const ocsd_vaddr_t address, + const ocsd_mem_space_acc_t mem_space, + const uint32_t size, + uint8_t *buffer); +extern ocsd_err_t arm_cs_create_test_memory_acc(dcd_tree_handle_t handle); +extern ocsd_err_t arm_cs_create_mem_acc_cb(dcd_tree_handle_t dcd_tree_h); +extern void arm_cs_destroy_mem_acc_cb(dcd_tree_handle_t dcd_tree_h); +extern ocsd_datapath_resp_t arm_cs_packet_handler(void *context, + const ocsd_datapath_op_t op, + const ocsd_trc_index_t index_sop, + const void *p_packet_in); +extern int arm_cs_print_data_array(const uint8_t *p_array, + const int array_size, + char *buffer, int size); +extern void arm_cs_packet_monitor(void *context, + const ocsd_datapath_op_t op, + const ocsd_trc_index_t index_sop, + const void *p_packet_in, + const uint32_t size, + const uint8_t *p_data); +extern ocsd_datapath_resp_t arm_cs_gen_trace_elem_print(const void *p_context, + const ocsd_trc_index_t index_sop, + const uint8_t trc_chan_id, + const ocsd_generic_trace_elem *elem); +extern ocsd_err_t arm_cs_create_generic_decoder(dcd_tree_handle_t handle, + const char *p_name, + const void *p_cfg, + const void *p_context); -- 2.7.4

6 years, 9 months

[PATCH v2 00/14] coresight: Implement device claim protocol

by Suzuki K Poulose

Coresight architecture defines CLAIM tags for a device to negotiate control of the components (external agent vs self-hosted). Each device has a pair of registers (CLAIMSET & CLAIMCLR) for managing the CLAIM tags. However, the protocol for the CLAIM tags is IMPLEMENTATION DEFINED. PSCI has recommendations for the use of the CLAIM tags to negotiate controls for external agent vs self-hosted use, as defined in ARM DEN 0022D, Section "6.8.1 Debug and Trace save and restore". This series implements the recommended protocol by PSCI. There were two options for the implementation. 1) Have the claim/disclaim operations performed from the coresight generic driver - This doesn't work unfortunately for ETM devices as the need cross-CPU calls to access the CLAIM registers. Also, makes it complex for error recovery and reference counting. 2) Have the claim/disclaim operations performed from the device specific drivers. The disadvantage is that the calls are sprinkled in each driver, but this makes the operation much simpler. This series implements the method (2). The first part of the series prepares different drivers to handle errors from the lower layer and clean up the state. The second part of the series updates the existing drivers to claim/disclaim the devices as necessary. Tested with a hacked coresight driver which modifies the external claim tag via sysfs handle. Applies on coresight/next in Mathieu's tree. Changes since V1: - Handle errors is enabling path and disable only the components that were enabled in the iteration. - Fix build break on arm32 (etm3x) - Update commit description for "coresight: Add support for CLAIM tag protocol" Suzuki K Poulose (14): coresight: Handle failures in enabling a trace path coresight: tmc-etr: Refactor for handling errors coresight: tmc-etr: Handle errors enabling CATU coresight: tmc-etb/etf: Prepare to handle errors enabling coresight: etm4x: Add support for handling errors coresight: etm3: Add support for handling errors coresight: etb10: Handle errors enabling the device coresight: dynamic-replicator: Handle multiple connections coresight: Add support for CLAIM tag protocol coresight: etmx: Claim devices before use coresight: funnel: Claim devices before use coresight: catu: Claim device before use coresight: dynamic-replicator: Claim device for use coreisght: tmc: Claim device before use drivers/hwtracing/coresight/coresight-catu.c | 6 ++ .../coresight/coresight-dynamic-replicator.c | 79 ++++++++++---- drivers/hwtracing/coresight/coresight-etb10.c | 18 +++- drivers/hwtracing/coresight/coresight-etm3x.c | 56 +++++++--- drivers/hwtracing/coresight/coresight-etm4x.c | 51 ++++++--- drivers/hwtracing/coresight/coresight-funnel.c | 26 ++++- drivers/hwtracing/coresight/coresight-priv.h | 7 ++ drivers/hwtracing/coresight/coresight-tmc-etf.c | 95 +++++++++++------ drivers/hwtracing/coresight/coresight-tmc-etr.c | 80 +++++++++----- drivers/hwtracing/coresight/coresight.c | 118 +++++++++++++++++++-- include/linux/coresight.h | 20 ++++ 11 files changed, 434 insertions(+), 122 deletions(-) -- 2.7.4

6 years, 9 months

[PATCH v2 0/2] CoreSight: tmc-etf: Fixes for updating buffer

by Leo Yan

This patch series is to two fixing of updating ring buffer in tmc-etf driver. The first patch is to fix alignment setting for RRP; the second patch tries to fix discarding trace data issue caused by filling barrier packets in the same place, the patch keeps complete trace data with inserting extra barrier packets. This patch series has been rebased on CoreSight next branch: https://git.linaro.org/kernel/coresight.git/log/?h=next with latest commit 3733ca5a6578 ("coresight: tmc: Refactor loops in etb dump"). Changes from v1: * Rebased on CoreSight next branch (Sept 11th, 2018); * Added checking 'lost || to_read > handle->size' to set 'barrier_sz'. Leo Yan (2): coresight: tmc: Fix byte-address alignment for RRP coresight: tmc: Fix writing barrier packets for ring buffer drivers/hwtracing/coresight/coresight-tmc-etf.c | 41 +++++++++++++++++-------- 1 file changed, 29 insertions(+), 12 deletions(-) -- 2.7.4

6 years, 9 months

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