From: Tingwei Zhang <tingwei(a)codeaurora.org>
On some Qualcomm Technologies Inc. SoCs like SC7180, there
exists a hardware errata where the APSS (Application Processor
SubSystem)/CPU watchdog counter is stopped when ETM register
TRCPDCR.PU=1. Since the ETMs share the same power domain as
that of respective CPU cores, they are powered on when the
CPU core is powered on. So we can disable powering up of the
trace unit after checking for this errata via new property
called "qcom,tupwr-disable".
Signed-off-by: Tingwei Zhang <tingwei(a)codeaurora.org>
Co-developed-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org>
---
.../devicetree/bindings/arm/coresight.txt | 6 ++++
drivers/hwtracing/coresight/coresight-etm4x.c | 29 ++++++++++++-------
2 files changed, 25 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 846f6daae71b..d2030128fe46 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -108,6 +108,12 @@ its hardware characteristcs.
* arm,cp14: must be present if the system accesses ETM/PTM management
registers via co-processor 14.
+ * qcom,tupwr-disable: boolean. Indicates that trace unit power up can
+ be disabled on Qualcomm Technologies Inc. systems where ETMs are in
+ the same power domain as their CPU cores. This property is required
+ to identify such systems with hardware errata where the CPU watchdog
+ counter is stopped when TRCPDCR.PU=1.
+
* Optional property for TMC:
* arm,buffer-size: size of contiguous buffer space for TMC ETR
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index fb0f5f4f3a91..6886b44f6947 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -104,6 +104,11 @@ struct etm4_enable_arg {
int rc;
};
+static inline bool etm4_can_disable_tupwr(struct device *dev)
+{
+ return fwnode_property_present(dev_fwnode(dev), "qcom,tupwr-disable");
+}
+
static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
{
int i, rc;
@@ -196,12 +201,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
- /*
- * Request to keep the trace unit powered and also
- * emulation of powerdown
- */
- writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
- drvdata->base + TRCPDCR);
+ if (!etm4_can_disable_tupwr(etm_dev)) {
+ /*
+ * Request to keep the trace unit powered and also
+ * emulation of powerdown
+ */
+ writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
+ drvdata->base + TRCPDCR);
+ }
/* Enable the trace unit */
writel_relaxed(1, drvdata->base + TRCPRGCTLR);
@@ -476,10 +483,12 @@ static void etm4_disable_hw(void *info)
CS_UNLOCK(drvdata->base);
- /* power can be removed from the trace unit now */
- control = readl_relaxed(drvdata->base + TRCPDCR);
- control &= ~TRCPDCR_PU;
- writel_relaxed(control, drvdata->base + TRCPDCR);
+ if (!etm4_can_disable_tupwr(etm_dev)) {
+ /* power can be removed from the trace unit now */
+ control = readl_relaxed(drvdata->base + TRCPDCR);
+ control &= ~TRCPDCR_PU;
+ writel_relaxed(control, drvdata->base + TRCPDCR);
+ }
control = readl_relaxed(drvdata->base + TRCPRGCTLR);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
This series adds support to skip powering up of trace unit on systems
with an errata which stops CPU watchdog counter when power up bit is
set (TRCPDCR.PU = 1). Setting this bit is not required on Qualcomm
Technologies Inc. chipsets where this errata exists since the ETMs
are in the same power domain as their respective CPU cores.
Tingwei Zhang (2):
coresight: etm4x: Add support to skip trace unit power up
dt-bindings: arm: coresight: Add support to skip trace unit power up
.../devicetree/bindings/arm/coresight.txt | 7 +++++
drivers/hwtracing/coresight/coresight-etm4x.c | 27 ++++++++++++-------
drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++
3 files changed, 27 insertions(+), 10 deletions(-)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
Adds in power management for CPU bound CTI devices:
i) CPU Hotplug - registers a new notifier for CPU start and stop events.
ii) CPU idle PM event notifier to handle PM_ENTER, PM_ENTER_FAILED and
PM_EXIT events.
Tested with DB410c on coresight/next tree (Linux 5.7-rc1)
Changes since v2:
1) removed helper functions filtering on CONFIG_CPU_PM to call cpu_pm
fns directly.
2) add check for return value from cpuhp_remove_state_nocalls().
Changes since V1: (requested by Mathieu).
1) Split into separate patches for CPU pm and CPU hotplug handling.
2) Enable on hotplug has a specific function to enable the hardware,
while leaving the enable reference counts unchanged.
Mike Leach (2):
coresight: cti: Add CPU Hotplug handling to CTI driver.
coresight: cti: Add CPU idle pm notifer to CTI devices.
drivers/hwtracing/coresight/coresight-cti.c | 160 ++++++++++++++++++++
include/linux/cpuhotplug.h | 1 +
2 files changed, 161 insertions(+)
--
2.17.1
On some QCOM SoCs, replicators in Always-On domain loses its
context as soon as the clock is disabled. Currently as a part
of pm_runtime workqueue, clock is disabled after the replicator
is initialized by amba_pm_runtime_suspend assuming that context
is not lost which is not true for replicators with such
limitations. Hence check the replicator idfilter registers
in dynamic_replicator_enable() and reset again.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan(a)codeaurora.org>
---
More info here - https://lore.kernel.org/patchwork/patch/1231182/
---
drivers/hwtracing/coresight/coresight-replicator.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
index e7dc1c31d20d..11df63f51071 100644
--- a/drivers/hwtracing/coresight/coresight-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-replicator.c
@@ -68,6 +68,17 @@ static int dynamic_replicator_enable(struct replicator_drvdata *drvdata,
int rc = 0;
u32 reg;
+ /*
+ * On some QCOM SoCs with replicators in Always-On domain, disabling
+ * clock will result in replicator losing its context. Currently
+ * as a part of pm_runtime workqueue, amba_pm_runtime_suspend disables
+ * clock assuming the context is not lost which is not true for cases
+ * with hardware limitations as the above.
+ */
+ if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) == 0) &&
+ (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) == 0))
+ dynamic_replicator_reset(drvdata);
+
switch (outport) {
case 0:
reg = REPLICATOR_IDFILTER0;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
This patchset provides a proposed infrastructure to allow for the automatic
selection of a sink during CoreSight tracing operations.
Currently starting tracing using perf requires a sink selection on the
command line:-
sudo ./perf record -e cs_etm/@tmc_etr0/ --per-thread uname -a
After this set the infrastructure will be able to select a default sink:-
sudo ./perf record -e cs_etm// --per-thread uname -a
This matches with the default operation provided with perf and intelpt.
The CoreSight infrastructure is updated with the concept of a
sink_select_priority value used when sinks are registered with the system.
Where no sink is specified at the start of a trace session, the CoreSight
system will walk the connection graph from the source ETM, to find a
suitable sink using the first encountered highest priority device.
Sinks set a value during component registration, ETR the highest priority,
ETB and ETF a lower priority. Thus the first ETR if present will be used,
otherwise fallback to the first encountered ETF/ETB.
The automatic sink selection will also operate if an ETM is enabled using
sysfs commands, and no sink is currently enabled.
Applied to Linux 5.7-rc3.
Changes since v1:
1) Dropped the device-tree attribute labelling of sinks for selection and
implemented the priority schema preferring first encountered ETR,
after mailing list discussions.
2) Added in sysfs support for auto sink selection.
Mike Leach (5):
coresight: Add default sink selection to CoreSight base
coresight: tmc: Add default sink selection priorities.
coresight: etm: perf: Add default sink selection to etm perf
coresight: sysfs: Allow select default sink on source enable.
perf: cs-etm: Allow no CoreSight sink to be specified on command line
.../hwtracing/coresight/coresight-etm-perf.c | 20 ++++-
drivers/hwtracing/coresight/coresight-priv.h | 2 +
drivers/hwtracing/coresight/coresight-tmc.c | 5 ++
drivers/hwtracing/coresight/coresight.c | 87 ++++++++++++++++++-
include/linux/coresight.h | 10 ++-
tools/perf/arch/arm/util/cs-etm.c | 6 +-
6 files changed, 121 insertions(+), 9 deletions(-)
--
2.17.1
OpenCSD version v0.14.0 adds in a new output element. This is represented
by a new value in the generic element type enum, which must be added to
the handling code in perf cs-etm-decoder to prevent build errors due to
build options on the perf project.
This element is not currently used by the perf decoder.
Perf build feature test updated to require a minimum of 0.14.0
Tested on Linux 5.7-rc3.
Signed-off-by: Mike Leach <mike.leach(a)linaro.org>
---
tools/build/feature/test-libopencsd.c | 4 ++--
tools/perf/util/cs-etm-decoder/cs-etm-decoder.c | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/tools/build/feature/test-libopencsd.c b/tools/build/feature/test-libopencsd.c
index 2b0e02c38870..1547bc2c0950 100644
--- a/tools/build/feature/test-libopencsd.c
+++ b/tools/build/feature/test-libopencsd.c
@@ -4,9 +4,9 @@
/*
* Check OpenCSD library version is sufficient to provide required features
*/
-#define OCSD_MIN_VER ((0 << 16) | (11 << 8) | (0))
+#define OCSD_MIN_VER ((0 << 16) | (14 << 8) | (0))
#if !defined(OCSD_VER_NUM) || (OCSD_VER_NUM < OCSD_MIN_VER)
-#error "OpenCSD >= 0.11.0 is required"
+#error "OpenCSD >= 0.14.0 is required"
#endif
int main(void)
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index cd92a99eb89d..cd007cc9c283 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
@@ -564,6 +564,8 @@ static ocsd_datapath_resp_t cs_etm_decoder__gen_trace_elem_printer(
resp = cs_etm_decoder__set_tid(etmq, packet_queue,
elem, trace_chan_id);
break;
+ /* Unused packet types */
+ case OCSD_GEN_TRC_ELEM_I_RANGE_NOPATH:
case OCSD_GEN_TRC_ELEM_ADDR_NACC:
case OCSD_GEN_TRC_ELEM_CYCLE_COUNT:
case OCSD_GEN_TRC_ELEM_ADDR_UNKNOWN:
--
2.17.1