CoreSight

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Enquiry on Using Coresight on Android (SM8450+Android 12+Linux 5.10)

by zengshun.wu＠outlook.com

HI ： I am currently using coresight ETM features on Android to try and improve performance. I compiled perf on aarch64 host and pushed it to android. The version of perf and linux kernel are the same. 1. Information about the device SM8450 + Android 12 Linux localhost 5.10.66-qki-consolidate-g14f56d7c5ad6 #1 SMP PREEMPT Tue May 10 11:18:19 UTC 2022 aarch64 2. I ran into some trouble 1) perf encountered syntax error when executing the command. 2) Unable to decode 3. The whole process of my test execution (1) PS C:\Users\wzs>adb push perf /data/local/tmp (2) PS C:\Users\wzs>adb shell chmod 0777 /data/local/tmp/perf (3) PS C:\Users\wzs>adb shell #ls /sys/bus/event_source/devices/cs_etm/sinks/ coresight-eud coresight-tmc-etf coresight-tmc-etr coresight-tmc-etr1 (4) #cd /data/local/tmp/perf #HOME=/data/local/tmp #./perf --buildid-dir /data/local/tmp/.debug record -e cs_etm/@coresight-tmc-etr/u --filter 'filter 0x15f0/0x40(a)/system/lib64/libcstest.so' --per-thread ./main event syntax error: 'cs_etm/@coresight-tmc-etr/u' \___ parser error Run 'perf list' for a list of valid events Usage: perf record [<options>] [<command>] or: perf record [<options>] -- <command> [<options>] -e, --event <event> event selector. use 'perf list' to list available events There is a syntax error here, I think it is because the perf parser thinks that the symbol "-" in the string "coresight-tmc-etr" is illegal. But I don't know how to fix it, so I did the following. Use tmc_etr, but replace it with coresight-tmc-etr in the code. --- a/tools/perf/util/parse-events2.c +++ b/tools/perf/util/parse-events.c @@ -2916,6 +2916,8 @@ int parse_events__is_hardcoded_term(struct parse_events_term *term) return term->type_term != PARSE_EVENTS__TERM_TYPE_USER; } +char *cs_str;//"coresight-tmc-etr" + static int new_term(struct parse_events_term **_term, struct parse_events_term *temp, char *str, u64 num) @@ -2925,6 +2927,12 @@ static int new_term(struct parse_events_term **_term, term = malloc(sizeof(*term)); if (!term) return -ENOMEM; + if (str && !strcmp(str, "tmc_etr")) { + cs_str = (char*)malloc(30); + strcpy(cs_str, "coresight-tmc-etr"); + str = cs_str; + } *term = *temp; INIT_LIST_HEAD(&term->list); term->weak = false; Will continue. (5) #./perf --buildid-dir /data/local/tmp/.debug record -e cs_etm/@tmc_etr/u --per-thread ./main val: 20 [ perf record: Woken up 1 times to write data ] BFD: /apex/com.android.runtime/bin/linker64: unknown type [0x13] section `.relr.dyn' BFD: /apex/com.android.runtime/lib64/bionic/libm.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libutils.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libnetd_client.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libcgrouprc.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libvndksupport.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/liblog.so: unknown type [0x13] section `.relr.dyn' BFD: /system/lib64/libc++.so: unknown type [0x13] section `.relr.dyn' [ perf record: Captured and wrote 1.316 MB perf.data ] (6) # ls -al total 1861311 drwxrwx--x 3 shell shell 8192 2022-01-05 05:37 . drwxr-x--x 5 root root 3452 2022-01-04 05:56 .. drwxr-xr-x 418 root root 24576 2022-01-05 04:31 .debug -rw-rw-rw- 1 root root 1859414850 2022-01-05 04:36 cs_example.tgz -rwxrwxrwx 1 root root 42944200 2022-05-14 16:15 perf -rw------- 1 root root 1425940 2022-01-05 05:37 perf.data (7) #./perf report --stdio # To display the perf.data header info, please use --header/--header-only options. # Error: The perf.data data has no samples! An exception has been shown here, no data was sampled. (8) #tar czf cs_example.tgz perf.data ~/.debug It will then be decoded on my host via OpenCSD. (9) wzs@ubuntu:~/perf/windows_path/test-cs/cs-decode$ cat disasm.sh EXEC_PATH=/home/wzs/perf/sm8450_kernel_src/tools/perf/ SCRIPT_PATH=/home/wzs/perf/sm8450_kernel_src/tools/perf/scripts/python/ XTOOLS_PATH=/home/wzs/android-ndk/toolchains/llvm/prebuilt/linux-x86_64/bin/llvm-objdump ./perf --exec-path=${EXEC_PATH} script --script=python:${SCRIPT_PATH}/arm-cs-trace-disasm.py -- -d $XTOOLS_PATH -k ./vmlinux -v (10) wzs@ubuntu:~/perf/windows_path/test-cs/cs-decode$ ./disasm.sh ARM CoreSight Trace Data Assembler Dump parse_mmap = { pid: 19130 dso: /data/local/tmp/main start: 0x5f8d029000 end: 0x5f8d02a000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/bin/linker64 start: 0x7eaafab000 end: 0x7eab096000} parse_mmap = { pid: 19130 dso: [vdso] start: 0x7eaaf72000 end: 0x7eaaf73000} parse_mmap = { pid: 19130 dso: /system/lib64/libcstest.so start: 0x7ea9c62000 end: 0x7ea9c63000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libc.so start: 0x7ea6f70000 end: 0x7ea702d000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libc.so start: 0x7ea6f70000 end: 0x7ea702d000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libdl.so start: 0x7ea9c0e000 end: 0x7ea9c0f000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libdl.so start: 0x7ea9c0e000 end: 0x7ea9c0f000} parse_mmap = { pid: 19130 dso: /system/lib64/libc++.so start: 0x7ea9a8a000 end: 0x7ea9ae7000} parse_mmap = { pid: 19130 dso: /system/lib64/libc++.so start: 0x7ea9a8a000 end: 0x7ea9ae7000} parse_mmap = { pid: 19130 dso: /system/lib64/libcutils.so start: 0x7ea6ef0000 end: 0x7ea6ef8000} parse_mmap = { pid: 19130 dso: /system/lib64/libcutils.so start: 0x7ea6ef0000 end: 0x7ea6ef8000} parse_mmap = { pid: 19130 dso: /system/lib64/libcgrouprc.so start: 0x7ea6e8f000 end: 0x7ea6e90000} parse_mmap = { pid: 19130 dso: /system/lib64/libcgrouprc.so start: 0x7ea6e8f000 end: 0x7ea6e90000} parse_mmap = { pid: 19130 dso: /system/lib64/libprocessgroup.so start: 0x7c96da5000 end: 0x7c96dd8000} parse_mmap = { pid: 19130 dso: /system/lib64/libprocessgroup.so start: 0x7c96da5000 end: 0x7c96dd8000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libm.so start: 0x7ea6e52000 end: 0x7ea6e75000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libm.so start: 0x7ea6e52000 end: 0x7ea6e75000} parse_mmap = { pid: 19130 dso: /system/lib64/libbase.so start: 0x7c96d53000 end: 0x7c96d7c000} parse_mmap = { pid: 19130 dso: /system/lib64/libbase.so start: 0x7c96d53000 end: 0x7c96d7c000} parse_mmap = { pid: 19130 dso: /system/lib64/liblog.so start: 0x7c96d2a000 end: 0x7c96d35000} parse_mmap = { pid: 19130 dso: /system/lib64/liblog.so start: 0x7c96d2a000 end: 0x7c96d35000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libdl_android.so start: 0x7c96ced000 end: 0x7c96cee000} parse_mmap = { pid: 19130 dso: /apex/com.android.runtime/lib64/bionic/libdl_android.so start: 0x7c96ced000 end: 0x7c96cee000} parse_mmap = { pid: 19130 dso: /system/lib64/libutils.so start: 0x7c96caa000 end: 0x7c96cb7000} parse_mmap = { pid: 19130 dso: /system/lib64/libutils.so start: 0x7c96caa000 end: 0x7c96cb7000} parse_mmap = { pid: 19130 dso: /system/lib64/libvndksupport.so start: 0x7c96c4d000 end: 0x7c96c4e000} parse_mmap = { pid: 19130 dso: /system/lib64/libvndksupport.so start: 0x7c96c4d000 end: 0x7c96c4e000} parse_mmap = { pid: 19130 dso: /system/lib64/libnetd_client.so start: 0x7c96c36000 end: 0x7c96c3c000} parse_mmap = { pid: 19130 dso: /system/lib64/libnetd_client.so start: 0x7c96c36000 end: 0x7c96c3c000} End At step 7 it shows no sampled data, and at step 10 there really isn't any output. I think it should be at step 5 that it doesn't work, but perf doesn't actually report an error. Please give me some advice, I would be happy to make this function work successfully on android. This would be helpful for debugging and performance related work. Thanks.

3 years, 1 month

[ISSUE] trace_id of ETM will be invalid when there are more than 48 CPUs on chip

by liuqi (BA)

Hi all, My colleague Junhao He noticed this issue when tracing CPU48 on Kunpeng920 platform, log as follows: [root@localhost ~]# perf record -e cs_etm/@sink_smb1/ -C 48 -o perf.data taskset -c 48 uname -a [root@localhost ~]# perf report -D --stdio -i perf.data > perf_48.log 0x270 [0xc8]: failed to process type: 70 [Invalid argument] Error: failed to process sample [root@localhost ~]# perf -v perf version 5.17.rc4.gdeea22e4af29 [root@localhost ~]# ldd /usr/bin/perf | grep opencsd libopencsd_c_api.so.1 => /root/lib/libopencsd_c_api.so.1 libopencsd.so.1 => /root/lib/libopencsd.so.1 As (CORESIGHT_ETM_PMU_SEED + (cpu * 2)) is used in coresight_get_trace_id() to cacualate trace_id, if there are more than 48 CPUs on chip, we will have some ETM device which trace id is invalid(trace_id = 0 or trace_id > 0x6F). In this situation, we cannot parse trace data using perf tool. Perhaps we should make trace_id in the range of 1 to 0x6F in coresight_get_trace_id()? But there also might be parsing problem if duplicate trace ID is used during collection. Any response will be highly appreciated. Thanks, Qi

3 years, 1 month

Re: [PATCH v5 2/2] perf scripts python: Support Arm CoreSight trace data disassembly

by Leo Yan

On Sun, May 15, 2022 at 02:18:53PM -0700, Ian Rogers wrote: [...] > This looks good to me and will run on python 2. The code would be more > idiomatic in python3 using f-strings. I'd rather the code was > idiomatic from the beginning, but others may disagree and prefer > python 2 compatibility (python 2 is now end of life). f-strings are > python 3.6+ and so have been supported for 5 years. Using f-string is the right thing for me, will update. Thanks for reviewing and suggestion! Leo

3 years, 1 month

[PATCH v5 0/2] perf script python: Add script for CoreSight disassembly

by Leo Yan

This patch set is to restart the upstreaming for CoreSight disassembly script [1], the python script can be used to dump assembly, source line and symbols so it can be easier for humans inspecting. The first patch changes python script engine to expose more information for DSO and maps, so it's helpful for disassembly with objdump program. The second patch is to introduce the python script for CoreSight trace data disassembly for branch samples. It also can dump source line and symbol info for instruction samples. This patch set has been tested on Arm64 Juno board: # perf script -s scripts/python/arm-cs-trace-disasm.py ... main 6728/6728 [004] 0.000000000 main+0x40 /root/coresight_test/main.c for (i = 0; i < 10000; i++) { main 6728/6728 [004] 0.000000000 main+0x20 /root/coresight_test/main.c val = lib_loop_test(100); main 6728/6728 [004] 0.000000000 lib_loop_test@plt+0xc /root/coresight_test/main main 6728/6728 [004] 0.000000000 lib_loop_test+0xc /root/coresight_test/libcstest.c for (i = 0; i < 5; i++) main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x30 main 6728/6728 [004] 0.000000000 lib_loop_test+0x3c /root/coresight_test/libcstest.c } # perf script -s scripts/python/arm-cs-trace-disasm.py -- -d llvm-objdump-11 -k ./vmlinux ARM CoreSight Trace Data Assembler Dump ffff800008eb3198 <etm4_enable_hw>: ffff800008eb3310: c0 38 00 35 cbnz w0, 0xffff800008eb3a28 <etm4_enable_hw+0x890> ffff800008eb3314: 9f 3f 03 d5 dsb sy ffff800008eb3318: df 3f 03 d5 isb ffff800008eb331c: f5 5b 42 a9 ldp x21, x22, [sp, #32] ffff800008eb3320: fb 73 45 a9 ldp x27, x28, [sp, #80] ffff800008eb3324: e0 82 40 39 ldrb w0, [x23, #32] ffff800008eb3328: 60 00 00 34 cbz w0, 0xffff800008eb3334 <etm4_enable_hw+0x19c> ffff800008eb332c: e0 03 19 aa mov x0, x25 ffff800008eb3330: 8c fe ff 97 bl 0xffff800008eb2d60 <etm4_cs_lock.isra.0.part.0> main 6055/6055 [004] 0.000000000 etm4_enable_hw+0x198 [kernel.kallsyms] ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0>: ffff800008eb2d60: 1f 20 03 d5 nop ffff800008eb2d64: 1f 20 03 d5 nop ffff800008eb2d68: 3f 23 03 d5 hint #25 ffff800008eb2d6c: 00 00 40 f9 ldr x0, [x0] ffff800008eb2d70: 9f 3f 03 d5 dsb sy ffff800008eb2d74: 00 c0 3e 91 add x0, x0, #4016 ffff800008eb2d78: 1f 00 00 b9 str wzr, [x0] ffff800008eb2d7c: bf 23 03 d5 hint #29 ffff800008eb2d80: c0 03 5f d6 ret main 6055/6055 [004] 0.000000000 etm4_cs_lock.isra.0.part.0+0x20 # perf script -s scripts/python/arm-cs-trace-disasm.py -- -d objdump -k ./vmlinux ARM CoreSight Trace Data Assembler Dump ffff800008eb3310 <etm4_enable_hw+0x178>: ffff800008eb3310: 350038c0 cbnz w0, ffff800008eb3a28 <etm4_enable_hw+0x890> ffff800008eb3314: d5033f9f dsb sy ffff800008eb3318: d5033fdf isb ffff800008eb331c: a9425bf5 ldp x21, x22, [sp, #32] ffff800008eb3320: a94573fb ldp x27, x28, [sp, #80] ffff800008eb3324: 394082e0 ldrb w0, [x23, #32] ffff800008eb3328: 34000060 cbz w0, ffff800008eb3334 <etm4_enable_hw+0x19c> ffff800008eb332c: aa1903e0 mov x0, x25 ffff800008eb3330: 97fffe8c bl ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0> main 6055/6055 [004] 0.000000000 etm4_enable_hw+0x198 [kernel.kallsyms] ffff800008eb2d60 <etm4_cs_lock.isra.0.part.0>: ffff800008eb2d60: d503201f nop ffff800008eb2d64: d503201f nop ffff800008eb2d68: d503233f paciasp ffff800008eb2d6c: f9400000 ldr x0, [x0] ffff800008eb2d70: d5033f9f dsb sy ffff800008eb2d74: 913ec000 add x0, x0, #0xfb0 ffff800008eb2d78: b900001f str wzr, [x0] ffff800008eb2d7c: d50323bf autiasp ffff800008eb2d80: d65f03c0 ret main 6055/6055 [004] 0.000000000 etm4_cs_lock.isra.0.part.0+0x20 [1] https://lists.linaro.org/archives/list/coresight@lists.linaro.org/thread/GI… Changes from v4: * Enhanced python script engine for DSO and map infos; * Rewrote the python script, added support for symbol and source line dumping. Leo Yan (2): perf scripting python: Expose dso and map information perf scripts python: Support Arm CoreSight trace data disassembly .../scripts/python/arm-cs-trace-disasm.py | 275 ++++++++++++++++++ .../scripting-engines/trace-event-python.c | 21 +- 2 files changed, 292 insertions(+), 4 deletions(-) create mode 100755 tools/perf/scripts/python/arm-cs-trace-disasm.py -- 2.25.1

3 years, 1 month

[GIT PULL] Coresight changes for v5.19

by Mathieu Poirier

The following changes since commit ce522ba9ef7e2d9fb22a39eb3371c0c64e2a433e: Linux 5.18-rc2 (2022-04-10 14:21:36 -1000) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.19 for you to fetch changes up to 1adff542d67a2ed1120955cb219bfff8a9c53f59: coresight: cpu-debug: Replace mutex with mutex_trylock on panic notifier (2022-05-09 16:03:24 +0100) ---------------------------------------------------------------- Coresight changes for v5.19 Good day Greg, Please consider those for the the upcoming v5.19 merge window when you have time. This pull request includes: - Work to uniformise access to the ETMv4 registers, making it easier to look for and change register accesses. - A correction to a probing failure when looking for links between devices. - The replacement of a call to mutex_lock() with a mutex_trylock() in the panic notifier of the cpu-debug infrastructure to avoid a possible deadlock. Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> ---------------------------------------------------------------- Guilherme G. Piccoli (1): coresight: cpu-debug: Replace mutex with mutex_trylock on panic notifier James Clark (15): coresight: etm4x: Cleanup TRCIDR0 register accesses coresight: etm4x: Cleanup TRCIDR2 register accesses coresight: etm4x: Cleanup TRCIDR3 register accesses coresight: etm4x: Cleanup TRCIDR4 register accesses coresight: etm4x: Cleanup TRCIDR5 register accesses coresight: etm4x: Cleanup TRCCONFIGR register accesses coresight: etm4x: Cleanup TRCEVENTCTL1R register accesses coresight: etm4x: Cleanup TRCSTALLCTLR register accesses coresight: etm4x: Cleanup TRCVICTLR register accesses coresight: etm3x: Cleanup ETMTECR1 register accesses coresight: etm4x: Cleanup TRCACATRn register accesses coresight: etm4x: Cleanup TRCSSCCRn and TRCSSCSRn register accesses coresight: etm4x: Cleanup TRCSSPCICRn register accesses coresight: etm4x: Cleanup TRCBBCTLR register accesses coresight: etm4x: Cleanup TRCRSCTLRn register accesses Mao Jinlong (1): coresight: core: Fix coresight device probe failure issue drivers/hwtracing/coresight/coresight-core.c | 33 ++-- drivers/hwtracing/coresight/coresight-cpu-debug.c | 7 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 2 +- .../hwtracing/coresight/coresight-etm3x-sysfs.c | 2 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 136 +++++----------- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 180 +++++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 120 +++++++++++--- 7 files changed, 268 insertions(+), 212 deletions(-)

3 years, 1 month

[PATCH 0/4] perf cs_etm: Basic support for virtual/kernel timestamps

by German Gomez

Hi, This change has a soft dependency on [1], but assuming the name/location of the new sysfs interface (ts_source) doesn't change, it should be safe to apply. The new 'ts_source' interface allows perf to detect if the timestamps in the trace correspond to the value of CNTVCT_EL0, which we can convert to a perf timestamp and store it in the instruction and branch samples. Due to the way the trace is compressed and decoded by OpenCSD, we only know the precise time of the first instruction in a range, but I think for now this is better than not having timestamps at all... Thanks, German [1] https://lore.kernel.org/all/20220503123537.1003035-1-german.gomez@arm.com/ German Gomez (4): perf pmu: Add function to check if a pmu file exists perf cs_etm: Keep separate symbols for ETMv4 and ETE parameters perf cs_etm: Record ts_source in AUXTRACE_INFO for ETMv4 and ETE perf cs_etm: Set the time field in the synthetic samples tools/perf/arch/arm/util/cs-etm.c | 89 +++++++++++++++++++-- tools/perf/util/cs-etm.c | 126 +++++++++++++++++++++++++----- tools/perf/util/cs-etm.h | 13 ++- tools/perf/util/pmu.c | 17 ++++ tools/perf/util/pmu.h | 2 + 5 files changed, 221 insertions(+), 26 deletions(-) -- 2.25.1

3 years, 1 month

Re: [PATCH v7 5/7] perf tool: Add support for HiSilicon PCIe Tune and Trace device driver

by James Clark

On 07/04/2022 13:58, Yicong Yang wrote: > From: Qi Liu <liuqi115(a)huawei.com> > > 'perf record' and 'perf report --dump-raw-trace' supported in this > patch. > > Example usage: > > Output will contain raw PTT data and its textual representation, such > as: > > 0 0 0x5810 [0x30]: PERF_RECORD_AUXTRACE size: 0x400000 offset: 0 > ref: 0xa5d50c725 idx: 0 tid: -1 cpu: 0 > . > . ... HISI PTT data: size 4194304 bytes > . 00000000: 00 00 00 00 Prefix > . 00000004: 08 20 00 60 Header DW0 > . 00000008: ff 02 00 01 Header DW1 > . 0000000c: 20 08 00 00 Header DW2 > . 00000010: 10 e7 44 ab Header DW3 > . 00000014: 2a a8 1e 01 Time > . 00000020: 00 00 00 00 Prefix > . 00000024: 01 00 00 60 Header DW0 > . 00000028: 0f 1e 00 01 Header DW1 > . 0000002c: 04 00 00 00 Header DW2 > . 00000030: 40 00 81 02 Header DW3 > . 00000034: ee 02 00 00 Time > .... > > Signed-off-by: Qi Liu <liuqi115(a)huawei.com> > Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> > --- > tools/perf/arch/arm/util/auxtrace.c | 76 +++++- > tools/perf/arch/arm/util/pmu.c | 3 + > tools/perf/arch/arm64/util/Build | 2 +- > tools/perf/arch/arm64/util/hisi_ptt.c | 195 ++++++++++++++++ > tools/perf/util/Build | 2 + > tools/perf/util/auxtrace.c | 4 + > tools/perf/util/auxtrace.h | 1 + > tools/perf/util/hisi-ptt-decoder/Build | 1 + > .../hisi-ptt-decoder/hisi-ptt-pkt-decoder.c | 170 ++++++++++++++ > .../hisi-ptt-decoder/hisi-ptt-pkt-decoder.h | 28 +++ > tools/perf/util/hisi_ptt.c | 218 ++++++++++++++++++ > tools/perf/util/hisi_ptt.h | 28 +++ > 12 files changed, 724 insertions(+), 4 deletions(-) > create mode 100644 tools/perf/arch/arm64/util/hisi_ptt.c > create mode 100644 tools/perf/util/hisi-ptt-decoder/Build > create mode 100644 tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.c > create mode 100644 tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.h > create mode 100644 tools/perf/util/hisi_ptt.c > create mode 100644 tools/perf/util/hisi_ptt.h > > diff --git a/tools/perf/arch/arm/util/auxtrace.c b/tools/perf/arch/arm/util/auxtrace.c > index 5fc6a2a3dbc5..393f5757c039 100644 > --- a/tools/perf/arch/arm/util/auxtrace.c > +++ b/tools/perf/arch/arm/util/auxtrace.c > @@ -4,9 +4,11 @@ > * Author: Mathieu Poirier <mathieu.poirier(a)linaro.org> > */ > > +#include <dirent.h> > #include <stdbool.h> > #include <linux/coresight-pmu.h> > #include <linux/zalloc.h> > +#include <api/fs/fs.h> > > #include "../../../util/auxtrace.h" > #include "../../../util/debug.h" > @@ -14,6 +16,7 @@ > #include "../../../util/pmu.h" > #include "cs-etm.h" > #include "arm-spe.h" > +#include "hisi_ptt.h" > > static struct perf_pmu **find_all_arm_spe_pmus(int *nr_spes, int *err) > { > @@ -50,6 +53,58 @@ static struct perf_pmu **find_all_arm_spe_pmus(int *nr_spes, int *err) > return arm_spe_pmus; > } > > +static struct perf_pmu **find_all_hisi_ptt_pmus(int *nr_ptts, int *err) > +{ > + const char *sysfs = sysfs__mountpoint(); > + struct perf_pmu **hisi_ptt_pmus = NULL; > + struct dirent *dent; > + char path[PATH_MAX]; > + DIR *dir = NULL; > + int idx = 0; > + > + snprintf(path, PATH_MAX, "%s" EVENT_SOURCE_DEVICE_PATH, sysfs); > + dir = opendir(path); > + if (!dir) { > + pr_err("can't read directory '%s'\n", EVENT_SOURCE_DEVICE_PATH); > + *err = -EINVAL; > + goto out; > + } > + > + while ((dent = readdir(dir))) { > + if (strstr(dent->d_name, HISI_PTT_PMU_NAME)) > + (*nr_ptts)++; > + } > + > + if (!(*nr_ptts)) > + goto out; > + > + hisi_ptt_pmus = zalloc(sizeof(struct perf_pmu *) * (*nr_ptts)); > + if (!hisi_ptt_pmus) { > + pr_err("hisi_ptt alloc failed\n"); > + *err = -ENOMEM; > + goto out; > + } > + > + rewinddir(dir); > + while ((dent = readdir(dir))) { > + if (strstr(dent->d_name, HISI_PTT_PMU_NAME) && idx < (*nr_ptts)) { > + hisi_ptt_pmus[idx] = perf_pmu__find(dent->d_name); > + if (hisi_ptt_pmus[idx]) { > + pr_debug2("%s %d: hisi_ptt_pmu %d type %d name %s\n", > + __func__, __LINE__, idx, > + hisi_ptt_pmus[idx]->type, > + hisi_ptt_pmus[idx]->name); > + idx++; > + } > + > + } > + } > + > +out: > + closedir(dir); > + return hisi_ptt_pmus; > +} > + > struct auxtrace_record > *auxtrace_record__init(struct evlist *evlist, int *err) > { > @@ -57,8 +112,12 @@ struct auxtrace_record > struct evsel *evsel; > bool found_etm = false; > struct perf_pmu *found_spe = NULL; > + struct perf_pmu *found_ptt = NULL; > struct perf_pmu **arm_spe_pmus = NULL; > + struct perf_pmu **hisi_ptt_pmus = NULL; > + > int nr_spes = 0; > + int nr_ptts = 0; > int i = 0; > > if (!evlist) > @@ -66,13 +125,14 @@ struct auxtrace_record > > cs_etm_pmu = perf_pmu__find(CORESIGHT_ETM_PMU_NAME); > arm_spe_pmus = find_all_arm_spe_pmus(&nr_spes, err); > + hisi_ptt_pmus = find_all_hisi_ptt_pmus(&nr_ptts, err); > > evlist__for_each_entry(evlist, evsel) { > if (cs_etm_pmu && > evsel->core.attr.type == cs_etm_pmu->type) > found_etm = true; > > - if (!nr_spes || found_spe) > + if ((!nr_spes || found_spe) && (!nr_ptts || found_ptt)) > continue; > > for (i = 0; i < nr_spes; i++) { > @@ -81,11 +141,18 @@ struct auxtrace_record > break; > } > } > + > + for (i = 0; i < nr_ptts; i++) { > + if (evsel->core.attr.type == hisi_ptt_pmus[i]->type) { > + found_ptt = hisi_ptt_pmus[i]; > + break; > + } > + } > } > free(arm_spe_pmus); > > - if (found_etm && found_spe) { > - pr_err("Concurrent ARM Coresight ETM and SPE operation not currently supported\n"); > + if (found_etm && found_spe && found_ptt) { > + pr_err("Concurrent ARM Coresight ETM ,SPE and HiSilicon PCIe Trace operation not currently supported\n"); Hi Yicong, Is that actually a limitation? I don't see why they couldn't work concurrently. > *err = -EOPNOTSUPP; > return NULL; > } > @@ -96,6 +163,9 @@ struct auxtrace_record > #if defined(__aarch64__) > if (found_spe) > return arm_spe_recording_init(err, found_spe); > + > + if (found_ptt) > + return hisi_ptt_recording_init(err, found_ptt); > #endif > > /* > diff --git a/tools/perf/arch/arm/util/pmu.c b/tools/perf/arch/arm/util/pmu.c > index b8b23b9dc598..89a3cedb4557 100644 > --- a/tools/perf/arch/arm/util/pmu.c > +++ b/tools/perf/arch/arm/util/pmu.c > @@ -10,6 +10,7 @@ > #include <linux/string.h> > > #include "arm-spe.h" > +#include "hisi_ptt.h" > #include "../../../util/pmu.h" > > struct perf_event_attr > @@ -22,6 +23,8 @@ struct perf_event_attr > #if defined(__aarch64__) > } else if (strstarts(pmu->name, ARM_SPE_PMU_NAME)) { > return arm_spe_pmu_default_config(pmu); > + } else if (strstarts(pmu->name, HISI_PTT_PMU_NAME)) { > + pmu->selectable = true; > #endif > } > > diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build > index 9fcb4e68add9..8b7fd1dc9f37 100644 > --- a/tools/perf/arch/arm64/util/Build > +++ b/tools/perf/arch/arm64/util/Build > @@ -11,4 +11,4 @@ perf-$(CONFIG_LIBDW_DWARF_UNWIND) += unwind-libdw.o > perf-$(CONFIG_AUXTRACE) += ../../arm/util/pmu.o \ > ../../arm/util/auxtrace.o \ > ../../arm/util/cs-etm.o \ > - arm-spe.o mem-events.o > + arm-spe.o mem-events.o hisi_ptt.o > diff --git a/tools/perf/arch/arm64/util/hisi_ptt.c b/tools/perf/arch/arm64/util/hisi_ptt.c > new file mode 100644 > index 000000000000..de3a3523ffd5 > --- /dev/null > +++ b/tools/perf/arch/arm64/util/hisi_ptt.c > @@ -0,0 +1,195 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * HiSilicon PCIe Trace and Tuning (PTT) support > + * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. > + */ > + > +#include <linux/kernel.h> > +#include <linux/types.h> > +#include <linux/bitops.h> > +#include <linux/log2.h> > +#include <linux/zalloc.h> > +#include <time.h> > + > +#include <internal/lib.h> // page_size > +#include "../../../util/auxtrace.h" > +#include "../../../util/cpumap.h" > +#include "../../../util/debug.h" > +#include "../../../util/event.h" > +#include "../../../util/evlist.h" > +#include "../../../util/evsel.h" > +#include "../../../util/hisi_ptt.h" > +#include "../../../util/pmu.h" > +#include "../../../util/record.h" > +#include "../../../util/session.h" > +#include "../../../util/tsc.h" > + > +#define DEFAULT_PAGE_SIZE 1024 > +#define KiB(x) ((x) * DEFAULT_PAGE_SIZE) > +#define MiB(x) ((x) * DEFAULT_PAGE_SIZE * DEFAULT_PAGE_SIZE) > + > +struct hisi_ptt_recording { > + struct auxtrace_record itr; > + struct perf_pmu *hisi_ptt_pmu; > + struct evlist *evlist; > +}; > + > +static size_t > +hisi_ptt_info_priv_size(struct auxtrace_record *itr __maybe_unused, > + struct evlist *evlist __maybe_unused) > +{ > + return HISI_PTT_AUXTRACE_PRIV_SIZE; > +} > + > +static int hisi_ptt_info_fill(struct auxtrace_record *itr, > + struct perf_session *session, > + struct perf_record_auxtrace_info *auxtrace_info, > + size_t priv_size) > +{ > + struct hisi_ptt_recording *pttr = > + container_of(itr, struct hisi_ptt_recording, itr); > + struct perf_pmu *hisi_ptt_pmu = pttr->hisi_ptt_pmu; > + > + if (priv_size != HISI_PTT_AUXTRACE_PRIV_SIZE) > + return -EINVAL; > + > + if (!session->evlist->core.nr_mmaps) > + return -EINVAL; > + > + auxtrace_info->type = PERF_AUXTRACE_HISI_PTT; > + auxtrace_info->priv[HISI_PTT_PMU_TYPE] = hisi_ptt_pmu->type; > + > + return 0; > +} > + > +static int hisi_ptt_set_auxtrace_mmap_page(struct record_opts *opts) > +{ > + bool privileged = perf_event_paranoid_check(-1); > + > + if (!opts->full_auxtrace) > + return 0; > + > + if (opts->full_auxtrace && !opts->auxtrace_mmap_pages) { > + if (privileged) { > + opts->auxtrace_mmap_pages = MiB(16) / page_size; > + } else { > + opts->auxtrace_mmap_pages = KiB(128) / page_size; > + if (opts->mmap_pages == UINT_MAX) > + opts->mmap_pages = KiB(256) / page_size; > + } > + } > + > + /* Validate auxtrace_mmap_pages */ > + if (opts->auxtrace_mmap_pages) { > + size_t sz = opts->auxtrace_mmap_pages * (size_t)page_size; > + size_t min_sz = KiB(8); > + > + if (sz < min_sz || !is_power_of_2(sz)) { > + pr_err("Invalid mmap size for HISI PTT: must be at least %zuKiB and a power of 2\n", > + min_sz / DEFAULT_PAGE_SIZE); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > +static int hisi_ptt_recording_options(struct auxtrace_record *itr, > + struct evlist *evlist, > + struct record_opts *opts) > +{ > + struct hisi_ptt_recording *pttr = > + container_of(itr, struct hisi_ptt_recording, itr); > + struct perf_pmu *hisi_ptt_pmu = pttr->hisi_ptt_pmu; > + struct perf_cpu_map *cpus = evlist->core.cpus; > + struct evsel *evsel, *hisi_ptt_evsel = NULL; > + struct evsel *tracking_evsel; > + int err; > + > + pttr->evlist = evlist; > + evlist__for_each_entry(evlist, evsel) { > + if (evsel->core.attr.type == hisi_ptt_pmu->type) { > + if (hisi_ptt_evsel) { > + pr_err("There may be only one " HISI_PTT_PMU_NAME "x event\n"); > + return -EINVAL; > + } > + evsel->core.attr.freq = 0; > + evsel->core.attr.sample_period = 1; > + hisi_ptt_evsel = evsel; > + opts->full_auxtrace = true; > + } > + } > + > + err = hisi_ptt_set_auxtrace_mmap_page(opts); > + if (err) > + return err; > + /* > + * To obtain the auxtrace buffer file descriptor, the auxtrace event > + * must come first. > + */ > + evlist__to_front(evlist, hisi_ptt_evsel); > + > + if (!perf_cpu_map__empty(cpus)) { > + evsel__set_sample_bit(hisi_ptt_evsel, TIME); > + evsel__set_sample_bit(hisi_ptt_evsel, CPU); > + } Similar to Leo's comment: CPU isn't required if it's uncore, and if TIME is useful then add it regardless of whether the event is opened per-cpu or on a task. > + > + /* Add dummy event to keep tracking */ > + err = parse_events(evlist, "dummy:u", NULL); > + if (err) > + return err; > + > + tracking_evsel = evlist__last(evlist); > + evlist__set_tracking_event(evlist, tracking_evsel); > + > + tracking_evsel->core.attr.freq = 0; > + tracking_evsel->core.attr.sample_period = 1; > + > + if (!perf_cpu_map__empty(cpus)) > + evsel__set_sample_bit(tracking_evsel, TIME); Same comment as above. > + > + return 0; > +} > + > +static u64 hisi_ptt_reference(struct auxtrace_record *itr __maybe_unused) > +{ > + return rdtsc(); > +} > + > +static void hisi_ptt_recording_free(struct auxtrace_record *itr) > +{ > + struct hisi_ptt_recording *pttr = > + container_of(itr, struct hisi_ptt_recording, itr); > + > + free(pttr); > +} > + > +struct auxtrace_record *hisi_ptt_recording_init(int *err, > + struct perf_pmu *hisi_ptt_pmu) > +{ > + struct hisi_ptt_recording *pttr; > + > + if (!hisi_ptt_pmu) { > + *err = -ENODEV; > + return NULL; > + } > + > + pttr = zalloc(sizeof(struct hisi_ptt_recording)); > + if (!pttr) { > + *err = -ENOMEM; > + return NULL; > + } > + > + pttr->hisi_ptt_pmu = hisi_ptt_pmu; > + pttr->itr.pmu = hisi_ptt_pmu; > + pttr->itr.recording_options = hisi_ptt_recording_options; > + pttr->itr.info_priv_size = hisi_ptt_info_priv_size; > + pttr->itr.info_fill = hisi_ptt_info_fill; > + pttr->itr.free = hisi_ptt_recording_free; > + pttr->itr.reference = hisi_ptt_reference; > + pttr->itr.read_finish = auxtrace_record__read_finish; > + pttr->itr.alignment = 0; > + > + *err = 0; > + return &pttr->itr; > +} > diff --git a/tools/perf/util/Build b/tools/perf/util/Build > index 9a7209a99e16..95d2d76c52da 100644 > --- a/tools/perf/util/Build > +++ b/tools/perf/util/Build > @@ -116,6 +116,8 @@ perf-$(CONFIG_AUXTRACE) += intel-pt.o > perf-$(CONFIG_AUXTRACE) += intel-bts.o > perf-$(CONFIG_AUXTRACE) += arm-spe.o > perf-$(CONFIG_AUXTRACE) += arm-spe-decoder/ > +perf-$(CONFIG_AUXTRACE) += hisi_ptt.o > +perf-$(CONFIG_AUXTRACE) += hisi-ptt-decoder/ > perf-$(CONFIG_AUXTRACE) += s390-cpumsf.o > > ifdef CONFIG_LIBOPENCSD > diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c > index df1c5bbbaa0d..f4841ebaf314 100644 > --- a/tools/perf/util/auxtrace.c > +++ b/tools/perf/util/auxtrace.c > @@ -51,6 +51,7 @@ > #include "intel-pt.h" > #include "intel-bts.h" > #include "arm-spe.h" > +#include "hisi_ptt.h" > #include "s390-cpumsf.h" > #include "util/mmap.h" > > @@ -1281,6 +1282,9 @@ int perf_event__process_auxtrace_info(struct perf_session *session, > case PERF_AUXTRACE_S390_CPUMSF: > err = s390_cpumsf_process_auxtrace_info(event, session); > break; > + case PERF_AUXTRACE_HISI_PTT: > + err = hisi_ptt_process_auxtrace_info(event, session); > + break; > case PERF_AUXTRACE_UNKNOWN: > default: > return -EINVAL; > diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h > index dc38b6f57232..3858c5752ead 100644 > --- a/tools/perf/util/auxtrace.h > +++ b/tools/perf/util/auxtrace.h > @@ -48,6 +48,7 @@ enum auxtrace_type { > PERF_AUXTRACE_CS_ETM, > PERF_AUXTRACE_ARM_SPE, > PERF_AUXTRACE_S390_CPUMSF, > + PERF_AUXTRACE_HISI_PTT, > }; > > enum itrace_period_type { > diff --git a/tools/perf/util/hisi-ptt-decoder/Build b/tools/perf/util/hisi-ptt-decoder/Build > new file mode 100644 > index 000000000000..db3db8b75033 > --- /dev/null > +++ b/tools/perf/util/hisi-ptt-decoder/Build > @@ -0,0 +1 @@ > +perf-$(CONFIG_AUXTRACE) += hisi-ptt-pkt-decoder.o > diff --git a/tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.c b/tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.c > new file mode 100644 > index 000000000000..3fb7a6949209 > --- /dev/null > +++ b/tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.c > @@ -0,0 +1,170 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * HiSilicon PCIe Trace and Tuning (PTT) support > + * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. > + */ > + > +#include <stdlib.h> > +#include <stdio.h> > +#include <string.h> > +#include <endian.h> > +#include <byteswap.h> > +#include <linux/bitops.h> > +#include <stdarg.h> > + > +#include "../color.h" > +#include "hisi-ptt-pkt-decoder.h" > + > +/* > + * For 8DW format, the bit[31:11] of DW0 is always 0x1fffff, which can be > + * used to distinguish the data format. > + * 8DW format is like: > + * bits [ 31:11 ][ 10:0 ] > + * |---------------------------------------|-------------------| > + * DW0 [ 0x1fffff ][ Reserved (0x7ff) ] > + * DW1 [ Prefix ] > + * DW2 [ Header DW0 ] > + * DW3 [ Header DW1 ] > + * DW4 [ Header DW2 ] > + * DW5 [ Header DW3 ] > + * DW6 [ Reserved (0x0) ] > + * DW7 [ Time ] > + * > + * 4DW format is like: > + * bits [31:30] [ 29:25 ][24][23][22][21][ 20:11 ][ 10:0 ] > + * |-----|---------|---|---|---|---|-------------|-------------| > + * DW0 [ Fmt ][ Type ][T9][T8][TH][SO][ Length ][ Time ] > + * DW1 [ Header DW1 ] > + * DW2 [ Header DW2 ] > + * DW3 [ Header DW3 ] > + */ > + > +enum hisi_ptt_8dw_pkt_field_type { > + HISI_PTT_8DW_PREFIX, > + HISI_PTT_8DW_HEAD0, > + HISI_PTT_8DW_HEAD1, > + HISI_PTT_8DW_HEAD2, > + HISI_PTT_8DW_HEAD3, > + HISI_PTT_8DW_TIME, > + HISI_PTT_8DW_TYPE_MAX > +}; > + > +enum hisi_ptt_4dw_pkt_field_type { > + HISI_PTT_4DW_HEAD1, > + HISI_PTT_4DW_HEAD2, > + HISI_PTT_4DW_HEAD3, > + HISI_PTT_4DW_TYPE_MAX > +}; > + > +static const char * const hisi_ptt_8dw_pkt_field_name[] = { > + [HISI_PTT_8DW_PREFIX] = "Prefix", > + [HISI_PTT_8DW_HEAD0] = "Header DW0", > + [HISI_PTT_8DW_HEAD1] = "Header DW1", > + [HISI_PTT_8DW_HEAD2] = "Header DW2", > + [HISI_PTT_8DW_HEAD3] = "Header DW3", > + [HISI_PTT_8DW_TIME] = "Time", > +}; > + > +static const char * const hisi_ptt_4dw_pkt_field_name[] = { > + [HISI_PTT_4DW_HEAD1] = "Header DW1", > + [HISI_PTT_4DW_HEAD2] = "Header DW2", > + [HISI_PTT_4DW_HEAD3] = "Header DW3", > +}; > + > +/* offset of each member is determined by format of 8dw packet. */ > +static uint32_t hisi_ptt_8dw_pkt_field_offset[] = { > + [HISI_PTT_8DW_PREFIX] = 4, > + [HISI_PTT_8DW_HEAD0] = 4, > + [HISI_PTT_8DW_HEAD1] = 4, > + [HISI_PTT_8DW_HEAD2] = 4, > + [HISI_PTT_8DW_HEAD3] = 4, > + [HISI_PTT_8DW_TIME] = 8, > +}; > + > +union hisi_ptt_4dw { > + struct { > + uint32_t format : 2; > + uint32_t type : 5; > + uint32_t t9 : 1; > + uint32_t t8 : 1; > + uint32_t th : 1; > + uint32_t so : 1; > + uint32_t len : 10; > + uint32_t time : 11; > + }; > + uint32_t value; > +}; > + > +static void hisi_ptt_print_pkt(const unsigned char *buf, int *pos, const char *desc) > +{ > + const char *color = PERF_COLOR_BLUE; > + int field_len = sizeof(uint32_t); > + int i; > + > + printf("."); > + color_fprintf(stdout, color, " %08x: ", *pos); > + for (i = 0; i < field_len; i++) > + color_fprintf(stdout, color, "%02x ", buf[i]); > + for (i = 0; i < HISI_PTT_MAX_SPACE_LEN; i++) > + color_fprintf(stdout, color, " "); > + color_fprintf(stdout, color, " %s\n", desc); > + *pos += field_len; > +} > + > +static int hisi_ptt_8dw_kpt_desc(const unsigned char *buf, int pos) > +{ > + int i; > + > + for (i = HISI_PTT_8DW_PREFIX; i < HISI_PTT_8DW_TYPE_MAX; i++) { > + buf += hisi_ptt_8dw_pkt_field_offset[i]; > + hisi_ptt_print_pkt(buf, &pos, hisi_ptt_8dw_pkt_field_name[i]); > + } > + > + return HISI_PTT_8DW_PKT_SIZE; > +} > + > +static void hisi_ptt_4dw_print_dw0(const unsigned char *buf, int *pos) > +{ > + const char *color = PERF_COLOR_BLUE; > + int field_len = sizeof(uint32_t); > + union hisi_ptt_4dw dw0; > + int i; > + > + dw0.value = *(uint32_t *)buf; > + printf("."); > + color_fprintf(stdout, color, " %08x: ", *pos); > + for (i = 0; i < field_len; i++) > + color_fprintf(stdout, color, "%02x ", buf[i]); > + for (i = 0; i < HISI_PTT_MAX_SPACE_LEN; i++) > + color_fprintf(stdout, color, " "); > + > + color_fprintf(stdout, color, > + " %s %x %s %x %s %x %s %x %s %x %s %x %s %x %s %x\n", > + "Format", dw0.format, "Type", dw0.type, "T9", dw0.t9, > + "T8", dw0.t8, "TH", dw0.th, "SO", dw0.so, "Length", > + dw0.len, "Time", dw0.time); > + > + *pos += field_len; > +} > + > +static int hisi_ptt_4dw_kpt_desc(const unsigned char *buf, int pos) > +{ > + int i; > + > + hisi_ptt_4dw_print_dw0(buf, &pos); > + > + for (i = HISI_PTT_4DW_HEAD1; i < HISI_PTT_4DW_TYPE_MAX; i++) { > + buf += sizeof(uint32_t); > + hisi_ptt_print_pkt(buf, &pos, hisi_ptt_4dw_pkt_field_name[i]); > + } > + > + return HISI_PTT_4DW_PKT_SIZE; > +} > + > +int hisi_ptt_pkt_desc(const unsigned char *buf, int pos, enum hisi_ptt_pkt_type type) > +{ > + if (type == HISI_PTT_8DW_PKT) > + return hisi_ptt_8dw_kpt_desc(buf, pos); > + > + return hisi_ptt_4dw_kpt_desc(buf, pos); > +} > diff --git a/tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.h b/tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.h > new file mode 100644 > index 000000000000..20c51f230cac > --- /dev/null > +++ b/tools/perf/util/hisi-ptt-decoder/hisi-ptt-pkt-decoder.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * HiSilicon PCIe Trace and Tuning (PTT) support > + * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. > + */ > + > +#ifndef INCLUDE__HISI_PTT_PKT_DECODER_H__ > +#define INCLUDE__HISI_PTT_PKT_DECODER_H__ > + > +#include <stddef.h> > +#include <stdint.h> > + > +#define HISI_PTT_PKT_DESC_MAX 256 > +#define HISI_PTT_NEED_MORE_BYTES -1 > +#define HISI_PTT_8DW_CHECK_MASK GENMASK(31, 11) > +#define HISI_PTT_IS_8DW_PKT GENMASK(31, 11) > +#define HISI_PTT_8DW_PKT_SIZE 32 > +#define HISI_PTT_4DW_PKT_SIZE 16 > +#define HISI_PTT_MAX_SPACE_LEN 10 > + > +enum hisi_ptt_pkt_type { > + HISI_PTT_4DW_PKT, > + HISI_PTT_8DW_PKT, > +}; > + > +int hisi_ptt_pkt_desc(const unsigned char *buf, int pos, enum hisi_ptt_pkt_type type); > + > +#endif > diff --git a/tools/perf/util/hisi_ptt.c b/tools/perf/util/hisi_ptt.c > new file mode 100644 > index 000000000000..e2934214763c > --- /dev/null > +++ b/tools/perf/util/hisi_ptt.c > @@ -0,0 +1,218 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * HiSilicon PCIe Trace and Tuning (PTT) support > + * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. > + */ > + > +#include <byteswap.h> > +#include <endian.h> > +#include <errno.h> > +#include <inttypes.h> > +#include <linux/bitops.h> > +#include <linux/kernel.h> > +#include <linux/log2.h> > +#include <linux/types.h> > +#include <linux/zalloc.h> > +#include <stdlib.h> > +#include <unistd.h> > + > +#include "auxtrace.h" > +#include "color.h" > +#include "debug.h" > +#include "evlist.h" > +#include "evsel.h" > +#include "hisi_ptt.h" > +#include "hisi-ptt-decoder/hisi-ptt-pkt-decoder.h" > +#include "machine.h" > +#include "session.h" > +#include "symbol.h" > +#include "tool.h" > +#include "util/synthetic-events.h" > + > +struct hisi_ptt { > + struct auxtrace auxtrace; > + struct auxtrace_queues queues; > + u32 auxtrace_type; > + struct perf_session *session; > + struct machine *machine; > + u32 pmu_type; > +}; > + > +struct hisi_ptt_queue { > + struct hisi_ptt *ptt; > + struct auxtrace_buffer *buffer; > +}; > + > +static enum hisi_ptt_pkt_type hisi_ptt_check_packet_type(unsigned char *buf) > +{ > + uint32_t head = *(uint32_t *)buf; > + > + if ((HISI_PTT_8DW_CHECK_MASK & head) == HISI_PTT_IS_8DW_PKT) > + return HISI_PTT_8DW_PKT; > + > + return HISI_PTT_4DW_PKT; > +} > + > +static void hisi_ptt_dump(struct hisi_ptt *ptt __maybe_unused, > + unsigned char *buf, size_t len) > +{ > + const char *color = PERF_COLOR_BLUE; > + enum hisi_ptt_pkt_type type; > + size_t pos = 0; > + int pkt_len; > + > + color_fprintf(stdout, color, ". ... HISI PTT data: size %zu bytes\n", > + len); > + > + type = hisi_ptt_check_packet_type(buf); > + while (len) { > + pkt_len = hisi_ptt_pkt_desc(buf, pos, type); > + if (!pkt_len) > + color_fprintf(stdout, color, " Bad packet!\n"); > + > + pos += pkt_len; > + buf += pkt_len; > + len -= pkt_len; > + } > +} > + > +static void hisi_ptt_dump_event(struct hisi_ptt *ptt, unsigned char *buf, > + size_t len) > +{ > + printf(".\n"); > + > + hisi_ptt_dump(ptt, buf, len); > +} > + > +static int hisi_ptt_process_event(struct perf_session *session __maybe_unused, > + union perf_event *event __maybe_unused, > + struct perf_sample *sample __maybe_unused, > + struct perf_tool *tool __maybe_unused) > +{ > + return 0; > +} > + > +static int hisi_ptt_process_auxtrace_event(struct perf_session *session, > + union perf_event *event, > + struct perf_tool *tool __maybe_unused) > +{ > + struct hisi_ptt *ptt = container_of(session->auxtrace, struct hisi_ptt, > + auxtrace); > + struct auxtrace_buffer *buffer; > + off_t data_offset; > + int fd = perf_data__fd(session->data); > + int err; > + > + if (perf_data__is_pipe(session->data)) { > + data_offset = 0; > + } else { > + data_offset = lseek(fd, 0, SEEK_CUR); > + if (data_offset == -1) > + return -errno; > + } > + > + err = auxtrace_queues__add_event(&ptt->queues, session, event, > + data_offset, &buffer); > + if (err) > + return err; > + > + if (dump_trace) { > + if (auxtrace_buffer__get_data(buffer, fd)) { > + hisi_ptt_dump_event(ptt, buffer->data, buffer->size); > + auxtrace_buffer__put_data(buffer); > + } Technically auxtrace_queues aren't required here because they are more for supporting trace from multiple CPUs and sorting and re-ordering between them. If this is new device is uncore and always from a single source you could just go straight to hisi_ptt_dump_event() with data_offset and size of the auxtrace event. But I suppose it also doesn't hurt to use some of the existing framework like you have done. > + } > + > + return 0; > +} > + > +static int hisi_ptt_flush(struct perf_session *session __maybe_unused, > + struct perf_tool *tool __maybe_unused) > +{ > + return 0; > +} > + > +static void hisi_ptt_free_events(struct perf_session *session) > +{ > + struct hisi_ptt *ptt = container_of(session->auxtrace, struct hisi_ptt, > + auxtrace); > + struct auxtrace_queues *queues = &ptt->queues; > + unsigned int i; > + > + for (i = 0; i < queues->nr_queues; i++) { > + free(queues->queue_array[i].priv); > + queues->queue_array[i].priv = NULL; > + } > + auxtrace_queues__free(queues); > +} > + > +static void hisi_ptt_free(struct perf_session *session) > +{ > + struct hisi_ptt *ptt = container_of(session->auxtrace, struct hisi_ptt, > + auxtrace); > + > + hisi_ptt_free_events(session); > + session->auxtrace = NULL; > + free(ptt); > +} > + > +static bool hisi_ptt_evsel_is_auxtrace(struct perf_session *session, > + struct evsel *evsel) > +{ > + struct hisi_ptt *ptt = container_of(session->auxtrace, struct hisi_ptt, auxtrace); > + > + return evsel->core.attr.type == ptt->pmu_type; > +} > + > +static const char * const hisi_ptt_info_fmts[] = { > + [HISI_PTT_PMU_TYPE] = " PMU Type %" PRId64 "\n", > +}; > + > +static void hisi_ptt_print_info(__u64 *arr) > +{ > + if (!dump_trace) > + return; > + > + fprintf(stdout, hisi_ptt_info_fmts[HISI_PTT_PMU_TYPE], arr[HISI_PTT_PMU_TYPE]); > +} > + > +int hisi_ptt_process_auxtrace_info(union perf_event *event, > + struct perf_session *session) > +{ > + struct perf_record_auxtrace_info *auxtrace_info = &event->auxtrace_info; > + struct hisi_ptt *ptt; > + int err; > + > + if (auxtrace_info->header.size < HISI_PTT_AUXTRACE_PRIV_SIZE + > + sizeof(struct perf_record_auxtrace_info)) > + return -EINVAL; > + > + ptt = zalloc(sizeof(struct hisi_ptt)); > + if (!ptt) > + return -ENOMEM; > + > + err = auxtrace_queues__init(&ptt->queues); > + if (err) > + goto err_free; > + > + ptt->session = session; > + ptt->machine = &session->machines.host; /* No kvm support */ > + ptt->auxtrace_type = auxtrace_info->type; > + ptt->pmu_type = auxtrace_info->priv[HISI_PTT_PMU_TYPE]; > + > + ptt->auxtrace.process_event = hisi_ptt_process_event; > + ptt->auxtrace.process_auxtrace_event = hisi_ptt_process_auxtrace_event; > + ptt->auxtrace.flush_events = hisi_ptt_flush; > + ptt->auxtrace.free_events = hisi_ptt_free_events; > + ptt->auxtrace.free = hisi_ptt_free; > + ptt->auxtrace.evsel_is_auxtrace = hisi_ptt_evsel_is_auxtrace; > + session->auxtrace = &ptt->auxtrace; > + > + hisi_ptt_print_info(&auxtrace_info->priv[0]); > + > + return 0; > + > +err_free: > + free(ptt); > + return err; > +} > diff --git a/tools/perf/util/hisi_ptt.h b/tools/perf/util/hisi_ptt.h > new file mode 100644 > index 000000000000..c0b6cbde1221 > --- /dev/null > +++ b/tools/perf/util/hisi_ptt.h > @@ -0,0 +1,28 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * HiSilicon PCIe Trace and Tuning (PTT) support > + * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. > + */ > + > +#ifndef INCLUDE__PERF_HISI_PTT_H__ > +#define INCLUDE__PERF_HISI_PTT_H__ > + > +#define HISI_PTT_PMU_NAME "hisi_ptt" > +enum { > + HISI_PTT_PMU_TYPE, > + HISI_PTT_PER_CPU_MMAPS, > + HISI_PTT_AUXTRACE_PRIV_MAX, > +}; > + > +#define HISI_PTT_AUXTRACE_PRIV_SIZE (HISI_PTT_AUXTRACE_PRIV_MAX * sizeof(u64)) > +union perf_event; > +struct perf_session; > +struct perf_pmu; > + > +struct auxtrace_record *hisi_ptt_recording_init(int *err, > + struct perf_pmu *hisi_ptt_pmu); > + > +int hisi_ptt_process_auxtrace_info(union perf_event *event, > + struct perf_session *session); > + > +#endif

3 years, 1 month

Re: [PATCH v7 2/7] hwtracing: Add trace function support for HiSilicon PCIe Tune and Trace device

by James Clark

On 10/05/2022 12:18, Yicong Yang wrote: > On 2022/5/10 17:46, James Clark wrote: >> >> >> On 07/04/2022 13:58, Yicong Yang wrote: >>> HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex integrated >>> Endpoint(RCiEP) device, providing the capability to dynamically monitor and >>> tune the PCIe traffic, and trace the TLP headers. >>> >>> Add the driver for the device to enable the trace function. Register PMU >>> device of PTT trace, then users can use trace through perf command. The >>> driver makes use of perf AUX trace and support following events to >>> configure the trace: >>> >>> - filter: select Root port or Endpoint to trace >>> - type: select the type of traced TLP headers >>> - direction: select the direction of traced TLP headers >>> - format: select the data format of the traced TLP headers >>> >>> This patch adds the driver part of PTT trace. The perf command support of >>> PTT trace is added in the following patch. >>> >>> Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> >>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> >>> --- >>> drivers/Makefile | 1 + >>> drivers/hwtracing/Kconfig | 2 + >>> drivers/hwtracing/ptt/Kconfig | 12 + >>> drivers/hwtracing/ptt/Makefile | 2 + >>> drivers/hwtracing/ptt/hisi_ptt.c | 874 +++++++++++++++++++++++++++++++ >>> drivers/hwtracing/ptt/hisi_ptt.h | 166 ++++++ >>> 6 files changed, 1057 insertions(+) >>> create mode 100644 drivers/hwtracing/ptt/Kconfig >>> create mode 100644 drivers/hwtracing/ptt/Makefile >>> create mode 100644 drivers/hwtracing/ptt/hisi_ptt.c >>> create mode 100644 drivers/hwtracing/ptt/hisi_ptt.h >>> >>> diff --git a/drivers/Makefile b/drivers/Makefile >>> index 020780b6b4d2..662d50599467 100644 >>> --- a/drivers/Makefile >>> +++ b/drivers/Makefile >>> @@ -175,6 +175,7 @@ obj-$(CONFIG_USB4) += thunderbolt/ >>> obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/ >>> obj-y += hwtracing/intel_th/ >>> obj-$(CONFIG_STM) += hwtracing/stm/ >>> +obj-$(CONFIG_HISI_PTT) += hwtracing/ptt/ >>> obj-$(CONFIG_ANDROID) += android/ >>> obj-$(CONFIG_NVMEM) += nvmem/ >>> obj-$(CONFIG_FPGA) += fpga/ >>> diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig >>> index 13085835a636..911ee977103c 100644 >>> --- a/drivers/hwtracing/Kconfig >>> +++ b/drivers/hwtracing/Kconfig >>> @@ -5,4 +5,6 @@ source "drivers/hwtracing/stm/Kconfig" >>> >>> source "drivers/hwtracing/intel_th/Kconfig" >>> >>> +source "drivers/hwtracing/ptt/Kconfig" >>> + >>> endmenu >>> diff --git a/drivers/hwtracing/ptt/Kconfig b/drivers/hwtracing/ptt/Kconfig >>> new file mode 100644 >>> index 000000000000..8902a6f27563 >>> --- /dev/null >>> +++ b/drivers/hwtracing/ptt/Kconfig >>> @@ -0,0 +1,12 @@ >>> +# SPDX-License-Identifier: GPL-2.0-only >>> +config HISI_PTT >>> + tristate "HiSilicon PCIe Tune and Trace Device" >>> + depends on ARM64 || (COMPILE_TEST && 64BIT) >>> + depends on PCI && HAS_DMA && HAS_IOMEM && PERF_EVENTS >>> + help >>> + HiSilicon PCIe Tune and Trace Device exists as a PCIe RCiEP >>> + device, and it provides support for PCIe traffic tuning and >>> + tracing TLP headers to the memory. >>> + >>> + This driver can also be built as a module. If so, the module >>> + will be called hisi_ptt. >>> diff --git a/drivers/hwtracing/ptt/Makefile b/drivers/hwtracing/ptt/Makefile >>> new file mode 100644 >>> index 000000000000..908c09a98161 >>> --- /dev/null >>> +++ b/drivers/hwtracing/ptt/Makefile >>> @@ -0,0 +1,2 @@ >>> +# SPDX-License-Identifier: GPL-2.0 >>> +obj-$(CONFIG_HISI_PTT) += hisi_ptt.o >>> diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c >>> new file mode 100644 >>> index 000000000000..242b41870380 >>> --- /dev/null >>> +++ b/drivers/hwtracing/ptt/hisi_ptt.c >>> @@ -0,0 +1,874 @@ >>> +// SPDX-License-Identifier: GPL-2.0 >>> +/* >>> + * Driver for HiSilicon PCIe tune and trace device >>> + * >>> + * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. >>> + * Author: Yicong Yang <yangyicong(a)hisilicon.com> >>> + */ >>> + >>> +#include <linux/bitfield.h> >>> +#include <linux/bitops.h> >>> +#include <linux/delay.h> >>> +#include <linux/dma-iommu.h> >>> +#include <linux/dma-mapping.h> >>> +#include <linux/interrupt.h> >>> +#include <linux/io.h> >>> +#include <linux/iommu.h> >>> +#include <linux/iopoll.h> >>> +#include <linux/module.h> >>> +#include <linux/sysfs.h> >>> +#include <linux/vmalloc.h> >>> + >>> +#include "hisi_ptt.h" >>> + >>> +static u16 hisi_ptt_get_filter_val(struct pci_dev *pdev) >>> +{ >>> + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) >>> + return BIT(HISI_PCIE_CORE_PORT_ID(PCI_SLOT(pdev->devfn))); >>> + >>> + return PCI_DEVID(pdev->bus->number, pdev->devfn); >>> +} >>> + >>> +static bool hisi_ptt_wait_trace_hw_idle(struct hisi_ptt *hisi_ptt) >>> +{ >>> + u32 val; >>> + >>> + return !readl_poll_timeout_atomic(hisi_ptt->iobase + HISI_PTT_TRACE_STS, >>> + val, val & HISI_PTT_TRACE_IDLE, >>> + HISI_PTT_WAIT_POLL_INTERVAL_US, >>> + HISI_PTT_WAIT_TRACE_TIMEOUT_US); >>> +} >>> + >>> +static bool hisi_ptt_wait_dma_reset_done(struct hisi_ptt *hisi_ptt) >>> +{ >>> + u32 val; >>> + >>> + return !readl_poll_timeout_atomic(hisi_ptt->iobase + HISI_PTT_TRACE_WR_STS, >>> + val, !val, HISI_PTT_RESET_POLL_INTERVAL_US, >>> + HISI_PTT_RESET_TIMEOUT_US); >>> +} >>> + >>> +static void hisi_ptt_free_trace_buf(struct hisi_ptt *hisi_ptt) >>> +{ >>> + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; >>> + struct device *dev = &hisi_ptt->pdev->dev; >>> + int i; >>> + >>> + if (!ctrl->trace_buf) >>> + return; >>> + >>> + for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++) { >>> + if (ctrl->trace_buf[i].addr) >>> + dmam_free_coherent(dev, HISI_PTT_TRACE_BUF_SIZE, >>> + ctrl->trace_buf[i].addr, >>> + ctrl->trace_buf[i].dma); >>> + } >>> + >>> + devm_kfree(dev, ctrl->trace_buf); >>> + ctrl->trace_buf = NULL; >>> +} >>> + >>> +static int hisi_ptt_alloc_trace_buf(struct hisi_ptt *hisi_ptt) >>> +{ >>> + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; >>> + struct device *dev = &hisi_ptt->pdev->dev; >>> + int i; >>> + >>> + hisi_ptt->trace_ctrl.buf_index = 0; >>> + >>> + /* If the trace buffer has already been allocated, zero it. */ >>> + if (ctrl->trace_buf) { >>> + for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++) >>> + memset(ctrl->trace_buf[i].addr, 0, HISI_PTT_TRACE_BUF_SIZE); >>> + return 0; >>> + } >>> + >>> + ctrl->trace_buf = devm_kcalloc(dev, HISI_PTT_TRACE_BUF_CNT, >>> + sizeof(struct hisi_ptt_dma_buffer), GFP_KERNEL); >>> + if (!ctrl->trace_buf) >>> + return -ENOMEM; >>> + >>> + for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; ++i) { >>> + ctrl->trace_buf[i].addr = dmam_alloc_coherent(dev, HISI_PTT_TRACE_BUF_SIZE, >>> + &ctrl->trace_buf[i].dma, >>> + GFP_KERNEL); >>> + if (!ctrl->trace_buf[i].addr) { >>> + hisi_ptt_free_trace_buf(hisi_ptt); >>> + return -ENOMEM; >>> + } >>> + } >>> + >>> + return 0; >>> +} >>> + >>> +static void hisi_ptt_trace_end(struct hisi_ptt *hisi_ptt) >>> +{ >>> + writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); >>> + hisi_ptt->trace_ctrl.started = false; >>> +} >>> + >>> +static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt) >>> +{ >>> + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; >>> + u32 val; >>> + int i; >>> + >>> + /* Check device idle before start trace */ >>> + if (!hisi_ptt_wait_trace_hw_idle(hisi_ptt)) { >>> + pci_err(hisi_ptt->pdev, "Failed to start trace, the device is still busy\n"); >>> + return -EBUSY; >>> + } >>> + >>> + ctrl->started = true; >>> + >>> + /* Reset the DMA before start tracing */ >>> + val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); >>> + val |= HISI_PTT_TRACE_CTRL_RST; >>> + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); >>> + >>> + hisi_ptt_wait_dma_reset_done(hisi_ptt); >>> + >>> + val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); >>> + val &= ~HISI_PTT_TRACE_CTRL_RST; >>> + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); >>> + >>> + /* Clear the interrupt status */ >>> + writel(HISI_PTT_TRACE_INT_STAT_MASK, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); >>> + writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK); >>> + >>> + /* Configure the trace DMA buffer */ >>> + for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++) { >>> + writel(lower_32_bits(ctrl->trace_buf[i].dma), >>> + hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_LO_0 + >>> + i * HISI_PTT_TRACE_ADDR_STRIDE); >>> + writel(upper_32_bits(ctrl->trace_buf[i].dma), >>> + hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_HI_0 + >>> + i * HISI_PTT_TRACE_ADDR_STRIDE); >>> + } >>> + writel(HISI_PTT_TRACE_BUF_SIZE, hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_SIZE); >>> + >>> + /* Set the trace control register */ >>> + val = FIELD_PREP(HISI_PTT_TRACE_CTRL_TYPE_SEL, ctrl->type); >>> + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_RXTX_SEL, ctrl->direction); >>> + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_DATA_FORMAT, ctrl->format); >>> + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_TARGET_SEL, hisi_ptt->trace_ctrl.filter); >>> + if (!hisi_ptt->trace_ctrl.is_port) >>> + val |= HISI_PTT_TRACE_CTRL_FILTER_MODE; >>> + >>> + /* Start the Trace */ >>> + val |= HISI_PTT_TRACE_CTRL_EN; >>> + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); >>> + >>> + return 0; >>> +} >>> + >>> +static int hisi_ptt_update_aux(struct hisi_ptt *hisi_ptt, int index, bool stop) >>> +{ >>> + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; >>> + struct perf_output_handle *handle = &ctrl->handle; >>> + struct perf_event *event = handle->event; >>> + struct hisi_ptt_pmu_buf *buf; >>> + void *addr; >>> + >>> + buf = perf_get_aux(handle); >>> + if (!buf || !handle->size) >>> + return -EINVAL; >>> + >>> + addr = ctrl->trace_buf[ctrl->buf_index].addr; >>> + >>> + memcpy(buf->base + buf->pos, addr, HISI_PTT_TRACE_BUF_SIZE); >>> + memset(addr, 0, HISI_PTT_TRACE_BUF_SIZE); >> >> Hi Kicong, >> >> I also have the same comment as Leo here, I don't think the memset is >> required. >> > > It's necessary in the current approach as we always commit HISI_PTT_TRACE_BUF_SIZE > data but the buffer maybe partly filled (called when perf going to stopp, not by the > interrupt). The buffer is cleared so the unfilled part of the buffer will have > empty data (normal traced TLP headers won't be all 0), then the user can distinguish > the valid part of the data. > > I'm trying to only copy the traced data rather than the whole buffer then the > clear operation here will be unnecessary. The hardware provide a register indicating > which offset of which buffer it's currently writing to and it canbe used here. If only the traced data is copied rather than the full buffer, isn't that what perf_aux_output_end() is for? Perf will only read up to the point where you say the buffer is filled to, it won't go and read the zeros if you didn't tell it to by emitting perf_aux_output_end() for more data than was written. If you are having to write zeros to detect which bits of the buffer is filled or not it sounds like those zero parts are making it into the perf file and are wasting disk space and CPU cycles to copy them. > >>> + buf->pos += HISI_PTT_TRACE_BUF_SIZE; >>> + >>> + if (stop) { >>> + perf_aux_output_end(handle, buf->pos); >>> + } else if (buf->length - buf->pos < HISI_PTT_TRACE_BUF_SIZE) { >>> + perf_aux_output_skip(handle, buf->length - buf->pos); >> >> perf_aux_output_skip() can also return an error so should probably also >> be checked like perf_aux_output_begin() >> > > ok it should be checked. > >> I'm also wondering why there is a skip for every output_end()? Is that >> to avoid having two memcpy calls to handle the wrap around if the data >> to be copied goes past the end of the aux buffer? >> >> For example if your buffers are 4MB each and the aux buffer that the >> user picked isn't a multiple of 4 I can see you needing to write the >> first part of the 4MB to the end of the aux buffer and then the last >> part to the beginning which would be two memcpy() calls. And then a >> skip wouldn't be required. >> > > I intended to handle the case that AUX buffer is not a multiple of 4 MiB. > When the resident AUX buffer size is less than 4MiB, we're not going to > commit data to it and will apply a new AUX buffer instead. I think you're > right that the perf_aux_output_skip() is unnecessary here. Thanks for > catching this. > >> I looked at all the other uses of perf_output_end() and perf_output_skip() >> in the kernel and didn't see a pattern like yours so it seems suspicous to >> me. Maybe at least some comments around this section are needed. >> > > Will add some comments of the handling here. > > Regards, > Yicong

3 years, 1 month

Re: [PATCH v7 2/7] hwtracing: Add trace function support for HiSilicon PCIe Tune and Trace device

by James Clark

On 07/04/2022 13:58, Yicong Yang wrote: > HiSilicon PCIe tune and trace device(PTT) is a PCIe Root Complex integrated > Endpoint(RCiEP) device, providing the capability to dynamically monitor and > tune the PCIe traffic, and trace the TLP headers. > > Add the driver for the device to enable the trace function. Register PMU > device of PTT trace, then users can use trace through perf command. The > driver makes use of perf AUX trace and support following events to > configure the trace: > > - filter: select Root port or Endpoint to trace > - type: select the type of traced TLP headers > - direction: select the direction of traced TLP headers > - format: select the data format of the traced TLP headers > > This patch adds the driver part of PTT trace. The perf command support of > PTT trace is added in the following patch. > > Signed-off-by: Yicong Yang <yangyicong(a)hisilicon.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron(a)huawei.com> > --- > drivers/Makefile | 1 + > drivers/hwtracing/Kconfig | 2 + > drivers/hwtracing/ptt/Kconfig | 12 + > drivers/hwtracing/ptt/Makefile | 2 + > drivers/hwtracing/ptt/hisi_ptt.c | 874 +++++++++++++++++++++++++++++++ > drivers/hwtracing/ptt/hisi_ptt.h | 166 ++++++ > 6 files changed, 1057 insertions(+) > create mode 100644 drivers/hwtracing/ptt/Kconfig > create mode 100644 drivers/hwtracing/ptt/Makefile > create mode 100644 drivers/hwtracing/ptt/hisi_ptt.c > create mode 100644 drivers/hwtracing/ptt/hisi_ptt.h > > diff --git a/drivers/Makefile b/drivers/Makefile > index 020780b6b4d2..662d50599467 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -175,6 +175,7 @@ obj-$(CONFIG_USB4) += thunderbolt/ > obj-$(CONFIG_CORESIGHT) += hwtracing/coresight/ > obj-y += hwtracing/intel_th/ > obj-$(CONFIG_STM) += hwtracing/stm/ > +obj-$(CONFIG_HISI_PTT) += hwtracing/ptt/ > obj-$(CONFIG_ANDROID) += android/ > obj-$(CONFIG_NVMEM) += nvmem/ > obj-$(CONFIG_FPGA) += fpga/ > diff --git a/drivers/hwtracing/Kconfig b/drivers/hwtracing/Kconfig > index 13085835a636..911ee977103c 100644 > --- a/drivers/hwtracing/Kconfig > +++ b/drivers/hwtracing/Kconfig > @@ -5,4 +5,6 @@ source "drivers/hwtracing/stm/Kconfig" > > source "drivers/hwtracing/intel_th/Kconfig" > > +source "drivers/hwtracing/ptt/Kconfig" > + > endmenu > diff --git a/drivers/hwtracing/ptt/Kconfig b/drivers/hwtracing/ptt/Kconfig > new file mode 100644 > index 000000000000..8902a6f27563 > --- /dev/null > +++ b/drivers/hwtracing/ptt/Kconfig > @@ -0,0 +1,12 @@ > +# SPDX-License-Identifier: GPL-2.0-only > +config HISI_PTT > + tristate "HiSilicon PCIe Tune and Trace Device" > + depends on ARM64 || (COMPILE_TEST && 64BIT) > + depends on PCI && HAS_DMA && HAS_IOMEM && PERF_EVENTS > + help > + HiSilicon PCIe Tune and Trace Device exists as a PCIe RCiEP > + device, and it provides support for PCIe traffic tuning and > + tracing TLP headers to the memory. > + > + This driver can also be built as a module. If so, the module > + will be called hisi_ptt. > diff --git a/drivers/hwtracing/ptt/Makefile b/drivers/hwtracing/ptt/Makefile > new file mode 100644 > index 000000000000..908c09a98161 > --- /dev/null > +++ b/drivers/hwtracing/ptt/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +obj-$(CONFIG_HISI_PTT) += hisi_ptt.o > diff --git a/drivers/hwtracing/ptt/hisi_ptt.c b/drivers/hwtracing/ptt/hisi_ptt.c > new file mode 100644 > index 000000000000..242b41870380 > --- /dev/null > +++ b/drivers/hwtracing/ptt/hisi_ptt.c > @@ -0,0 +1,874 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Driver for HiSilicon PCIe tune and trace device > + * > + * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. > + * Author: Yicong Yang <yangyicong(a)hisilicon.com> > + */ > + > +#include <linux/bitfield.h> > +#include <linux/bitops.h> > +#include <linux/delay.h> > +#include <linux/dma-iommu.h> > +#include <linux/dma-mapping.h> > +#include <linux/interrupt.h> > +#include <linux/io.h> > +#include <linux/iommu.h> > +#include <linux/iopoll.h> > +#include <linux/module.h> > +#include <linux/sysfs.h> > +#include <linux/vmalloc.h> > + > +#include "hisi_ptt.h" > + > +static u16 hisi_ptt_get_filter_val(struct pci_dev *pdev) > +{ > + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) > + return BIT(HISI_PCIE_CORE_PORT_ID(PCI_SLOT(pdev->devfn))); > + > + return PCI_DEVID(pdev->bus->number, pdev->devfn); > +} > + > +static bool hisi_ptt_wait_trace_hw_idle(struct hisi_ptt *hisi_ptt) > +{ > + u32 val; > + > + return !readl_poll_timeout_atomic(hisi_ptt->iobase + HISI_PTT_TRACE_STS, > + val, val & HISI_PTT_TRACE_IDLE, > + HISI_PTT_WAIT_POLL_INTERVAL_US, > + HISI_PTT_WAIT_TRACE_TIMEOUT_US); > +} > + > +static bool hisi_ptt_wait_dma_reset_done(struct hisi_ptt *hisi_ptt) > +{ > + u32 val; > + > + return !readl_poll_timeout_atomic(hisi_ptt->iobase + HISI_PTT_TRACE_WR_STS, > + val, !val, HISI_PTT_RESET_POLL_INTERVAL_US, > + HISI_PTT_RESET_TIMEOUT_US); > +} > + > +static void hisi_ptt_free_trace_buf(struct hisi_ptt *hisi_ptt) > +{ > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + struct device *dev = &hisi_ptt->pdev->dev; > + int i; > + > + if (!ctrl->trace_buf) > + return; > + > + for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++) { > + if (ctrl->trace_buf[i].addr) > + dmam_free_coherent(dev, HISI_PTT_TRACE_BUF_SIZE, > + ctrl->trace_buf[i].addr, > + ctrl->trace_buf[i].dma); > + } > + > + devm_kfree(dev, ctrl->trace_buf); > + ctrl->trace_buf = NULL; > +} > + > +static int hisi_ptt_alloc_trace_buf(struct hisi_ptt *hisi_ptt) > +{ > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + struct device *dev = &hisi_ptt->pdev->dev; > + int i; > + > + hisi_ptt->trace_ctrl.buf_index = 0; > + > + /* If the trace buffer has already been allocated, zero it. */ > + if (ctrl->trace_buf) { > + for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++) > + memset(ctrl->trace_buf[i].addr, 0, HISI_PTT_TRACE_BUF_SIZE); > + return 0; > + } > + > + ctrl->trace_buf = devm_kcalloc(dev, HISI_PTT_TRACE_BUF_CNT, > + sizeof(struct hisi_ptt_dma_buffer), GFP_KERNEL); > + if (!ctrl->trace_buf) > + return -ENOMEM; > + > + for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; ++i) { > + ctrl->trace_buf[i].addr = dmam_alloc_coherent(dev, HISI_PTT_TRACE_BUF_SIZE, > + &ctrl->trace_buf[i].dma, > + GFP_KERNEL); > + if (!ctrl->trace_buf[i].addr) { > + hisi_ptt_free_trace_buf(hisi_ptt); > + return -ENOMEM; > + } > + } > + > + return 0; > +} > + > +static void hisi_ptt_trace_end(struct hisi_ptt *hisi_ptt) > +{ > + writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + hisi_ptt->trace_ctrl.started = false; > +} > + > +static int hisi_ptt_trace_start(struct hisi_ptt *hisi_ptt) > +{ > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + u32 val; > + int i; > + > + /* Check device idle before start trace */ > + if (!hisi_ptt_wait_trace_hw_idle(hisi_ptt)) { > + pci_err(hisi_ptt->pdev, "Failed to start trace, the device is still busy\n"); > + return -EBUSY; > + } > + > + ctrl->started = true; > + > + /* Reset the DMA before start tracing */ > + val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + val |= HISI_PTT_TRACE_CTRL_RST; > + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + > + hisi_ptt_wait_dma_reset_done(hisi_ptt); > + > + val = readl(hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + val &= ~HISI_PTT_TRACE_CTRL_RST; > + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + > + /* Clear the interrupt status */ > + writel(HISI_PTT_TRACE_INT_STAT_MASK, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > + writel(0, hisi_ptt->iobase + HISI_PTT_TRACE_INT_MASK); > + > + /* Configure the trace DMA buffer */ > + for (i = 0; i < HISI_PTT_TRACE_BUF_CNT; i++) { > + writel(lower_32_bits(ctrl->trace_buf[i].dma), > + hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_LO_0 + > + i * HISI_PTT_TRACE_ADDR_STRIDE); > + writel(upper_32_bits(ctrl->trace_buf[i].dma), > + hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_BASE_HI_0 + > + i * HISI_PTT_TRACE_ADDR_STRIDE); > + } > + writel(HISI_PTT_TRACE_BUF_SIZE, hisi_ptt->iobase + HISI_PTT_TRACE_ADDR_SIZE); > + > + /* Set the trace control register */ > + val = FIELD_PREP(HISI_PTT_TRACE_CTRL_TYPE_SEL, ctrl->type); > + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_RXTX_SEL, ctrl->direction); > + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_DATA_FORMAT, ctrl->format); > + val |= FIELD_PREP(HISI_PTT_TRACE_CTRL_TARGET_SEL, hisi_ptt->trace_ctrl.filter); > + if (!hisi_ptt->trace_ctrl.is_port) > + val |= HISI_PTT_TRACE_CTRL_FILTER_MODE; > + > + /* Start the Trace */ > + val |= HISI_PTT_TRACE_CTRL_EN; > + writel(val, hisi_ptt->iobase + HISI_PTT_TRACE_CTRL); > + > + return 0; > +} > + > +static int hisi_ptt_update_aux(struct hisi_ptt *hisi_ptt, int index, bool stop) > +{ > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + struct perf_output_handle *handle = &ctrl->handle; > + struct perf_event *event = handle->event; > + struct hisi_ptt_pmu_buf *buf; > + void *addr; > + > + buf = perf_get_aux(handle); > + if (!buf || !handle->size) > + return -EINVAL; > + > + addr = ctrl->trace_buf[ctrl->buf_index].addr; > + > + memcpy(buf->base + buf->pos, addr, HISI_PTT_TRACE_BUF_SIZE); > + memset(addr, 0, HISI_PTT_TRACE_BUF_SIZE); Hi Kicong, I also have the same comment as Leo here, I don't think the memset is required. > + buf->pos += HISI_PTT_TRACE_BUF_SIZE; > + > + if (stop) { > + perf_aux_output_end(handle, buf->pos); > + } else if (buf->length - buf->pos < HISI_PTT_TRACE_BUF_SIZE) { > + perf_aux_output_skip(handle, buf->length - buf->pos); perf_aux_output_skip() can also return an error so should probably also be checked like perf_aux_output_begin() I'm also wondering why there is a skip for every output_end()? Is that to avoid having two memcpy calls to handle the wrap around if the data to be copied goes past the end of the aux buffer? For example if your buffers are 4MB each and the aux buffer that the user picked isn't a multiple of 4 I can see you needing to write the first part of the 4MB to the end of the aux buffer and then the last part to the beginning which would be two memcpy() calls. And then a skip wouldn't be required. I looked at all the other uses of perf_output_end() and perf_output_skip() in the kernel and didn't see a pattern like yours so it seems suspicous to me. Maybe at least some comments around this section are needed. Thanks James > + perf_aux_output_end(handle, buf->pos); > + > + buf = perf_aux_output_begin(handle, event); > + if (!buf) > + return -EINVAL; > + > + buf->pos = handle->head % buf->length; > + if (buf->length - buf->pos < HISI_PTT_TRACE_BUF_SIZE) { > + perf_aux_output_end(handle, 0); > + return -EINVAL; > + } > + } > + > + return 0; > +} > + > +static irqreturn_t hisi_ptt_isr(int irq, void *context) > +{ > + struct hisi_ptt *hisi_ptt = context; > + u32 status, buf_idx; > + > + status = readl(hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > + buf_idx = ffs(status) - 1; > + > + /* Clear the interrupt status of buffer @buf_idx */ > + writel(status, hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > + > + /* > + * Update the AUX buffer and cache the current buffer index, > + * as we need to know this and save the data when the trace > + * is ended out of the interrupt handler. End the trace > + * if the updating fails. > + */ > + if (hisi_ptt_update_aux(hisi_ptt, buf_idx, false)) > + hisi_ptt_trace_end(hisi_ptt); > + else > + hisi_ptt->trace_ctrl.buf_index = (buf_idx + 1) % HISI_PTT_TRACE_BUF_CNT; > + > + return IRQ_HANDLED; > +} > + > +static irqreturn_t hisi_ptt_irq(int irq, void *context) > +{ > + struct hisi_ptt *hisi_ptt = context; > + u32 status; > + > + status = readl(hisi_ptt->iobase + HISI_PTT_TRACE_INT_STAT); > + if (!(status & HISI_PTT_TRACE_INT_STAT_MASK)) > + return IRQ_NONE; > + > + return IRQ_WAKE_THREAD; > +} > + > +static void hisi_ptt_irq_free_vectors(void *pdev) > +{ > + pci_free_irq_vectors(pdev); > +} > + > +static int hisi_ptt_register_irq(struct hisi_ptt *hisi_ptt) > +{ > + struct pci_dev *pdev = hisi_ptt->pdev; > + int ret; > + > + ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); > + if (ret < 0) { > + pci_err(pdev, "failed to allocate irq vector, ret = %d\n", ret); > + return ret; > + } > + > + ret = devm_add_action_or_reset(&pdev->dev, hisi_ptt_irq_free_vectors, pdev); > + if (ret < 0) > + return ret; > + > + ret = devm_request_threaded_irq(&pdev->dev, > + pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), > + hisi_ptt_irq, hisi_ptt_isr, 0, > + DRV_NAME, hisi_ptt); > + if (ret) { > + pci_err(pdev, "failed to request irq %d, ret = %d\n", > + pci_irq_vector(pdev, HISI_PTT_TRACE_DMA_IRQ), ret); > + return ret; > + } > + > + return 0; > +} > + > +static int hisi_ptt_init_filters(struct pci_dev *pdev, void *data) > +{ > + struct hisi_ptt_filter_desc *filter; > + struct hisi_ptt *hisi_ptt = data; > + struct list_head *target_list; > + > + target_list = pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ? > + &hisi_ptt->port_filters : &hisi_ptt->req_filters; > + > + filter = kzalloc(sizeof(*filter), GFP_KERNEL); > + if (!filter) { > + pci_err(hisi_ptt->pdev, "failed to add filter %s\n", pci_name(pdev)); > + return -ENOMEM; > + } > + > + filter->pdev = pdev; > + list_add_tail(&filter->list, target_list); > + > + /* Update the available port mask */ > + if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) > + hisi_ptt->port_mask |= hisi_ptt_get_filter_val(pdev); > + > + return 0; > +} > + > +static void hisi_ptt_release_filters(void *data) > +{ > + struct hisi_ptt_filter_desc *filter, *tfilter; > + struct hisi_ptt *hisi_ptt = data; > + > + list_for_each_entry_safe(filter, tfilter, &hisi_ptt->req_filters, list) { > + list_del(&filter->list); > + kfree(filter); > + } > + > + list_for_each_entry_safe(filter, tfilter, &hisi_ptt->port_filters, list) { > + list_del(&filter->list); > + kfree(filter); > + } > +} > + > +static int hisi_ptt_init_ctrls(struct hisi_ptt *hisi_ptt) > +{ > + struct pci_dev *pdev = hisi_ptt->pdev; > + struct pci_bus *bus; > + int ret; > + u32 reg; > + > + INIT_LIST_HEAD(&hisi_ptt->port_filters); > + INIT_LIST_HEAD(&hisi_ptt->req_filters); > + > + /* > + * The device range register provides the information about the > + * root ports which the RCiEP can control and trace. The RCiEP > + * and the root ports it support are on the same PCIe core, with > + * same domain number but maybe different bus number. The device > + * range register will tell us which root ports we can support, > + * Bit[31:16] indicates the upper BDF numbers of the root port, > + * while Bit[15:0] indicates the lower. > + */ > + reg = readl(hisi_ptt->iobase + HISI_PTT_DEVICE_RANGE); > + hisi_ptt->upper = FIELD_GET(HISI_PTT_DEVICE_RANGE_UPPER, reg); > + hisi_ptt->lower = FIELD_GET(HISI_PTT_DEVICE_RANGE_LOWER, reg); > + > + bus = pci_find_bus(pci_domain_nr(pdev->bus), PCI_BUS_NUM(hisi_ptt->upper)); > + if (bus) > + pci_walk_bus(bus, hisi_ptt_init_filters, hisi_ptt); > + > + ret = devm_add_action_or_reset(&pdev->dev, hisi_ptt_release_filters, hisi_ptt); > + if (ret) > + return ret; > + > + hisi_ptt->trace_ctrl.default_cpu = cpumask_first(cpumask_of_node(dev_to_node(&pdev->dev))); > + > + return 0; > +} > + > +#define HISI_PTT_PMU_FILTER_IS_PORT BIT(19) > +#define HISI_PTT_PMU_FILTER_VAL_MASK GENMASK(15, 0) > +#define HISI_PTT_PMU_DIRECTION_MASK GENMASK(23, 20) > +#define HISI_PTT_PMU_TYPE_MASK GENMASK(31, 24) > +#define HISI_PTT_PMU_FORMAT_MASK GENMASK(35, 32) > + > +static ssize_t available_root_port_filters_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev)); > + struct hisi_ptt_filter_desc *filter; > + int pos = 0; > + > + mutex_lock(&hisi_ptt->mutex); > + if (list_empty(&hisi_ptt->port_filters)) { > + pos = sysfs_emit(buf, "\n"); > + goto out; > + } > + > + list_for_each_entry(filter, &hisi_ptt->port_filters, list) > + pos += sysfs_emit_at(buf, pos, "%s 0x%05lx\n", > + pci_name(filter->pdev), > + hisi_ptt_get_filter_val(filter->pdev) | > + HISI_PTT_PMU_FILTER_IS_PORT); > + > +out: > + mutex_unlock(&hisi_ptt->mutex); > + return pos; > +} > +static DEVICE_ATTR_ADMIN_RO(available_root_port_filters); > + > +static ssize_t available_requester_filters_show(struct device *dev, > + struct device_attribute *attr, > + char *buf) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(dev_get_drvdata(dev)); > + struct hisi_ptt_filter_desc *filter; > + int pos = 0; > + > + mutex_lock(&hisi_ptt->mutex); > + if (list_empty(&hisi_ptt->req_filters)) { > + pos = sysfs_emit(buf, "\n"); > + goto out; > + } > + > + list_for_each_entry(filter, &hisi_ptt->req_filters, list) > + pos += sysfs_emit_at(buf, pos, "%s 0x%05x\n", > + pci_name(filter->pdev), > + hisi_ptt_get_filter_val(filter->pdev)); > + > +out: > + mutex_unlock(&hisi_ptt->mutex); > + return pos; > +} > +static DEVICE_ATTR_ADMIN_RO(available_requester_filters); > + > +PMU_FORMAT_ATTR(filter, "config:0-19"); > +PMU_FORMAT_ATTR(direction, "config:20-23"); > +PMU_FORMAT_ATTR(type, "config:24-31"); > +PMU_FORMAT_ATTR(format, "config:32-35"); > + > +static struct attribute *hisi_ptt_pmu_format_attrs[] = { > + &format_attr_filter.attr, > + &format_attr_direction.attr, > + &format_attr_type.attr, > + &format_attr_format.attr, > + NULL > +}; > + > +static struct attribute_group hisi_ptt_pmu_format_group = { > + .name = "format", > + .attrs = hisi_ptt_pmu_format_attrs, > +}; > + > +static struct attribute *hisi_ptt_pmu_filter_attrs[] = { > + &dev_attr_available_root_port_filters.attr, > + &dev_attr_available_requester_filters.attr, > + NULL > +}; > + > +static struct attribute_group hisi_ptt_pmu_filter_group = { > + .attrs = hisi_ptt_pmu_filter_attrs, > +}; > + > +static const struct attribute_group *hisi_ptt_pmu_groups[] = { > + &hisi_ptt_pmu_format_group, > + &hisi_ptt_pmu_filter_group, > + NULL > +}; > + > +/* > + * Check whether the config is valid or not. Some configs are multi-selectable > + * and can be set simultaneously, while some are single selectable (onehot). > + * Use this function to check the non-onehot configs while > + * hisi_ptt_trace_valid_config_onehot() for the onehot ones. > + */ > +static int hisi_ptt_trace_valid_config(u32 val, const u32 *available_list, u32 list_size) > +{ > + int i; > + > + /* The non-onehot configs cannot be 0. */ > + if (!val) > + return -EINVAL; > + > + /* > + * Walk the available list and clear the valid bits of > + * the config. If there is any resident bit after the > + * walk then the config is invalid. > + */ > + for (i = 0; i < list_size; i++) > + val &= ~available_list[i]; > + > + return val ? -EINVAL : 0; > +} > + > +static int hisi_ptt_trace_valid_config_onehot(u32 val, const u32 *available_list, u32 list_size) > +{ > + int i; > + > + for (i = 0; i < list_size; i++) > + if (val == available_list[i]) > + return 0; > + > + return -EINVAL; > +} > + > +static int hisi_ptt_trace_init_filter(struct hisi_ptt *hisi_ptt, u64 config) > +{ > + unsigned long val, port_mask = hisi_ptt->port_mask; > + struct hisi_ptt_filter_desc *filter; > + int ret = -EINVAL; > + > + hisi_ptt->trace_ctrl.is_port = FIELD_GET(HISI_PTT_PMU_FILTER_IS_PORT, config); > + val = FIELD_GET(HISI_PTT_PMU_FILTER_VAL_MASK, config); > + > + /* > + * Port filters are defined as bit mask. For port filters, check > + * the bits in the @val are within the range of hisi_ptt->port_mask > + * and whether it's empty or not, otherwise user has specified > + * some unsupported root ports. > + * > + * For Requester ID filters, walk the available filter list to see > + * whether we have one matched. > + */ > + if (!hisi_ptt->trace_ctrl.is_port) { > + list_for_each_entry(filter, &hisi_ptt->req_filters, list) > + if (val == hisi_ptt_get_filter_val(filter->pdev)) { > + ret = 0; > + break; > + } > + } else if (bitmap_subset(&val, &port_mask, BITS_PER_LONG)) { > + ret = 0; > + } > + > + if (ret) > + return ret; > + > + hisi_ptt->trace_ctrl.filter = val; > + return 0; > +} > + > +static int hisi_ptt_pmu_event_init(struct perf_event *event) > +{ > + /* > + * The supported value of the direction parameter. See hisi_ptt.rst > + * documentation for more details. > + */ > + static const u32 hisi_ptt_trace_available_direction[] = { > + 0, > + 1, > + 2, > + 3, > + }; > + /* Different types can be set simultaneously */ > + static const u32 hisi_ptt_trace_available_type[] = { > + 1, /* posted_request */ > + 2, /* non-posted_request */ > + 4, /* completion */ > + }; > + static const u32 hisi_ptt_trace_availble_format[] = { > + 0, /* 4DW */ > + 1, /* 8DW */ > + }; > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > + struct hisi_ptt_trace_ctrl *ctrl = &hisi_ptt->trace_ctrl; > + int ret; > + u32 val; > + > + if (event->attr.type != hisi_ptt->hisi_ptt_pmu.type) > + return -ENOENT; > + > + mutex_lock(&hisi_ptt->mutex); > + > + ret = hisi_ptt_trace_init_filter(hisi_ptt, event->attr.config); > + if (ret < 0) > + goto out; > + > + val = FIELD_GET(HISI_PTT_PMU_DIRECTION_MASK, event->attr.config); > + ret = hisi_ptt_trace_valid_config_onehot(val, hisi_ptt_trace_available_direction, > + ARRAY_SIZE(hisi_ptt_trace_available_direction)); > + if (ret < 0) > + goto out; > + ctrl->direction = val; > + > + val = FIELD_GET(HISI_PTT_PMU_TYPE_MASK, event->attr.config); > + ret = hisi_ptt_trace_valid_config(val, hisi_ptt_trace_available_type, > + ARRAY_SIZE(hisi_ptt_trace_available_type)); > + if (ret < 0) > + goto out; > + ctrl->type = val; > + > + val = FIELD_GET(HISI_PTT_PMU_FORMAT_MASK, event->attr.config); > + ret = hisi_ptt_trace_valid_config_onehot(val, hisi_ptt_trace_availble_format, > + ARRAY_SIZE(hisi_ptt_trace_availble_format)); > + if (ret < 0) > + goto out; > + ctrl->format = val; > + > +out: > + mutex_unlock(&hisi_ptt->mutex); > + return ret; > +} > + > +static void *hisi_ptt_pmu_setup_aux(struct perf_event *event, void **pages, > + int nr_pages, bool overwrite) > +{ > + struct hisi_ptt_pmu_buf *buf; > + struct page **pagelist; > + int i; > + > + if (overwrite) { > + dev_warn(event->pmu->dev, "Overwrite mode is not supported\n"); > + return NULL; > + } > + > + /* If the pages size less than buffers, we cannot start trace */ > + if (nr_pages < HISI_PTT_TRACE_TOTAL_BUF_SIZE / PAGE_SIZE) > + return NULL; > + > + buf = kzalloc(sizeof(*buf), GFP_KERNEL); > + if (!buf) > + return NULL; > + > + pagelist = kcalloc(nr_pages, sizeof(*pagelist), GFP_KERNEL); > + if (!pagelist) { > + kfree(buf); > + return NULL; > + } > + > + for (i = 0; i < nr_pages; i++) > + pagelist[i] = virt_to_page(pages[i]); > + > + buf->base = vmap(pagelist, nr_pages, VM_MAP, PAGE_KERNEL); > + if (!buf->base) { > + kfree(pagelist); > + kfree(buf); > + return NULL; > + } > + > + buf->nr_pages = nr_pages; > + buf->length = nr_pages * PAGE_SIZE; > + buf->pos = 0; > + > + kfree(pagelist); > + return buf; > +} > + > +static void hisi_ptt_pmu_free_aux(void *aux) > +{ > + struct hisi_ptt_pmu_buf *buf = aux; > + > + vunmap(buf->base); > + kfree(buf); > +} > + > +static void hisi_ptt_pmu_start(struct perf_event *event, int flags) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > + struct perf_output_handle *handle = &hisi_ptt->trace_ctrl.handle; > + struct hw_perf_event *hwc = &event->hw; > + struct hisi_ptt_pmu_buf *buf; > + int cpu = event->cpu; > + int ret; > + > + hwc->state = 0; > + mutex_lock(&hisi_ptt->mutex); > + if (hisi_ptt->trace_ctrl.started) { > + pci_dbg(hisi_ptt->pdev, "trace has already started\n"); > + goto stop; > + } > + > + if (cpu == -1) > + cpu = hisi_ptt->trace_ctrl.default_cpu; > + > + /* > + * Handle the interrupt on the same cpu which starts the trace to avoid > + * context mismatch. Otherwise we'll trigger the WARN from the perf > + * core in event_function_local(). > + */ > + WARN_ON(irq_set_affinity(pci_irq_vector(hisi_ptt->pdev, HISI_PTT_TRACE_DMA_IRQ), > + cpumask_of(cpu))); > + > + ret = hisi_ptt_alloc_trace_buf(hisi_ptt); > + if (ret) { > + pci_dbg(hisi_ptt->pdev, "alloc trace buf failed, ret = %d\n", ret); > + goto stop; > + } > + > + buf = perf_aux_output_begin(handle, event); > + if (!buf) { > + pci_dbg(hisi_ptt->pdev, "aux output begin failed\n"); > + goto stop; > + } > + > + buf->pos = handle->head % buf->length; > + > + ret = hisi_ptt_trace_start(hisi_ptt); > + if (ret) { > + pci_dbg(hisi_ptt->pdev, "trace start failed, ret = %d\n", ret); > + perf_aux_output_end(handle, 0); > + goto stop; > + } > + > + mutex_unlock(&hisi_ptt->mutex); > + return; > +stop: > + event->hw.state |= PERF_HES_STOPPED; > + mutex_unlock(&hisi_ptt->mutex); > +} > + > +static void hisi_ptt_pmu_stop(struct perf_event *event, int flags) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > + struct hw_perf_event *hwc = &event->hw; > + > + if (hwc->state & PERF_HES_STOPPED) > + return; > + > + mutex_lock(&hisi_ptt->mutex); > + if (hisi_ptt->trace_ctrl.started) { > + hisi_ptt_trace_end(hisi_ptt); > + WARN(!hisi_ptt_wait_trace_hw_idle(hisi_ptt), "Device is still busy"); > + hisi_ptt_update_aux(hisi_ptt, hisi_ptt->trace_ctrl.buf_index, true); > + } > + mutex_unlock(&hisi_ptt->mutex); > + > + hwc->state |= PERF_HES_STOPPED; > + perf_event_update_userpage(event); > + hwc->state |= PERF_HES_UPTODATE; > +} > + > +static int hisi_ptt_pmu_add(struct perf_event *event, int flags) > +{ > + struct hisi_ptt *hisi_ptt = to_hisi_ptt(event->pmu); > + struct hw_perf_event *hwc = &event->hw; > + int cpu = event->cpu; > + > + /* > + * Only allow the default cpu to add the event if user doesn't specify > + * the cpus. > + */ > + if (cpu == -1 && smp_processor_id() != hisi_ptt->trace_ctrl.default_cpu) > + return 0; > + > + hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; > + > + if (flags & PERF_EF_START) { > + hisi_ptt_pmu_start(event, PERF_EF_RELOAD); > + if (hwc->state & PERF_HES_STOPPED) > + return -EINVAL; > + } > + > + return 0; > +} > + > +static void hisi_ptt_pmu_del(struct perf_event *event, int flags) > +{ > + hisi_ptt_pmu_stop(event, PERF_EF_UPDATE); > +} > + > +static int hisi_ptt_register_pmu(struct hisi_ptt *hisi_ptt) > +{ > + u16 core_id, sicl_id; > + char *pmu_name; > + u32 reg; > + > + hisi_ptt->hisi_ptt_pmu = (struct pmu) { > + .module = THIS_MODULE, > + .capabilities = PERF_PMU_CAP_EXCLUSIVE | PERF_PMU_CAP_ITRACE, > + .task_ctx_nr = perf_sw_context, > + .attr_groups = hisi_ptt_pmu_groups, > + .event_init = hisi_ptt_pmu_event_init, > + .setup_aux = hisi_ptt_pmu_setup_aux, > + .free_aux = hisi_ptt_pmu_free_aux, > + .start = hisi_ptt_pmu_start, > + .stop = hisi_ptt_pmu_stop, > + .add = hisi_ptt_pmu_add, > + .del = hisi_ptt_pmu_del, > + }; > + > + reg = readl(hisi_ptt->iobase + HISI_PTT_LOCATION); > + core_id = FIELD_GET(HISI_PTT_CORE_ID, reg); > + sicl_id = FIELD_GET(HISI_PTT_SICL_ID, reg); > + > + pmu_name = devm_kasprintf(&hisi_ptt->pdev->dev, GFP_KERNEL, "hisi_ptt%u_%u", > + sicl_id, core_id); > + if (!pmu_name) > + return -ENOMEM; > + > + return perf_pmu_register(&hisi_ptt->hisi_ptt_pmu, pmu_name, -1); > +} > + > +/* > + * The DMA of PTT trace can only use direct mapping, due to some > + * hardware restriction. Check whether there is an IOMMU or the > + * policy of the IOMMU domain is passthrough, otherwise the trace > + * cannot work. > + * > + * The PTT device is supposed to behind the ARM SMMUv3, which > + * should have passthrough the device by a quirk. > + */ > +static int hisi_ptt_check_iommu_mapping(struct pci_dev *pdev) > +{ > + struct iommu_domain *iommu_domain; > + > + iommu_domain = iommu_get_domain_for_dev(&pdev->dev); > + if (!iommu_domain || iommu_domain->type == IOMMU_DOMAIN_IDENTITY) > + return 0; > + > + return -EOPNOTSUPP; > +} > + > +static int hisi_ptt_probe(struct pci_dev *pdev, > + const struct pci_device_id *id) > +{ > + struct hisi_ptt *hisi_ptt; > + int ret; > + > + ret = hisi_ptt_check_iommu_mapping(pdev); > + if (ret) { > + pci_err(pdev, "requires direct DMA mappings\n"); > + return ret; > + } > + > + hisi_ptt = devm_kzalloc(&pdev->dev, sizeof(*hisi_ptt), GFP_KERNEL); > + if (!hisi_ptt) > + return -ENOMEM; > + > + mutex_init(&hisi_ptt->mutex); > + hisi_ptt->pdev = pdev; > + pci_set_drvdata(pdev, hisi_ptt); > + > + ret = pcim_enable_device(pdev); > + if (ret) { > + pci_err(pdev, "failed to enable device, ret = %d\n", ret); > + return ret; > + } > + > + ret = pcim_iomap_regions(pdev, BIT(2), DRV_NAME); > + if (ret) { > + pci_err(pdev, "failed to remap io memory, ret = %d\n", ret); > + return ret; > + } > + > + hisi_ptt->iobase = pcim_iomap_table(pdev)[2]; > + > + ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); > + if (ret) { > + pci_err(pdev, "failed to set 64 bit dma mask, ret = %d\n", ret); > + return ret; > + } > + > + pci_set_master(pdev); > + > + ret = hisi_ptt_register_irq(hisi_ptt); > + if (ret) > + return ret; > + > + ret = hisi_ptt_init_ctrls(hisi_ptt); > + if (ret) { > + pci_err(pdev, "failed to init controls, ret = %d\n", ret); > + return ret; > + } > + > + ret = hisi_ptt_register_pmu(hisi_ptt); > + if (ret) { > + pci_err(pdev, "failed to register PMU device, ret = %d", ret); > + return ret; > + } > + > + return 0; > +} > + > +static void hisi_ptt_remove(struct pci_dev *pdev) > +{ > + struct hisi_ptt *hisi_ptt = pci_get_drvdata(pdev); > + > + /* > + * We have to manually unregister the PMU device rather than make it > + * devres managed to keep order that the PMU device's unregistration > + * is prior to the release of DMA buffers. As the DMA buffers are > + * devm allocated when necessary which is after the registration of > + * the PMU device. > + */ > + perf_pmu_unregister(&hisi_ptt->hisi_ptt_pmu); > +} > + > +static const struct pci_device_id hisi_ptt_id_tbl[] = { > + { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa12e) }, > + { } > +}; > +MODULE_DEVICE_TABLE(pci, hisi_ptt_id_tbl); > + > +static struct pci_driver hisi_ptt_driver = { > + .name = DRV_NAME, > + .id_table = hisi_ptt_id_tbl, > + .probe = hisi_ptt_probe, > + .remove = hisi_ptt_remove, > +}; > +module_pci_driver(hisi_ptt_driver); > + > +MODULE_LICENSE("GPL"); > +MODULE_AUTHOR("Yicong Yang <yangyicong(a)hisilicon.com>"); > +MODULE_DESCRIPTION("Driver for HiSilicon PCIe tune and trace device"); > diff --git a/drivers/hwtracing/ptt/hisi_ptt.h b/drivers/hwtracing/ptt/hisi_ptt.h > new file mode 100644 > index 000000000000..29b6d6293d6c > --- /dev/null > +++ b/drivers/hwtracing/ptt/hisi_ptt.h > @@ -0,0 +1,166 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Driver for HiSilicon PCIe tune and trace device > + * > + * Copyright (c) 2022 HiSilicon Technologies Co., Ltd. > + * Author: Yicong Yang <yangyicong(a)hisilicon.com> > + */ > + > +#ifndef _HISI_PTT_H > +#define _HISI_PTT_H > + > +#include <linux/bits.h> > +#include <linux/list.h> > +#include <linux/mutex.h> > +#include <linux/pci.h> > +#include <linux/perf_event.h> > +#include <linux/types.h> > + > +#define DRV_NAME "hisi_ptt" > + > +/* > + * The definition of the device registers and register fields. > + */ > +#define HISI_PTT_TRACE_ADDR_SIZE 0x0800 > +#define HISI_PTT_TRACE_ADDR_BASE_LO_0 0x0810 > +#define HISI_PTT_TRACE_ADDR_BASE_HI_0 0x0814 > +#define HISI_PTT_TRACE_ADDR_STRIDE 0x8 > +#define HISI_PTT_TRACE_CTRL 0x0850 > +#define HISI_PTT_TRACE_CTRL_EN BIT(0) > +#define HISI_PTT_TRACE_CTRL_RST BIT(1) > +#define HISI_PTT_TRACE_CTRL_RXTX_SEL GENMASK(3, 2) > +#define HISI_PTT_TRACE_CTRL_TYPE_SEL GENMASK(7, 4) > +#define HISI_PTT_TRACE_CTRL_DATA_FORMAT BIT(14) > +#define HISI_PTT_TRACE_CTRL_FILTER_MODE BIT(15) > +#define HISI_PTT_TRACE_CTRL_TARGET_SEL GENMASK(31, 16) > +#define HISI_PTT_TRACE_INT_STAT 0x0890 > +#define HISI_PTT_TRACE_INT_STAT_MASK GENMASK(3, 0) > +#define HISI_PTT_TRACE_INT_MASK 0x0894 > +#define HISI_PTT_TRACE_WR_STS 0x08a0 > +#define HISI_PTT_TRACE_WR_STS_WRITE GENMASK(27, 0) > +#define HISI_PTT_TRACE_WR_STS_BUFFER GENMASK(29, 28) > +#define HISI_PTT_TRACE_STS 0x08b0 > +#define HISI_PTT_TRACE_IDLE BIT(0) > +#define HISI_PTT_DEVICE_RANGE 0x0fe0 > +#define HISI_PTT_DEVICE_RANGE_UPPER GENMASK(31, 16) > +#define HISI_PTT_DEVICE_RANGE_LOWER GENMASK(15, 0) > +#define HISI_PTT_LOCATION 0x0fe8 > +#define HISI_PTT_CORE_ID GENMASK(15, 0) > +#define HISI_PTT_SICL_ID GENMASK(31, 16) > + > +/* Parameters of PTT trace DMA part. */ > +#define HISI_PTT_TRACE_DMA_IRQ 0 > +#define HISI_PTT_TRACE_BUF_CNT 4 > +#define HISI_PTT_TRACE_BUF_SIZE SZ_4M > +#define HISI_PTT_TRACE_TOTAL_BUF_SIZE (HISI_PTT_TRACE_BUF_SIZE * \ > + HISI_PTT_TRACE_BUF_CNT) > +/* Wait time for hardware DMA to reset */ > +#define HISI_PTT_RESET_TIMEOUT_US 10UL > +#define HISI_PTT_RESET_POLL_INTERVAL_US 1UL > +/* Poll timeout and interval for waiting hardware work to finish */ > +#define HISI_PTT_WAIT_TRACE_TIMEOUT_US 100UL > +#define HISI_PTT_WAIT_POLL_INTERVAL_US 10UL > + > +#define HISI_PCIE_CORE_PORT_ID(devfn) (PCI_FUNC(devfn) << 1) > + > +/** > + * struct hisi_ptt_dma_buffer - describe a single trace buffer of PTT trace. > + * The detail of the data format is described > + * in the documentation of PTT device. > + * @dma: DMA address of this buffer visible to the device > + * @addr: virtual address of this buffer visible to the cpu > + */ > +struct hisi_ptt_dma_buffer { > + dma_addr_t dma; > + void *addr; > +}; > + > +/** > + * struct hisi_ptt_trace_ctrl - control and status of PTT trace > + * @trace_buf: array of the trace buffers for holding the trace data. > + * the length will be HISI_PTT_TRACE_BUF_CNT. > + * @handle: perf output handle of current trace session > + * @default_cpu: default cpu to start the trace session > + * @buf_index: the index of current using trace buffer > + * @started: current trace status, true for started > + * @is_port: whether we're tracing root port or not > + * @direction: direction of the TLP headers to trace > + * @filter: filter value for tracing the TLP headers > + * @format: format of the TLP headers to trace > + * @type: type of the TLP headers to trace > + */ > +struct hisi_ptt_trace_ctrl { > + struct hisi_ptt_dma_buffer *trace_buf; > + struct perf_output_handle handle; > + int default_cpu; > + u32 buf_index; > + bool started; > + bool is_port; > + u32 direction:2; > + u32 filter:16; > + u32 format:1; > + u32 type:4; > +}; > + > +/** > + * struct hisi_ptt_filter_desc - descriptor of the PTT trace filter > + * @list: entry of this descriptor in the filter list > + * @pdev: pci_dev related to this filter > + */ > +struct hisi_ptt_filter_desc { > + struct list_head list; > + struct pci_dev *pdev; > +}; > + > + > +/** > + * struct hisi_ptt_pmu_buf - descriptor of the AUX buffer of PTT trace > + * @length: size of the AUX buffer > + * @nr_pages: number of pages of the AUX buffer > + * @base: start address of AUX buffer > + * @pos: position in the AUX buffer to commit traced data > + */ > +struct hisi_ptt_pmu_buf { > + size_t length; > + int nr_pages; > + void *base; > + long pos; > +}; > + > +/** > + * struct hisi_ptt - per PTT device data > + * @trace_ctrl: the control information of PTT trace > + * @hisi_ptt_pmu: the pum device of trace > + * @iobase: base IO address of the device > + * @pdev: pci_dev of this PTT device > + * @mutex: mutex to protect the filter list and serialize the perf process. > + * @upper: the upper BDF range of the PCI devices managed by this PTT device > + * @lower: the lower BDF range of the PCI devices managed by this PTT device > + * @port_filters: the filter list of root ports > + * @req_filters: the filter list of requester ID > + * @port_mask: port mask of the managed root ports > + */ > +struct hisi_ptt { > + struct hisi_ptt_trace_ctrl trace_ctrl; > + struct pmu hisi_ptt_pmu; > + void __iomem *iobase; > + struct pci_dev *pdev; > + struct mutex mutex; > + u32 upper; > + u32 lower; > + > + /* > + * The trace TLP headers can either be filtered by certain > + * root port, or by the requester ID. Organize the filters > + * by @port_filters and @req_filters here. The mask of all > + * the valid ports is also cached for doing sanity check > + * of user input. > + */ > + struct list_head port_filters; > + struct list_head req_filters; > + u16 port_mask; > +}; > + > +#define to_hisi_ptt(pmu) container_of(pmu, struct hisi_ptt, hisi_ptt_pmu) > + > +#endif /* _HISI_PTT_H */

3 years, 1 month

[PATCH v5 0/2] Add support for UltraSoc System Memory Buffer

by Qi Liu

Add support for UltraSoc System Memory Buffer. Change since v4: - Add a simple document of SMB driver according to Suzuki's comment. - Address the comments from Suzuki. - https://lore.kernel.org/linux-arm-kernel/20220128061755.31909-1-liuqi115@hu… Change since v3: - Modify the file header according to community specifications. - Address the comments from Mathieu. - Link:https://lore.kernel.org/linux-arm-kernel/20211118110016.40398-1-liuqi1… Change since v2: - Move ultrasoc driver to drivers/hwtracing/coresight. - Link:https://lists.linaro.org/pipermail/coresight/2021-November/007310.html Change since v1: - Drop the document of UltraSoc according to Mathieu's comment. - Add comments to explain some private hardware settings. - Address the comments from Mathieu. - Link: https://lists.linaro.org/pipermail/coresight/2021-August/006842.html Change since RFC: - Move driver to drivers/hwtracing/coresight/ultrasoc. - Remove ultrasoc-axi-com.c, as AXI-COM doesn't need to be configured in basic tracing function. - Remove ultrasoc.c as SMB does not need to register with the ultrasoc core. - Address the comments from Mathieu and Suzuki. - Link: https://lists.linaro.org/pipermail/coresight/2021-June/006535.html Qi Liu (2): drivers/coresight: Add UltraSoc System Memory Buffer driver Documentation: Add document for UltraSoc SMB drivers .../trace/coresight/ultrasoc-smb.rst | 79 +++ drivers/hwtracing/coresight/Kconfig | 10 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/ultrasoc-smb.c | 643 ++++++++++++++++++ drivers/hwtracing/coresight/ultrasoc-smb.h | 106 +++ 5 files changed, 839 insertions(+) create mode 100644 Documentation/trace/coresight/ultrasoc-smb.rst create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.c create mode 100644 drivers/hwtracing/coresight/ultrasoc-smb.h -- 2.24.0

3 years, 1 month

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