CoreSight

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[PATCH] perf test: Increase buffer size for Coresight basic tests

by James Clark

These tests record in a mode that includes kernel trace but look for samples of a userspace process. This makes them sensitive to any kernel compilation options that increase the amount of time spent in the kernel. If the trace buffer is completely filled before userspace is reached then the test will fail. Double the buffer size to fix this. The other tests in the same file aren't sensitive to this for various reasons, for example the iterate devices test filters by userspace trace only. But in order to keep coverage of all the modes, increase the buffer size rather than filtering by userspace for the basic tests. Fixes: d1efa4a0a696 ("perf cs-etm: Add separate decode paths for timeless and per-thread modes") Signed-off-by: James Clark <james.clark(a)arm.com> --- tools/perf/tests/shell/test_arm_coresight.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/tests/shell/test_arm_coresight.sh b/tools/perf/tests/shell/test_arm_coresight.sh index 65dd85207125..3302ea0b9672 100755 --- a/tools/perf/tests/shell/test_arm_coresight.sh +++ b/tools/perf/tests/shell/test_arm_coresight.sh @@ -188,7 +188,7 @@ arm_cs_etm_snapshot_test() { arm_cs_etm_basic_test() { echo "Recording trace with '$*'" - perf record -o ${perfdata} "$@" -- ls > /dev/null 2>&1 + perf record -o ${perfdata} "$@" -m,8M -- ls > /dev/null 2>&1 perf_script_branch_samples ls && perf_report_branch_samples ls && -- 2.34.1

1 year, 4 months

Re: [PATCH 00/19] amba: store owner from modules with amba_driver_register()

by Suzuki K Poulose

+ Greg Hi Krzysztof, On 30/03/2024 18:00, Krzysztof Kozlowski wrote: > On 30/03/2024 18:58, Krzysztof Kozlowski wrote: >> >> On Tue, 26 Mar 2024 21:23:30 +0100, Krzysztof Kozlowski wrote: >>> Merging >>> ======= >>> All further patches depend on the first amba patch, therefore please ack >>> and this should go via one tree. >>> >>> Description >>> =========== >>> Modules registering driver with amba_driver_register() often forget to >>> set .owner field. >>> >>> [...] >> >> Applied, thanks! >> >> [01/19] amba: store owner from modules with amba_driver_register() >> (no commit info) > > Patchset applied here: > https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git/log/?h=fo… How do you plan to push this ? Given this affects most of the drivers/, do you plan to send this to Greg ? We have changes in the coresight tree that would conflict with this "tag" ( I haven't merged them yet, but is in my local queue). I want to make sure we can avoid the conflicts. I am happy to merge this to my local tree and base the changes on this, if this is going in for v6.10 and all are in agreement. Kind regards Suzuki > > Best regards, > Krzysztof >

1 year, 4 months

[PATCH 0/3] coresight: etm4x: Fix CPU idle PM support for ETE

by Suzuki K Poulose

Our CPUidle state save restore has some bugs which are triggered for an ETM with system instructions (e.g. ETE). This is a series of fixes to address them. Suzuki K Poulose (3): coresight: etm4x: Do not hardcode IOMEM access for register restore coresight: etm4x: Do not save/restore Data trace control registers coresight: etm4x: Safe access for TRCQCLTR .../coresight/coresight-etm4x-core.c | 20 +++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 6 +++--- 2 files changed, 13 insertions(+), 13 deletions(-) -- 2.34.1

1 year, 4 months

Re: [PATCH 3/3] coresight: etm4x: Safe access for TRCQCLTR

by Suzuki K Poulose

On 11/04/2024 23:33, Yabin Cui wrote: > On Thu, Apr 11, 2024 at 4:31 AM Suzuki K Poulose <suzuki.poulose(a)arm.com> wrote: >> >> ETM4x implements TRCQCLTR only when the Q elements are supported >> and the Q element filtering is supported (TRCIDR0.QFILT). Access >> to the register otherwise could be fatal. Fix this by tracking the >> availability, like the others. >> >> Fixes: f188b5e76aae9 ("coresight: etm4x: Save/restore state across CPU low power states") >> Reported-by: Yabin Cui <yabinc(a)google.com> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++++-- >> drivers/hwtracing/coresight/coresight-etm4x.h | 3 +++ >> 2 files changed, 9 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index ff57aabb24c4..e0ebf7d7db91 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -1240,6 +1240,8 @@ static void etm4_init_arch_data(void *info) >> drvdata->nr_event = FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); >> /* QSUPP, bits[16:15] Q element support field */ >> drvdata->q_support = FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); >> + if (drvdata->q_support) >> + drvdata->q_filt = !!(etmidr0 & TRCIDR0_QFILT); >> /* TSSIZE, bits[28:24] Global timestamp size field */ >> drvdata->ts_size = FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0); >> >> @@ -1732,7 +1734,8 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) >> state->trcccctlr = etm4x_read32(csa, TRCCCCTLR); >> state->trcbbctlr = etm4x_read32(csa, TRCBBCTLR); >> state->trctraceidr = etm4x_read32(csa, TRCTRACEIDR); >> - state->trcqctlr = etm4x_read32(csa, TRCQCTLR); >> + if (drvdata->q_filt) >> + state->trcqctlr = etm4x_read32(csa, TRCQCTLR); >> >> state->trcvictlr = etm4x_read32(csa, TRCVICTLR); >> state->trcviiectlr = etm4x_read32(csa, TRCVIIECTLR); >> @@ -1862,7 +1865,8 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) >> etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); >> etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); >> etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); >> - etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); >> + if (drvdata->q_filt) >> + etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); >> >> etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); >> etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h >> index acd2b1db2052..25dc8ffef5c0 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x.h >> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h >> @@ -136,6 +136,7 @@ >> * of _MASK for multi bit fields and BIT() for single bits. >> */ >> #define TRCIDR0_INSTP0_MASK GENMASK(2, 1) >> +#define TRCIDR0_QFILT BIT(4) > > COMMENT: QFILT is BIT(14)? Indeed. I will fix this in the next revision. Thanks Suzuki > >> #define TRCIDR0_TRCBB BIT(5) >> #define TRCIDR0_TRCCOND BIT(6) >> #define TRCIDR0_TRCCCI BIT(7) >> @@ -979,6 +980,7 @@ struct etmv4_save_state { >> * @os_unlock: True if access to management registers is allowed. >> * @instrp0: Tracing of load and store instructions >> * as P0 elements is supported. >> + * @q_filt: Q element filtering support, if Q elements are supported. >> * @trcbb: Indicates if the trace unit supports branch broadcast tracing. >> * @trccond: If the trace unit supports conditional >> * instruction tracing. >> @@ -1041,6 +1043,7 @@ struct etmv4_drvdata { >> bool boot_enable; >> bool os_unlock; >> bool instrp0; >> + bool q_filt; >> bool trcbb; >> bool trccond; >> bool retstack; >> -- >> 2.34.1 >>

1 year, 4 months

Re: [PATCH 1/3] coresight: etm4x: Do not hardcode IOMEM access for register restore

by Suzuki K Poulose

On 11/04/2024 23:30, Yabin Cui wrote: > On Thu, Apr 11, 2024 at 4:31 AM Suzuki K Poulose <suzuki.poulose(a)arm.com> wrote: >> >> When we restore the register state for ETM4x, while coming back >> from CPU idle, we hardcode IOMEM access. This is wrong and could >> blow up for an ETM with system instructions access (and for ETE). >> >> Fixes: f5bd523690d2f ("coresight: etm4x: Convert all register accesses") >> Reported-by: Yabin Cui <yabinc(a)google.com> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> >> --- >> drivers/hwtracing/coresight/coresight-etm4x-core.c | 6 ++++-- >> 1 file changed, 4 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> index c2ca4a02dfce..fae96151cdaf 100644 >> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c >> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c >> @@ -1843,8 +1843,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) >> { >> int i; >> struct etmv4_save_state *state = drvdata->save_state; >> - struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base); >> - struct csdev_access *csa = &tmp_csa; >> + struct csdev_access *csa = &drvdata->csdev->access; >> + >> + if (!WARN_ON(!drvdata->csdev)) > > COMMENT: Remove ! before WARN_ON? WARN_ON returns 1 when the warning happens. > Yikes! Well spotted, I will fix this. Suzuki >> + return; >> >> etm4_cs_unlock(drvdata, csa); >> etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); >> -- >> 2.34.1 >>

1 year, 4 months

Lockdep splat in TMC ETR

by Denis Nikitin

Hello CoreSight friends, There is a bug recently reported on ChromeOS (with the linux kernel 6.6), https://issuetracker.google.com/329285580. Lockdep detected a deadlock in TMC ETR in a debug kernel build. [12453.456471] WARNING: possible circular locking dependency detected [12453.456518] 6.6.21-lockdep-01250-gbecf1787b73c #1 Not tainted [12453.456575] ------------------------------------------------------ [12453.456618] perf/12414 is trying to acquire lock: [12453.456671] ffffffc084bc0990 (&dma_entry_hash[i].lock){-.-.}-{2:2}, at: check_sync+0x84/0x11a0 [12453.456896] but task is already holding lock: [12453.456938] ffffff80cdb940f8 (&drvdata->spinlock){....}-{2:2}, at: tmc_update_etr_buffer+0xbc/0x898 [coresight_tmc] [12453.457332] which lock already depends on the new lock. Could you please take a look? Thanks, Denis Nikitin

1 year, 4 months

Re: [PATCH 00/19] amba: store owner from modules with amba_driver_register()

by Suzuki K Poulose

On 27/03/2024 05:57, Krzysztof Kozlowski wrote: > On 27/03/2024 00:24, Suzuki K Poulose wrote: >> Hi Krzysztof >> >> On 26/03/2024 20:23, Krzysztof Kozlowski wrote: >>> Merging >>> ======= >>> All further patches depend on the first amba patch, therefore please ack >>> and this should go via one tree. >> >> Are you able to provide a stable branch with these patches once you pull > > I doubt I will be merging this. I think amba code goes through Russell. > >> them in to "one tree" here ? We have changes coming up in the coresight >> tree, which would conflict with the changes here (horribly). >> > > You mean conflict with coresight conversion to platform driver? Worst Yes. > case it is solveable: just drop .owner. Or, we could merge the CoreSight changes (as they are really not affected by the problem this series is trying to address) after the base changes land in AMBA, via the CoreSight tree. Suzuki > > Best regards, > Krzysztof >

1 year, 5 months

Re: [PATCH 00/19] amba: store owner from modules with amba_driver_register()

by Suzuki K Poulose

Hi Krzysztof On 26/03/2024 20:23, Krzysztof Kozlowski wrote: > Merging > ======= > All further patches depend on the first amba patch, therefore please ack > and this should go via one tree. Are you able to provide a stable branch with these patches once you pull them in to "one tree" here ? We have changes coming up in the coresight tree, which would conflict with the changes here (horribly). FWIW, For patches 1 to 13 : Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Suzuki

1 year, 5 months

Re: [PATCH RESEND 1/2] dt-bindings: arm: qcom,coresight-tpda: drop redundant type from ports

by Suzuki K Poulose

Hi Krzysztof On 25/03/2024 10:40, Krzysztof Kozlowski wrote: > "in-ports" and "out-ports" are defined by graph schema, so defining its > type is redundant. > > Acked-by: Rob Herring <robh(a)kernel.org> > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski(a)linaro.org> Both patches look good to me. How would you like to pull this ? I could queue them for v6.10 via coresight tree. If you would like to take them, Acked-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> Suzuki > > --- > > No changes, but patches were split from previous set. First patch in > previouis series was being discussed, so let's just make these accepted. > > v1: https://lore.kernel.org/all/20231206115332.22712-1-krzysztof.kozlowski@lina… > --- > Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml > index ea3c5db6b52d..7fbd855a66a0 100644 > --- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml > +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml > @@ -66,13 +66,11 @@ properties: > - const: apb_pclk > > in-ports: > - type: object > description: | > Input connections from TPDM to TPDA > $ref: /schemas/graph.yaml#/properties/ports > > out-ports: > - type: object > description: | > Output connections from the TPDA to legacy CoreSight trace bus. > $ref: /schemas/graph.yaml#/properties/ports

1 year, 5 months

Re: [PATCH 1/4] dt-bindings: arm: qcom,coresight-funnel: Add label for multi-ouput

by Tingwei Zhang

On 3/21/2024 10:42 PM, Rob Herring wrote: > On Thu, Mar 21, 2024 at 04:32:04PM +0800, Tao Zhang wrote: >> Add new property "label" to label the source corresponding to the >> output connection. When the funnel supports multi-output, this >> property needs to be introduced to mark which source component a >> certain output connection corresponds to. >> >> Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> >> --- >> .../arm/arm,coresight-dynamic-funnel.yaml | 34 ++++++++++++++++--- >> 1 file changed, 30 insertions(+), 4 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> index 44a1041cb0fc..cde62c286d29 100644 >> --- a/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> +++ b/Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml >> @@ -66,13 +66,39 @@ properties: >> $ref: /schemas/graph.yaml#/properties/port >> >> out-ports: >> - $ref: /schemas/graph.yaml#/properties/ports >> - additionalProperties: false >> - >> + type: object >> properties: >> + "#address-cells": >> + const: 1 >> + >> + "#size-cells": >> + const: 0 >> + >> port: >> + type: object >> + >> + patternProperties: >> + '^port(@[0-7])?$': >> + type: object >> description: Output connection to CoreSight Trace bus >> - $ref: /schemas/graph.yaml#/properties/port > > Nope, now you have no constraints on port node properties. Please look > at how other bindings are done to add properties on endpoint node. > Thanks for pointing this out, Rob. Shall we ref port-base and endpoint-base then add new properties on endpoint? In this way, the redundant code from port schema is not required. >> + >> + patternProperties: >> + "^endpoint(@[0-9a-f]+)?$": >> + type: object >> + properties: >> + remote-endpoint: >> + description: | >> + phandle to an 'endpoint' subnode of a remote device node. >> + $ref: /schemas/types.yaml#/definitions/phandle > > Don't need this. > >> + label: >> + description: Label the source corresponding to the output connection >> + $ref: /schemas/types.yaml#/definitions/string > > label already has a type. > > As this node is an output, aren't you labeling what the destination is, > not the "source"? > > Why can't you look at the remote connection to identify what it is? > This funnel can route data stream from different trace source to different output ports. This lable property is added to describe which source is routed to this output port. For example, the graph is as below. Funnel3 routes trace data from TPDM0 to output[0] and output[0] of funnel3 is connected to input[0] of TPDA0. While Funnels routes trace data from TPDM1 to output[1] which connects to input[1] of TPDA0. Hope that clarifies this a little bit. |---------| |---------| |---------| |---------| |---------| | TPDM0 | | TPDM1 | | TPDM2 | | TPDM3 | | TPDM4 | |---------| |---------| |---------| |---------| |---------| | | | | | | | | | | | | | | | |-----| |-----| |-----| |-----| | | | | | | | | | | | [0]| |[1] [0]| |[1] | \-------------/ \-------------/ \------------/ \ FUNNEL0 / \ FUNNEL1 / \ FUNNEL2 / ----------- ----------- ----------- | | | \-------------/ \-------------/ | \ FUNNEL3 / \ FUNNEL4 / | ----------- ----------- | | | | | [0]| |[1] [0]| |[1] | | |---------- | | | | | | | | |-------| | |------- | | |--------- | | | | | | | | | | | [0]| |[1] |[2] |[3] |[4] \ ---------------------------------------------------/ \ TPDA0 / \ / ------------------------------------------------ > >> + oneOf: >> + - required: >> + - port >> + - required: >> + - "#address-cells" >> + - "#size-cells" > > The common schema that you removed handles this. > > Rob -- Thanks, Tingwei

1 year, 5 months

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