CoreSight

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Re: [PATCH v5 04/10] coresight: Appropriately disable programming clocks

by Suzuki K Poulose

On 29/07/2025 12:31, Mark Brown wrote: > On Mon, Jul 28, 2025 at 05:45:04PM +0100, Mark Brown wrote: >> On Thu, Jul 24, 2025 at 04:22:34PM +0100, Leo Yan wrote: >> >> Previously we would return NULL for any error (which isn't super great >> for deferred probe but never mind). >> >>> + pclk = devm_clk_get_enabled(dev, "apb_pclk"); >>> + if (IS_ERR(pclk)) >>> + pclk = devm_clk_get_enabled(dev, "apb"); >> >> ... >> >>> return pclk; >>> } >> >> Now we pass errors back to the caller, making missing clocks fatal. > > Thinking about this some more I think for compatiblity these clocks need > to be treated as optional - that's what the original code was > effectively doing, and I can imagine this isn't the only SoC which has > (hopefully) always on clocks and didn't wire things up in DT. You're right. The static components (funnels, replicators) don't have APB programming interface and hence no clocks. That said, may be the "is amba device" check could be used to enforce the presence of a clock. I will let Leo sort this out Suzuki

3 weeks, 5 days

[PATCH v5 00/10] coresight: Fix and improve clock usage

by Leo Yan

This series fixes and improves clock usage in the Arm CoreSight drivers. Based on the DT binding documents, the trace clock (atclk) is defined in some CoreSight modules, but support is absent. In most cases, the issue is hidden because the atclk clock is shared by multiple CoreSight modules and the clock is enabled anyway by other drivers. The first three patches address this issue. The programming clock (pclk) management in CoreSight drivers does not use the devm_XXX() variant APIs, the drivers needs to manually disable and release clocks for errors and for normal module exit. However, the drivers miss to disable clocks during module exit. The atclk may also not be disabled in CoreSight drivers during module exit. By using devm APIs, patches 04 and 05 fix clock disabling issues. Another issue is pclk might be enabled twice in init phase - once by AMBA bus driver, and again by CoreSight drivers. This is fixed in patch 06. Patches 07 to 10 refactor the clock related code. Patch 07 consolidates the clock initialization into a central place. Patch 08 polishes driver data allocation. Patch 09 makes the clock enabling sequence consistent. Patch 09 removes redundant condition checks and adds error handling in runtime PM. This series has been verified on Arm64 Juno platform, for both DT and ACPI modes. --- Changes in v5: - Skip clock management for ACPI devices (Suzuki). - Link to v4: https://lore.kernel.org/r/20250627-arm_cs_fix_clock_v4-v4-0-0ce0009c38f8@ar… Changes in v4: - Separated patch 07 into two patches, one is for clock consolidation and another is for polishing driver data allocation (Anshuman). Changes in v3: - Updated subjects for patches 04 and 05 (Anshuman). - Refined condition checking "if (dev_is_amba(dev))" in patch 07 (Anshuman). --- Leo Yan (10): coresight: tmc: Support atclk coresight: catu: Support atclk coresight: etm4x: Support atclk coresight: Appropriately disable programming clocks coresight: Appropriately disable trace bus clocks coresight: Avoid enable programming clock duplicately coresight: Consolidate clock enabling coresight: Refactor driver data allocation coresight: Make clock sequence consistent coresight: Refactor runtime PM drivers/hwtracing/coresight/coresight-catu.c | 53 ++++++++--------- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-core.c | 48 ++++++++++++++++ drivers/hwtracing/coresight/coresight-cpu-debug.c | 41 +++++--------- drivers/hwtracing/coresight/coresight-ctcu-core.c | 24 +++----- drivers/hwtracing/coresight/coresight-etb10.c | 18 ++---- drivers/hwtracing/coresight/coresight-etm3x-core.c | 17 ++---- drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 ++++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- drivers/hwtracing/coresight/coresight-funnel.c | 66 ++++++++-------------- drivers/hwtracing/coresight/coresight-replicator.c | 63 ++++++++------------- drivers/hwtracing/coresight/coresight-stm.c | 34 +++++------ drivers/hwtracing/coresight/coresight-tmc-core.c | 48 ++++++++-------- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpiu.c | 36 +++++------- include/linux/coresight.h | 31 +--------- 16 files changed, 228 insertions(+), 290 deletions(-) --- base-commit: a80198ba650f50d266d7fc4a6c5262df9970f9f2 change-id: 20250627-arm_cs_fix_clock_v4-e24b1e1f8920 Best regards, -- Leo Yan <leo.yan(a)arm.com>

3 weeks, 6 days

Re: [PATCH v6 0/7] Provides support for Trigger Generation Unit

by Mike Leach

Hi, On Wed, 23 Jul 2025 at 07:33, Songwei Chai <quic_songchai(a)quicinc.com> wrote: > > > On 7/21/2025 9:39 PM, Mike Leach wrote: > > Hi, > > On Wed, 9 Jul 2025 at 11:41, songchai <songchai(a)qti.qualcomm.com> wrote: > > From: Songwei Chai <quic_songchai(a)quicinc.com> > > Provide support for the TGU (Trigger Generation Unit), which can be > utilized to sense a plurality of signals and create a trigger into > the CTI or generate interrupts to processors once the input signal > meets the conditions. We can treat the TGU’s workflow as a flowsheet, > it has some “steps” regions for customization. In each step region, > we can set the signals that we want with priority in priority_group, set > the conditions in each step via condition_decode, and set the resultant > action by condition_select. Meanwhile, some TGUs (not all) also provide > timer/counter functionality. Based on the characteristics described > above, we consider the TGU as a helper in the CoreSight subsystem. > Its master device is the TPDM, which can transmit signals from other > subsystems, and we reuse the existing ports mechanism to link the TPDM to > the connected TGU. > > Here is a detailed example to explain how to use the TGU: > > In this example, the TGU is configured to use 2 conditions, 2 steps, and > the timer. The goal is to look for one of two patterns which are generated > from TPDM, giving priority to one, and then generate a trigger once the > timer reaches a certain value. In other words, two conditions are used > for the first step to look for the two patterns, where the one with the > highest priority is used in the first condition. Then, in the second step, > the timer is enabled and set to be compared to the given value at each > clock cycle. These steps are better shown below. > > |-----------------| > | | > | TPDM | > | | > |-----------------| > | > | > --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ------ > | | | > | | |--------------------| | > | |---- ---> | | Go to next steps | | > | | | |--- ---> | Enable timer | | > | | v | | | | > | | |-----------------| | |--------------------| | > | | | | Yes | | | > | | | inputs==0xB | ----->| | <-------- | > | | | | | | No | | > | No | |-----------------| | v | | > | | | | |-----------------| | | > | | | | | | | | > | | | | | timer>=3 |-- | > | | v | | | | > | | |-----------------| | |-----------------| | > | | | | Yes | | | > | |--- | inputs==0xA | ----->| | Yes | > | | | | | > | |-----------------| v | > | |-----------------| | > | | | | > | | Trigger | | > | | | | > | |-----------------| | > | TGU | | > |--- --- --- --- --- --- --- --- --- --- --- --- --- --- |--- --- -- | > | > v > |-----------------| > |The controllers | > |which will use | > |triggers further | > |-----------------| > > steps: > 1. Reset TGU /*it will disable tgu and reset dataset*/ > - echo 1 > /sys/bus/coresight/devices/<tgu-name>/reset_tgu > > 2. Set the pattern match for priority0 to 0xA = 0b1010 and for > priority 1 to 0xB = 0b1011. > - echo 0x11113232 > /sys/bus/coresight/devices/<tgu-name>/step0_priority0/reg0 > - echo 0x11113233 > /sys/bus/coresight/devices/<tgu-name>/step0_priority1/reg0 > > Note: > Bit distribution diagram for each priority register > |-------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 29:28 | SEL_BIT7_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 25:24 | SEL_BIT6_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 21:20 | SEL_BIT5_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 17:16 | SEL_BIT4_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 13:12 | SEL_BIT3_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 9:8 | SEL_BIT2_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 5:4 | SEL_BIT1_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > | | | 00 = bypass for OR output | > | 1:0 | SEL_BIT0_TYPE2 | 01 = bypass for AND output | > | | | 10 = sense input '0' is true| > | | | 11 = sense input '1' is true| > |-------------------------------------------------------------------| > These bits are used to identify the signals we want to sense, with > a maximum signal number of 140. For example, to sense the signal > 0xA (binary 1010), we set the value of bits 0 to 13 to 3232, which > represents 1010. The remaining bits are set to 1, as we want to use > AND gate to summarize all the signals we want to sense here. For > rising or falling edge detection of any input to the priority, set > the remaining bits to 0 to use an OR gate. > > 3. look for the pattern for priority_i i=0,1. > - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg0 > - echo 0x30 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_decode/reg1 > > |-------------------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-------------------------------------------------------------------------------| > | | |For each decoded condition, this | > | 24 | NOT |inverts the output. If the condition | > | | |decodes to true, and the NOT field | > | | |is '1', then the output is NOT true. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 21 | BC0_COMP_ACTIVE |comparator will be actively included in| > | | |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 20 | BC0_COMP_HIGH |the decoding of this condition. | > | | |Conversely, a '0' here requires a '0' | > | | |from the comparator | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 17 | |comparator will be actively included in| > | | TC0_COMP_ACTIVE |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 16 | TC0_COMP_HIGH |the decoding of this particular | > | | |condition.Conversely, a 0 here | > | | |requires a '0' from the comparator | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |OR logic will be actively | > | 4n+3 | Priority_n_OR_ACTIVE|included in the decoding of | > | | (n=0,1,2,3) |this particular condition. | > | | | | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |will need to be '1' to affect the | > | 4n+2 | Priority_n_OR_HIGH |decoding of this particular | > | | (n=0,1,2,3) |condition. Conversely, a '0' here | > | | |requires a '0' from Priority_n OR logic| > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |AND logic will be actively | > | 4n+1 |Priority_n_AND_ACTIVE|included in the decoding of this | > | | (n=0,1,2,3) |particular condition. | > | | | | > |-------------------------------------------------------------------------------| > | | |When '1' the output from Priority_n | > | | |AND logic will need to be '1' to | > | 4n | Priority_n_AND_HIGH |affect the decoding of this | > | | (n=0,1,2,3) |particular condition. Conversely, | > | | |a '0' here requires a '0' from | > | | |Priority_n AND logic. | > |-------------------------------------------------------------------------------| > Since we use `priority_0` and `priority_1` with an AND output in step 2, we set `0x3` > and `0x30` here to activate them. > > 4. Set NEXT_STEP = 1 and TC0_ENABLE = 1 so that when the conditions > are met then the next step will be step 1 and the timer will be enabled. > - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg0 > - echo 0x20008 > /sys/bus/coresight/devices/<tgu-name>/step0_condition_select/reg1 > > |-----------------------------------------------------------------------------| > | Bits | Field Nam | Description | > |-----------------------------------------------------------------------------| > | | |This field defines the next step the | > | 18:17 | NEXT_STEP |TGU will 'goto' for the associated | > | | |Condition and Step. | > |-----------------------------------------------------------------------------| > | | |For each possible output trigger | > | 13 | TRIGGER |available, set a '1' if you want | > | | |the trigger to go active for the | > | | |associated condition and Step. | > |-----------------------------------------------------------------------------| > | | |This will cause BC0 to increment if the| > | 9 | BC0_INC |associated Condition is decoded for | > | | |this step. | > |-----------------------------------------------------------------------------| > | | |This will cause BC0 to decrement if the| > | 8 | BC0_DEC |associated Condition is decoded for | > | | |this step. | > |-----------------------------------------------------------------------------| > | | |This will clear BC0 count value to 0 if| > | 7 | BC0_CLEAR |the associated Condition is decoded | > | | |for this step. | > |-----------------------------------------------------------------------------| > | | |This will cause TC0 to increment until | > | 3 | TC0_ENABLE |paused or cleared if the associated | > | | |Condition is decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will cause TC0 to pause until | > | 2 | TC0_PAUSE |enabled if the associated Condition | > | | |is decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will clear TC0 count value to 0 | > | 1 | TC0_CLEAR |if the associated Condition is | > | | |decoded for this step. | > |-----------------------------------------------------------------------------| > | | |This will set the done signal to the | > | 0 | DONE |TGU FSM if the associated Condition | > | | |is decoded for this step. | > |-----------------------------------------------------------------------------| > Based on the distribution diagram, we set `0x20008` for `priority0` and `priority1` to > achieve "jump to step 1 and enable TC0" once the signal is sensed. > > 5. activate the timer comparison for this step. > - echo 0x30000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_decode/reg0 > > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | 17 | |comparator will be actively included in| > | | TC0_COMP_ACTIVE |the decoding of this particular | > | | |condition. | > |-------------------------------------------------------------------------------| > | | |When '1' the output from the associated| > | | |comparator will need to be 1 to affect | > | 16 | TC0_COMP_HIGH |the decoding of this particular | > | | |condition.Conversely, a 0 here | > | | |requires a '0' from the comparator | > |-------------------------------------------------------------------------------| > Accroding to the decode distribution diagram , we give 0x30000 here to set 16th&17th bit > to enable timer comparison. > > 6. Set the NEXT_STEP = 0 and TC0_PAUSE = 1 and TC0_CLEAR = 1 once the timer > has reached the given value. > - echo 0x6 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/reg0 > > 7. Enable Trigger 0 for TGU when the condition 0 is met in step1, > i.e. when the timer reaches 3. > - echo 0x2000 > /sys/bus/coresight/devices/<tgu-name>/step1_condition_select/default > > Note: > 1. 'default' register allows for establishing the resultant action for > the default condition > > 2. Trigger:For each possible output trigger available from > the Design document, there are three triggers: interrupts, CTI, > and Cross-TGU mapping.All three triggers can occur, but > the choice of which trigger to use depends on the user's > needs. > > 8. Compare the timer to 3 in step 1. > - echo 0x3 > /sys/bus/coresight/devices/<tgu-name>/step1_timer/reg0 > > 9. enale tgu > - echo 1 > /sys/bus/coresight/devices/<tgu-name>/enable_tgu > --- > Link to V5: https://lore.kernel.org/all/20250529081949.26493-1-quic_songchai@quicinc.co… > > Changes in V6: > - Replace spinlock with guard(spinlock) in tgu_enable. > - Remove redundant blank line. > - Update publish date and contact member's name in "sysfs-bus-coresight-devices-tgu". > --- > Link to V4: https://patchwork.kernel.org/project/linux-arm-msm/cover/20250423101054.954… > > Changes in V5: > - Update publish date and kernel_version in "sysfs-bus-coresight-devices-tgu" > --- > Link to V3: https://lore.kernel.org/all/20250227092640.2666894-1-quic_songchai@quicinc.… > > Changes in V4: > - Add changlog in coverletter. > - Correct 'year' in Copyright in patch1. > - Correct port mechansim description in patch1. > - Remove 'tgu-steps','tgu-regs','tgu-conditions','tgu-timer-counters' from dt-binding > and set them through reading DEVID register as per Mike's suggestion. > - Modify tgu_disable func to make it have single return point in patch2 as per > Mike's suggestion. > - Use sysfs_emit in enable_tgu_show func in ptach2. > - Remove redundant judgement in enable_tgu_store in patch2. > - Correct typo in description in patch3. > - Set default ret as SYSFS_GROUP_INVISIBLE, and returnret at end in pacth3 as > per Mike's suggestion. > - Remove tgu_dataset_ro definition in patch3 > - Use #define constants with explanations of what they are rather than > arbitrary magic numbers in patch3 and patch4. > - Check -EINVAL before using 'calculate_array_location()' in array in patch4. > - Add 'default' in 'tgu_dataset_show''s switch part in patch4. > - Document the value needed to initiate the reset in pacth7. > - Check "value" in 'reset_tgu_store' and bail out with an error code if 0 in patch7. > - Remove dev_dbg in 'reset_tgu_store' in patch7. > --- > Link to V2: https://lore.kernel.org/all/20241010073917.16023-1-quic_songchai@quicinc.co… > > Changes in V3: > - Correct typo and format in dt-binding in patch1 > - Rebase to the latest kernel version > --- > Link to V1: https://lore.kernel.org/all/20240830092311.14400-1-quic_songchai@quicinc.co… > > Changes in V2: > - Use real name instead of login name, > - Correct typo and format in dt-binding and code. > - Bring order in tgu_prob(declarations with and without assignments) as per > Krzysztof's suggestion. > - Add module device table in patch2. > - Set const for tgu_common_grp and tgu_ids in patch2. > - Initialize 'data' in tgu_ids to fix the warning in pacth2. > --- > > Songwei Chai (7): > dt-bindings: arm: Add support for Coresight TGU trace > coresight: Add coresight TGU driver > coresight-tgu: Add signal priority support > coresight-tgu: Add TGU decode support > coresight-tgu: add support to configure next action > coresight-tgu: add timer/counter functionality for TGU > coresight-tgu: add reset node to initialize > > .../testing/sysfs-bus-coresight-devices-tgu | 51 ++ > .../bindings/arm/qcom,coresight-tgu.yaml | 92 +++ > drivers/hwtracing/coresight/Kconfig | 11 + > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-tgu.c | 776 ++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tgu.h | 255 ++++++ > 6 files changed, 1186 insertions(+) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tgu > create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tgu.yaml > create mode 100644 drivers/hwtracing/coresight/coresight-tgu.c > create mode 100644 drivers/hwtracing/coresight/coresight-tgu.h > > > As per the discussion here in v3 of this patchset > > https://lists.infradead.org/pipermail/linux-arm-kernel/2025-March/1012896.h… > > this component is primarily a part of the qualcom proprietary QPMDA > subsystem, and is capable of operating independently from the > CoreSight hardware trace generation system. > > The only link to Coresight is via the trigger input to CTI > component(s). CTI triggers can either be part of the ARM architected > or recommended connections between Coresight infrastructure from the > coresight specs and TRM documents, or platform specific triggers from > components external to coresight. For example on the Juno board a > trigger from the PL011 serial port is input to one of the system CTIs > on the board. > > Having Coresight management registers does not necessarily mean that > the component should be maintained under the hwtracing/coresight. Some > ARM Corelink interconnect components have the capability to generate > ATB trace into the coresight subsystem, and have some of the coresight > management registers. However, I would not expect the drivers for > these components to appear in hwtracing/coresight. > > As such this component could probably be better managed and maintained > as part of the /drivers/soc/qcom or similar area. > > The only changes to the Coresight infrastructure you should need to > get this component connected, is to alter the CTI declaration in board > device tree to add the incoming trigger as per the CTI bindings. > > Regards > > Mike > > Hi Mike, > > Thank you very much for your detailed feedback and for pointing out the architectural considerations > regarding the component's relationship with Coresight and the QPMDA subsystems. We fully understand > and appreciate your perspective on keeping the driver organization clean and aligned with subsystem boundaries. > > However, we would like to offer a slightly different view regarding the placement of this driver: > The TGU driver here exposes sysfs interfaces for user interaction and configuration. This kind of interface is generally not acceptable > under /driver/soc/qcom, which is typically reserved for passive platform drivers without user-facing interfaces. > > Given this, we'd like to ask your opinion on an alternative: > Would it be acceptable to create a new sub directory under /hwtracing/qcom to host this driver? > Alternatively, we could consider placing it under /driver/misc if that's more appropriate. > > Our preference would be place it under /driver/hwtracing/qcom, as this would provide a natural > home form Qualcomm-specific trace-related components that are adjacent to, but not strictly > part of, the Coresight architecture. This could also help organize future drivers that share similar > characteristics. > I am unsure on the procedure for creating new sub-directories for code in the kernel, but one key thing you do need is a maintainer for the code. The reason I suggested /driver/soc/qcom, was that this had qualcomm specific code with active maintainers. I recommend you consult with those responsible for maintaining qualcomm code within the kernel for the best course of action. Regards Mike > Looking forward to your thoughts. > > BRs, > Songwei > > > > > > -- > Mike Leach > Principal Engineer, ARM Ltd. > Manchester Design Centre. UK > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

3 weeks, 6 days

Re: [GIT PULL] coresight: updates for Linux v6.17

by Suzuki K Poulose

Hi Greg On 25/07/2025 10:47, Greg KH wrote: > On Fri, Jul 25, 2025 at 10:21:21AM +0100, Suzuki K Poulose wrote: >> Hi Greg >> >> Apologies for the late pull request. Please find the updates for v6.17 >> >> Kindly pull >> >> Suzuki >> >> >> >> The following changes since commit 86731a2a651e58953fc949573895f2fa6d456841: >> >> Linux 6.16-rc3 (2025-06-22 13:30:08 -0700) >> >> are available in the Git repository at: >> >> git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.17 >> >> for you to fetch changes up to 2b52cf338d39d684a1c6af298e8204902c026aca: >> >> coresight: Refactor runtime PM (2025-07-25 09:47:13 +0100) >> >> ---------------------------------------------------------------- >> coresight: Updates for Linux v6.17 >> >> CoreSight selfhosted tracing subsystem updates for v6.17, includes: >> - Qualcomm CoreSight TNOC driver >> - Cleanup of CoreSight clocks for the subsystem >> - Miscellaneous fixes >> >> Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > This all is really late, I wanted to close my tree a few days ago :( > > As this hasn't even been in linux-next yet, and I need to send a pull > request for this on Monday, that's not going to give any time at all > here in linux-next. I understand. > > How about you wait until after -rc1 and then just send me 2 requests, > one for bugfixes, and one for new stuff for 6.18-rc1? I could get you one with the stuff that was already on -next, dropping the last series I merged. But I guess we can wait until the merge window as you suggested. Kind regards Suzuki > > thanks, > > greg k-h

1 month

[GIT PULL] coresight: updates for Linux v6.17

by Suzuki K Poulose

Hi Greg Apologies for the late pull request. Please find the updates for v6.17 Kindly pull Suzuki The following changes since commit 86731a2a651e58953fc949573895f2fa6d456841: Linux 6.16-rc3 (2025-06-22 13:30:08 -0700) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v6.17 for you to fetch changes up to 2b52cf338d39d684a1c6af298e8204902c026aca: coresight: Refactor runtime PM (2025-07-25 09:47:13 +0100) ---------------------------------------------------------------- coresight: Updates for Linux v6.17 CoreSight selfhosted tracing subsystem updates for v6.17, includes: - Qualcomm CoreSight TNOC driver - Cleanup of CoreSight clocks for the subsystem - Miscellaneous fixes Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> ---------------------------------------------------------------- Dan Carpenter (1): coresight: Fix a NULL vs IS_ERR() bug in probe James Clark (2): coresight: trbe: Add ISB after TRBLIMITR write coresight: Fix missing include for FIELD_GET Leo Yan (12): coresight: stm: Remove redundant NULL checks coresight: perf: Use %px for printing pointers coresight: tmc: Support atclk coresight: catu: Support atclk coresight: etm4x: Support atclk coresight: Appropriately disable programming clocks coresight: Appropriately disable trace bus clocks coresight: Avoid enable programming clock duplicately coresight: Consolidate clock enabling coresight: Refactor driver data allocation coresight: Make clock sequence consistent coresight: Refactor runtime PM Rob Herring (Arm) (1): hwtracing: coresight: Use of_reserved_mem_region_to_resource() for "memory-region" Yeoreum Yun (1): coresight: fix indentation error in cscfg_remove_owned_csdev_configs() Yuanfang Zhang (3): coresight: Only register perf symlink for sinks with alloc_buffer dt-bindings: arm: Add device Trace Network On Chip definition coresight: add coresight Trace Network On Chip driver .../bindings/arm/qcom,coresight-tnoc.yaml | 113 ++++++++++ drivers/hwtracing/coresight/Kconfig | 12 + drivers/hwtracing/coresight/Makefile | 1 + drivers/hwtracing/coresight/coresight-catu.c | 53 +++-- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-core.c | 54 ++++- drivers/hwtracing/coresight/coresight-cpu-debug.c | 41 ++-- drivers/hwtracing/coresight/coresight-ctcu-core.c | 24 +- drivers/hwtracing/coresight/coresight-etb10.c | 18 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 4 +- drivers/hwtracing/coresight/coresight-etm3x-core.c | 17 +- drivers/hwtracing/coresight/coresight-etm4x-core.c | 33 +-- .../hwtracing/coresight/coresight-etm4x-sysfs.c | 1 + drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- drivers/hwtracing/coresight/coresight-funnel.c | 66 ++---- drivers/hwtracing/coresight/coresight-replicator.c | 63 ++---- drivers/hwtracing/coresight/coresight-stm.c | 42 ++-- drivers/hwtracing/coresight/coresight-syscfg.c | 2 +- drivers/hwtracing/coresight/coresight-tmc-core.c | 70 +++--- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tnoc.c | 242 +++++++++++++++++++++ drivers/hwtracing/coresight/coresight-tpiu.c | 36 ++- drivers/hwtracing/coresight/coresight-trbe.c | 1 + drivers/hwtracing/coresight/ultrasoc-smb.h | 1 + include/linux/coresight.h | 31 +-- 25 files changed, 617 insertions(+), 315 deletions(-) create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml create mode 100644 drivers/hwtracing/coresight/coresight-tnoc.c

1 month

Re: [PATCH next] coresight: Fix a NULL vs IS_ERR() bug in probe

by Anshuman Khandual

On 17/07/25 1:08 AM, Dan Carpenter wrote: > The devm_ioremap_resource() function returns error pointers on error. > It never returns NULL. Update the error checking to match. > > Fixes: 26e20622a8ae ("coresight: add coresight Trace Network On Chip driver") > Signed-off-by: Dan Carpenter <dan.carpenter(a)linaro.org> > --- > drivers/hwtracing/coresight/coresight-tnoc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtracing/coresight/coresight-tnoc.c > index 0e4164707eea..d542df46ea39 100644 > --- a/drivers/hwtracing/coresight/coresight-tnoc.c > +++ b/drivers/hwtracing/coresight/coresight-tnoc.c > @@ -183,8 +183,8 @@ static int trace_noc_probe(struct amba_device *adev, const struct amba_id *id) > dev_set_drvdata(dev, drvdata); > > drvdata->base = devm_ioremap_resource(dev, &adev->res); > - if (!drvdata->base) > - return -ENOMEM; > + if (IS_ERR(drvdata->base)) > + return PTR_ERR(drvdata->base); > > spin_lock_init(&drvdata->spinlock); > Do we still have more similar instances in coresight ?

1 month

[PATCH v4 00/10] coresight: Fix and improve clock usage

by Leo Yan

This series fixes and improves clock usage in the Arm CoreSight drivers. Based on the DT binding documents, the trace clock (atclk) is defined in some CoreSight modules, but support is absent. In most cases, the issue is hidden because the atclk clock is shared by multiple CoreSight modules and the clock is enabled anyway by other drivers. The first three patches address this issue. The programming clock (pclk) management in CoreSight drivers does not use the devm_XXX() variant APIs, the drivers needs to manually disable and release clocks for errors and for normal module exit. However, the drivers miss to disable clocks during module exit. The atclk may also not be disabled in CoreSight drivers during module exit. By using devm APIs, patches 04 and 05 fix clock disabling issues. Another issue is pclk might be enabled twice in init phase - once by AMBA bus driver, and again by CoreSight drivers. This is fixed in patch 06. Patches 07 to 10 refactor the clock related code. Patch 07 consolidates the clock initialization into a central place. Patch 08 polishes driver data allocation. Patch 09 makes the clock enabling sequence consistent. Patch 09 removes redundant condition checks and adds error handling in runtime PM. This series has been verified on Arm64 Hikey960 and Juno platforms. Changes from v3: - Separated patch 07 into two patches, one is for clock consolidation and another is for polishing driver data allocation (Anshuman). Changes from v2: - Updated subjects for patches 04 and 05 (Anshuman). - Refined condition checking "if (dev_is_amba(dev))" in patch 07 (Anshuman). Changes from v1: - Moved the coresight_get_enable_clocks() function into CoreSight core layer (James). - Added comments for clock naming "apb_pclk" and "apb" (James). - Re-ordered patches for easier understanding (Anshuman). - Minor improvement for commit log in patch 01 (Anshuman). Signed-off-by: Leo Yan <leo.yan(a)arm.com> --- Leo Yan (10): coresight: tmc: Support atclk coresight: catu: Support atclk coresight: etm4x: Support atclk coresight: Appropriately disable programming clocks coresight: Appropriately disable trace bus clocks coresight: Avoid enable programming clock duplicately coresight: Consolidate clock enabling coresight: Refactor driver data allocation coresight: Make clock sequence consistent coresight: Refactor runtime PM drivers/hwtracing/coresight/coresight-catu.c | 53 ++++++++--------- drivers/hwtracing/coresight/coresight-catu.h | 1 + drivers/hwtracing/coresight/coresight-core.c | 46 +++++++++++++++ drivers/hwtracing/coresight/coresight-cpu-debug.c | 41 +++++--------- drivers/hwtracing/coresight/coresight-ctcu-core.c | 24 +++----- drivers/hwtracing/coresight/coresight-etb10.c | 18 ++---- drivers/hwtracing/coresight/coresight-etm3x-core.c | 17 ++---- drivers/hwtracing/coresight/coresight-etm4x-core.c | 32 ++++++----- drivers/hwtracing/coresight/coresight-etm4x.h | 4 +- drivers/hwtracing/coresight/coresight-funnel.c | 66 ++++++++-------------- drivers/hwtracing/coresight/coresight-replicator.c | 63 ++++++++------------- drivers/hwtracing/coresight/coresight-stm.c | 34 +++++------ drivers/hwtracing/coresight/coresight-tmc-core.c | 48 ++++++++-------- drivers/hwtracing/coresight/coresight-tmc.h | 2 + drivers/hwtracing/coresight/coresight-tpiu.c | 36 +++++------- include/linux/coresight.h | 30 +--------- 16 files changed, 226 insertions(+), 289 deletions(-) --- base-commit: 67a993863163cb88b1b68974c31b0d84ece4293e change-id: 20250627-arm_cs_fix_clock_v4-e24b1e1f8920 Best regards, -- Leo Yan <leo.yan(a)arm.com>

1 month

Re: [PATCH v2] coresight: fix indentation error in cscfg_remove_owned_csdev_configs()

by Suzuki K Poulose

On Wed, 11 Jun 2025 11:30:25 +0100, Yeoreum Yun wrote: > Fix wrong indentation in cscfg_remove_owned_csdev_configs() > > Applied, thanks! [1/1] coresight: fix indentation error in cscfg_remove_owned_csdev_configs() https://git.kernel.org/coresight/c/a80198ba650f Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

1 month

Re: [PATCH v3 RESEND 04/10] coresight: ctcu: enable byte-cntr for TMC ETR devices

by Mike Leach

Hi, There are some parameters in the new structure that are unused in this patch. please only introduce fields when they start to be used to make review easier. Regards Mike On Mon, 14 Jul 2025 at 07:31, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > The byte-cntr function provided by the CTCU device is used to transfer data > from the ETR buffer to the userspace. An interrupt is triggered if the data > size exceeds the threshold set in the BYTECNTRVAL register. The interrupt > handler counts the number of triggered interruptions and the read function > will read the data from the ETR buffer. > > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > .../testing/sysfs-bus-coresight-devices-ctcu | 5 + > drivers/hwtracing/coresight/Makefile | 2 +- > .../coresight/coresight-ctcu-byte-cntr.c | 102 ++++++++++++++++++ > .../hwtracing/coresight/coresight-ctcu-core.c | 94 +++++++++++++++- > drivers/hwtracing/coresight/coresight-ctcu.h | 49 ++++++++- > 5 files changed, 246 insertions(+), 6 deletions(-) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > > diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu > new file mode 100644 > index 000000000000..e21f5bcb8097 > --- /dev/null > +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu > @@ -0,0 +1,5 @@ > +What: /sys/bus/coresight/devices/<ctcu-name>/irq_val > +Date: June 2025 > +KernelVersion: 6.16 > +Contact: Tingwei Zhang (QUIC) <quic_tingweiz(a)quicinc.com>; Jinlong Mao (QUIC) <quic_jinlmao(a)quicinc.com>; Jie Gan <jie.gan(a)oss.qualcomm.com> > +Description: (RW) Configure the IRQ value for byte-cntr register. > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile > index 4e7cc3c5bf99..3568d9768567 100644 > --- a/drivers/hwtracing/coresight/Makefile > +++ b/drivers/hwtracing/coresight/Makefile > @@ -54,5 +54,5 @@ coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \ > obj-$(CONFIG_ULTRASOC_SMB) += ultrasoc-smb.o > obj-$(CONFIG_CORESIGHT_DUMMY) += coresight-dummy.o > obj-$(CONFIG_CORESIGHT_CTCU) += coresight-ctcu.o > -coresight-ctcu-y := coresight-ctcu-core.o > +coresight-ctcu-y := coresight-ctcu-core.o coresight-ctcu-byte-cntr.o > obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) += coresight-kunit-tests.o > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > new file mode 100644 > index 000000000000..d3b6eb7a89fb > --- /dev/null > +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > @@ -0,0 +1,102 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#include <linux/coresight.h> > +#include <linux/device.h> > +#include <linux/fs.h> > +#include <linux/interrupt.h> > +#include <linux/of_irq.h> > +#include <linux/uaccess.h> > + > +#include "coresight-ctcu.h" > +#include "coresight-priv.h" > +#include "coresight-tmc.h" > + > +static irqreturn_t byte_cntr_handler(int irq, void *data) > +{ > + struct ctcu_byte_cntr *byte_cntr_data = (struct ctcu_byte_cntr *)data; > + > + atomic_inc(&byte_cntr_data->irq_cnt); > + wake_up(&byte_cntr_data->wq); > + > + byte_cntr_data->irq_num++; > + These two - irq_num & irq_cnt appear to count the same thing. Do not understand why one has to be atomic and the other does not. > + return IRQ_HANDLED; > +} > + > +/* Start the byte-cntr function when the path is enabled. */ > +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + struct coresight_device *sink = coresight_get_sink(path); > + struct ctcu_byte_cntr *byte_cntr_data; > + int port_num; > + > + if (!sink) > + return; > + > + port_num = coresight_get_port_helper(sink, csdev); > + if (port_num < 0) > + return; > + > + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; > + /* Don't start byte-cntr function when threshold is not set. */ > + if (!byte_cntr_data->thresh_val || byte_cntr_data->enable) > + return; > + > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + byte_cntr_data->enable = true; > + byte_cntr_data->reading_buf = false; > +} > + > +/* Stop the byte-cntr function when the path is disabled. */ > +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent); > + struct coresight_device *sink = coresight_get_sink(path); > + struct ctcu_byte_cntr *byte_cntr_data; > + int port_num; > + > + if (!sink || coresight_get_mode(sink) == CS_MODE_SYSFS) > + return; > + > + port_num = coresight_get_port_helper(sink, csdev); > + if (port_num < 0) > + return; > + > + byte_cntr_data = &drvdata->byte_cntr_data[port_num]; > + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); > + byte_cntr_data->enable = false; > +} > + > +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int etr_num) > +{ > + struct ctcu_byte_cntr *byte_cntr_data; > + struct device_node *nd = dev->of_node; > + int byte_cntr_irq, ret, i; > + > + for (i = 0; i < etr_num; i++) { > + byte_cntr_data = &drvdata->byte_cntr_data[i]; > + byte_cntr_irq = of_irq_get_byname(nd, byte_cntr_data->irq_name); > + if (byte_cntr_irq < 0) { > + dev_err(dev, "Failed to get IRQ from DT for %s\n", > + byte_cntr_data->irq_name); > + continue; > + } > + > + ret = devm_request_irq(dev, byte_cntr_irq, byte_cntr_handler, > + IRQF_TRIGGER_RISING | IRQF_SHARED, > + dev_name(dev), byte_cntr_data); > + if (ret) { > + dev_err(dev, "Failed to register IRQ for %s\n", > + byte_cntr_data->irq_name); > + continue; > + } > + > + byte_cntr_data->byte_cntr_irq = byte_cntr_irq; > + disable_irq(byte_cntr_data->byte_cntr_irq); > + init_waitqueue_head(&byte_cntr_data->wq); > + } > +} > diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hwtracing/coresight/coresight-ctcu-core.c > index 28ea4a216345..721836d42523 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c > +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c > @@ -15,6 +15,7 @@ > #include <linux/platform_device.h> > #include <linux/pm_runtime.h> > #include <linux/slab.h> > +#include <linux/sizes.h> > > #include "coresight-ctcu.h" > #include "coresight-priv.h" > @@ -45,17 +46,23 @@ DEFINE_CORESIGHT_DEVLIST(ctcu_devs, "ctcu"); > > #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) > #define CTCU_ATID_REG_SIZE 0x10 > +#define CTCU_ETR0_IRQCTRL 0x6c > +#define CTCU_ETR1_IRQCTRL 0x70 > #define CTCU_ETR0_ATID0 0xf8 > #define CTCU_ETR1_ATID0 0x108 > > static const struct ctcu_etr_config sa8775p_etr_cfgs[] = { > { > - .atid_offset = CTCU_ETR0_ATID0, > - .port_num = 0, > + .atid_offset = CTCU_ETR0_ATID0, > + .irq_ctrl_offset = CTCU_ETR0_IRQCTRL, > + .irq_name = "etr0", > + .port_num = 0, > }, > { > - .atid_offset = CTCU_ETR1_ATID0, > - .port_num = 1, > + .atid_offset = CTCU_ETR1_ATID0, > + .irq_ctrl_offset = CTCU_ETR1_IRQCTRL, > + .irq_name = "etr1", > + .port_num = 1, > }, > }; > > @@ -64,6 +71,76 @@ static const struct ctcu_config sa8775p_cfgs = { > .num_etr_config = ARRAY_SIZE(sa8775p_etr_cfgs), > }; > > +static void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offset) > +{ > + CS_UNLOCK(drvdata->base); > + ctcu_writel(drvdata, val, offset); > + CS_LOCK(drvdata->base); > +} > + > +static ssize_t irq_val_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); > + int i, len = 0; > + > + for (i = 0; i < ETR_MAX_NUM; i++) { > + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) > + len += scnprintf(buf + len, PAGE_SIZE - len, "%u ", > + drvdata->byte_cntr_data[i].thresh_val); > + } > + > + len += scnprintf(buf + len, PAGE_SIZE - len, "\n"); > + > + return len; > +} > + > +/* Program a valid value into IRQCTRL register will enable byte-cntr interrupt */ > +static ssize_t irq_val_store(struct device *dev, struct device_attribute *attr, > + const char *buf, size_t size) > +{ > + struct ctcu_drvdata *drvdata = dev_get_drvdata(dev->parent); > + u32 thresh_vals[ETR_MAX_NUM] = { 0 }; > + u32 irq_ctrl_offset; > + int num, i; > + > + num = sscanf(buf, "%i %i", &thresh_vals[0], &thresh_vals[1]); > + if (num <= 0 || num > ETR_MAX_NUM) > + return -EINVAL; > + > + /* Threshold 0 disables the interruption. */ > + guard(raw_spinlock_irqsave)(&drvdata->spin_lock); > + for (i = 0; i < num; i++) { > + /* A small threshold will result in a large number of interruptions */ > + if (thresh_vals[i] && thresh_vals[i] < SZ_4K) > + return -EINVAL; > + > + if (drvdata->byte_cntr_data[i].irq_ctrl_offset) { > + drvdata->byte_cntr_data[i].thresh_val = thresh_vals[i]; > + irq_ctrl_offset = drvdata->byte_cntr_data[i].irq_ctrl_offset; > + /* A one value for IRQCTRL register represents 8 bytes */ > + ctcu_program_register(drvdata, thresh_vals[i] / 8, irq_ctrl_offset); > + } > + } > + > + return size; > +} > +static DEVICE_ATTR_RW(irq_val); > + I think it may make more sense to call this something with "threshold" - as it is thresholds that are being set. > +static struct attribute *ctcu_attrs[] = { > + &dev_attr_irq_val.attr, > + NULL, > +}; > + > +static struct attribute_group ctcu_attr_grp = { > + .attrs = ctcu_attrs, > +}; > + > +static const struct attribute_group *ctcu_attr_grps[] = { > + &ctcu_attr_grp, > + NULL, > +}; > + > static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 reg_offset, > u8 bit, bool enable) > { > @@ -143,6 +220,8 @@ static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, void * > { > struct coresight_path *path = (struct coresight_path *)data; > > + ctcu_byte_cntr_start(csdev, path); > + > return ctcu_set_etr_traceid(csdev, path, true); > } > > @@ -150,6 +229,8 @@ static int ctcu_disable(struct coresight_device *csdev, void *data) > { > struct coresight_path *path = (struct coresight_path *)data; > > + ctcu_byte_cntr_stop(csdev, path); > + > return ctcu_set_etr_traceid(csdev, path, false); > } > > @@ -200,7 +281,11 @@ static int ctcu_probe(struct platform_device *pdev) > for (i = 0; i < cfgs->num_etr_config; i++) { > etr_cfg = &cfgs->etr_cfgs[i]; > drvdata->atid_offset[i] = etr_cfg->atid_offset; > + drvdata->byte_cntr_data[i].irq_name = etr_cfg->irq_name; > + drvdata->byte_cntr_data[i].irq_ctrl_offset = > + etr_cfg->irq_ctrl_offset; > } > + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); > } > } > > @@ -212,6 +297,7 @@ static int ctcu_probe(struct platform_device *pdev) > desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CTCU; > desc.pdata = pdata; > desc.dev = dev; > + desc.groups = ctcu_attr_grps; > desc.ops = &ctcu_ops; > desc.access = CSDEV_ACCESS_IOMEM(base); > > diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtracing/coresight/coresight-ctcu.h > index e9594c38dd91..71266371591b 100644 > --- a/drivers/hwtracing/coresight/coresight-ctcu.h > +++ b/drivers/hwtracing/coresight/coresight-ctcu.h > @@ -5,19 +5,27 @@ > > #ifndef _CORESIGHT_CTCU_H > #define _CORESIGHT_CTCU_H > + > +#include <linux/time.h> > #include "coresight-trace-id.h" > > /* Maximum number of supported ETR devices for a single CTCU. */ > #define ETR_MAX_NUM 2 > > +#define BYTE_CNTR_TIMEOUT (5 * HZ) > + > /** > * struct ctcu_etr_config > * @atid_offset: offset to the ATID0 Register. > - * @port_num: in-port number of CTCU device that connected to ETR. > + * @port_num: in-port number of the CTCU device that connected to ETR. > + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. > + * @irq_name: IRQ name in dt node. > */ > struct ctcu_etr_config { > const u32 atid_offset; > const u32 port_num; > + const u32 irq_ctrl_offset; > + const char *irq_name; > }; > > struct ctcu_config { > @@ -25,15 +33,54 @@ struct ctcu_config { > int num_etr_config; > }; > > +/** > + * struct ctcu_byte_cntr > + * @enable: indicates that byte_cntr function is enabled or not. > + * @reading: indicates that its byte-cntr reading. > + * @reading_buf: indicates that byte-cntr is reading buffer. > + * @thresh_val: threshold to trigger a interruption. > + * @total_size: total size of transferred data. > + * @byte_cntr_irq: IRQ number. > + * @irq_cnt: IRQ count. > + * @irq_num: number of the byte_cntr IRQ for one session. the difference between byte_cntr_irg and irq_cnt is not clear. > + * @wq: workqueue of reading ETR data. > + * @read_work: work of reading ETR data. > + * @spin_lock: spinlock of byte cntr data. > + * the byte cntr is stopped. > + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. > + * @irq_name: IRQ name in DT. > + */ > +struct ctcu_byte_cntr { > + bool enable; > + bool reading; This parameter is unused in this patch > + bool reading_buf; > + u32 thresh_val; > + u64 total_size; parameter unused in this patch > + int byte_cntr_irq; > + atomic_t irq_cnt; > + int irq_num; > + wait_queue_head_t wq; > + struct work_struct read_work; > + raw_spinlock_t spin_lock; > + u32 irq_ctrl_offset; > + const char *irq_name; > +}; > + > struct ctcu_drvdata { > void __iomem *base; > struct clk *apb_clk; > struct device *dev; > struct coresight_device *csdev; > + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; > raw_spinlock_t spin_lock; > u32 atid_offset[ETR_MAX_NUM]; > /* refcnt for each traceid of each sink */ > u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; > }; > > +/* Byte-cntr functions */ > +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight_path *path); > +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_path *path); > +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata, int port_num); > + > #endif > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

1 month

Re: [PATCH v3 RESEND 00/10] coresight: ctcu: Enable byte-cntr function for TMC ETR

by Mike Leach

Hi I have had a look at a few of the patches. The buffer swap mechanism appears to be good. However there is a lot of byte-ctr code in the "core" tmc / etr source files. As much of this code as possible needs to be moved to the byte-cntr specifc source. I suggest having a helper function such as qcom_byte_ctr_in_use() to call from the core code, and if true then call back into the byte-cntr specific code to do the specialist functionality. One other possibility is to have a flag / enum in the tmc->drvdata structure to indicate a variant. - e.g. TMC_STD, TMC_QCOM_BYTE_CTR, set at initialisation stage to remove the need for checking the device tree every call. Regards Mike On Mon, 14 Jul 2025 at 07:31, Jie Gan <jie.gan(a)oss.qualcomm.com> wrote: > > The byte-cntr function provided by the CTCU device is used to count the > trace data entering the ETR. An interrupt is triggered if the data size > exceeds the threshold set in the BYTECNTRVAL register. The interrupt > handler counts the number of triggered interruptions. > > Based on this concept, the irq_cnt can be used to determine whether > the etr_buf is full. The ETR device will be disabled when the active > etr_buf is nearly full or a timeout occurs. The nearly full buffer will > be switched to background after synced. A new buffer will be picked from > the etr_buf_list, then restart the ETR device. > > The byte-cntr reading functions can access data from the synced and > deactivated buffer, transferring trace data from the etr_buf to userspace > without stopping the ETR device. > > The byte-cntr read operation has integrated with the file node tmc_etr, > for example: > /dev/tmc_etr0 > /dev/tmc_etr1 > > There are two scenarios for the tmc_etr file node with byte-cntr function: > 1. BYTECNTRVAL register is configured and byte-cntr is enabled -> byte-cntr read > 2. BYTECNTRVAL register is reset or byte-cntr is disabled -> original behavior > > Shell commands to enable byte-cntr reading for etr0: > echo 0x10000 > /sys/bus/coresight/devices/ctcu0/irq_val > echo 1 > /sys/bus/coresight/devices/tmc_etr0/enable_sink > echo 1 > /sys/bus/coresight/devices/etm0/enable_source > cat /dev/tmc_etr0 > > Reset the BYTECNTR register for etr0: > echo 0 > /sys/bus/coresight/devices/ctcu0/irq_val > > Changes in V3 resend: > 1. rebased on next-20250711. > Link to V3 - https://lore.kernel.org/all/20250624060438.7469-1-jie.gan@oss.qualcomm.com/ > > Changes in V3: > 1. The previous solution has been deprecated. > 2. Add a etr_buf_list to manage allcated etr buffers. > 3. Add a logic to switch buffer for ETR. > 4. Add read functions to read trace data from synced etr buffer. > Link to V2 - https://lore.kernel.org/all/20250410013330.3609482-1-jie.gan@oss.qualcomm.c… > > Changes in V2: > 1. Removed the independent file node /dev/byte_cntr. > 2. Integrated the byte-cntr's file operations with current ETR file > node. > 3. Optimized the driver code of the CTCU that associated with byte-cntr. > 4. Add kernel document for the export API tmc_etr_get_rwp_offset. > 5. Optimized the way to read the rwp_offset according to Mike's > suggestion. > 6. Removed the dependency of the dts patch. > Link to V1 - https://lore.kernel.org/all/20250310090407.2069489-1-quic_jiegan@quicinc.co… > > Jie Gan (10): > coresight: core: Refactoring ctcu_get_active_port and make it generic > coresight: core: add a new API to retrieve the helper device > dt-bindings: arm: add an interrupt property for Coresight CTCU > coresight: ctcu: enable byte-cntr for TMC ETR devices > coresight: tmc: add etr_buf_list to store allocated etr_buf > coresight: tmc: add create/delete functions for etr_buf_node > coresight: tmc: add prepare/unprepare functions for byte-cntr > coresight: tmc: add a switch buffer function for byte-cntr > coresight: tmc: add read function for byte-cntr > arm64: dts: qcom: sa8775p: Add interrupts to CTCU device > > .../testing/sysfs-bus-coresight-devices-ctcu | 5 + > .../bindings/arm/qcom,coresight-ctcu.yaml | 17 ++ > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 5 + > drivers/hwtracing/coresight/Makefile | 2 +- > drivers/hwtracing/coresight/coresight-core.c | 54 ++++ > .../coresight/coresight-ctcu-byte-cntr.c | 102 +++++++ > .../hwtracing/coresight/coresight-ctcu-core.c | 113 ++++++-- > drivers/hwtracing/coresight/coresight-ctcu.h | 49 +++- > drivers/hwtracing/coresight/coresight-priv.h | 4 + > .../hwtracing/coresight/coresight-tmc-core.c | 70 ++++- > .../hwtracing/coresight/coresight-tmc-etr.c | 270 ++++++++++++++++++ > drivers/hwtracing/coresight/coresight-tmc.h | 29 ++ > 12 files changed, 688 insertions(+), 32 deletions(-) > create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu > create mode 100644 drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c > > -- > 2.34.1 > -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

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