CoreSight

coresight@lists.linaro.org

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2630 discussions

by Mike Leach

Version v0.11.0 release of OpenCSD library. * ETMv4 support updated to cover all ETM versions up to v4.4 (from v4.1 previously). This covers the latest v8.4 arch cores. * Updated memory callback function to pass trace ID to client when requesting memory data. Allows client to determine source CPU for the request and return memory images accordingly. (required for upcoming work on perf support.). * Other minor fixes and updates. -- Mike Leach Principal Engineer, ARM Ltd. Manchester Design Centre. UK

6 years, 11 months

Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660

by Shiwanglai

-----邮件原件----- 发件人: Leo Yan [mailto:leo.yan@linaro.org] 发送时间: 2019年3月1日 15:33 收件人: Shiwanglai <shiwanglai(a)hisilicon.com> 抄送: robh+dt(a)kernel.org; mark.rutland(a)arm.com; john.stultz(a)linaro.org; xuwei (O) <xuwei5(a)huawei.com>; linux-arm-kernel(a)lists.infradead.org; devicetree(a)vger.kernel.org; linux-kernel(a)vger.kernel.org; coresight(a)lists.linaro.org; Suzhuangluan <suzhuangluan(a)hisilicon.com> 主题: Re: [PATCH v2] dts: arm64: add CoreSight trace support for hi3660 Hi Wanglai, On Thu, Feb 28, 2019 at 02:33:23PM +0800, Wanglai Shi wrote: > This patch adds devicetree entries for the CoreSight trace components > on hi3660. > > Signed-off-by: Wanglai Shi <shiwanglai(a)hisilicon.com> > --- > .../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 429 +++++++++++++++++++++ > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 + > 2 files changed, 431 insertions(+) > create mode 100644 > arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi > b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi > new file mode 100644 > index 0000000..d651a8b > --- /dev/null > +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi > @@ -0,0 +1,429 @@ > +// SPDX-License-Identifier: GPL-2.0 > + > +/* > + * dtsi for Hisilicon Hi3660 Coresight > + * > + * Copyright (C) 2016-2018 Hisilicon Ltd. > + * > + * Author: Wanglai Shi <shiwanglai(a)hisilicon.com> > + * > + */ > +/ { > + soc { > + /* A53 cluster internals */ > + etm@ecc40000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0xecc40000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + cpu = <&cpu0>; > + > + out-ports { > + port { > + etm0_out: endpoint { > + remote-endpoint = > + <&cluster0_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@ecd40000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0xecd40000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + cpu = <&cpu1>; > + > + out-ports { > + port { > + etm1_out: endpoint { > + remote-endpoint = > + <&cluster0_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@ece40000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0xece40000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + cpu = <&cpu2>; > + > + out-ports { > + port { > + etm2_out: endpoint { > + remote-endpoint = > + <&cluster0_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@ecf40000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0xecf40000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + cpu = <&cpu3>; > + > + out-ports { > + port { > + etm3_out: endpoint { > + remote-endpoint = > + <&cluster0_funnel_in3>; > + }; > + }; > + }; > + }; > + > + funnel@ec801000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0 0xec801000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + cluster0_funnel_out: endpoint { > + remote-endpoint = > + <&cluster0_etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + cluster0_funnel_in0: endpoint { > + remote-endpoint = <&etm0_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + cluster0_funnel_in1: endpoint { > + remote-endpoint = <&etm1_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + cluster0_funnel_in2: endpoint { > + remote-endpoint = <&etm2_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + cluster0_funnel_in3: endpoint { > + remote-endpoint = <&etm3_out>; > + }; > + }; > + }; > + }; > + > + etf@ec802000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0xec802000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + cluster0_etf_in: endpoint { > + remote-endpoint = > + <&cluster0_funnel_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + cluster0_etf_out: endpoint { > + remote-endpoint = > + <&top_funnel_in0>; > + }; > + }; > + }; > + }; > + > + /* A73 cluster internals */ > + etm@ed440000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0xed440000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + cpu = <&cpu4>; > + > + out-ports { > + port { > + etm4_out: endpoint { > + remote-endpoint = > + <&cluster1_funnel_in0>; > + }; > + }; > + }; > + }; > + > + etm@ed540000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0xed540000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + cpu = <&cpu5>; > + > + out-ports { > + port { > + etm5_out: endpoint { > + remote-endpoint = > + <&cluster1_funnel_in1>; > + }; > + }; > + }; > + }; > + > + etm@ed640000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0xed640000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + cpu = <&cpu6>; > + > + out-ports { > + port { > + etm6_out: endpoint { > + remote-endpoint = > + <&cluster1_funnel_in2>; > + }; > + }; > + }; > + }; > + > + etm@ed740000 { > + compatible = "arm,coresight-etm4x", "arm,primecell"; > + reg = <0 0xed740000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + cpu = <&cpu7>; > + > + out-ports { > + port { > + etm7_out: endpoint { > + remote-endpoint = > + <&cluster1_funnel_in3>; > + }; > + }; > + }; > + }; > + > + funnel@ed001000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0 0xed001000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + out-ports { > + port { > + cluster1_funnel_out: endpoint { > + remote-endpoint = > + <&cluster1_etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + cluster1_funnel_in0: endpoint { > + remote-endpoint = <&etm4_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + cluster1_funnel_in1: endpoint { > + remote-endpoint = <&etm5_out>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + cluster1_funnel_in2: endpoint { > + remote-endpoint = <&etm6_out>; > + }; > + }; > + > + port@3 { > + reg = <3>; > + cluster1_funnel_in3: endpoint { > + remote-endpoint = <&etm7_out>; > + }; > + }; > + }; > + }; > + > + etf@ed002000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0xed002000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + cluster1_etf_in: endpoint { > + remote-endpoint = > + <&cluster1_funnel_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + cluster1_etf_out: endpoint { > + remote-endpoint = > + <&top_funnel_in1>; > + }; > + }; > + }; > + }; > + > + /* Top internals */ > + funnel@ec031000 { > + compatible = "arm,coresight-funnel", "arm,primecell"; > + reg = <0 0xec031000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + > + out-ports { > + port { > + top_funnel_out: endpoint { > + remote-endpoint = > + <&top_etf_in>; > + }; > + }; > + }; > + > + in-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + top_funnel_in0: endpoint { > + remote-endpoint = > + <&cluster0_etf_out>; > + }; > + }; > + > + port@1 { > + reg = <0>; Here should s/<0>/<1>; otherwise DTC will complain warning for mismatching between 'port@1' and 'reg = <0>'. -- if reg set to 1, then there's no data output from cluster 1 to top. > + /* there's an invisible funnel combo */ > + /* between clusters and top funnel */ -- for the above reason. > + top_funnel_in1: endpoint { > + remote-endpoint = > + <&cluster1_etf_out>; > + }; > + }; > + }; > + }; > + > + etf@ec036000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0xec036000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + top_etf_in: endpoint { > + remote-endpoint = > + <&top_funnel_out>; > + }; > + }; > + }; > + > + out-ports { > + port { > + top_etf_out: endpoint { > + remote-endpoint = > + <&replicator_in>; > + }; > + }; > + }; > + }; > + > + replicator { > + compatible = "arm,coresight-replicator"; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + replicator_in: endpoint { > + remote-endpoint = > + <&top_etf_out>; > + }; > + }; > + }; > + > + out-ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + replicator0_out0: endpoint { > + remote-endpoint = <&etr_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + replicator0_out1: endpoint { > + remote-endpoint = <&tpiu_in>; > + }; > + }; > + }; > + }; > + > + etr@ec033000 { > + compatible = "arm,coresight-tmc", "arm,primecell"; > + reg = <0 0xec033000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + etr_in: endpoint { > + remote-endpoint = > + <&replicator0_out0>; > + }; > + }; > + }; > + }; > + > + tpiu@ec032000 { > + compatible = "arm,coresight-tpiu", "arm,primecell"; > + reg = <0 0xec032000 0 0x1000>; > + clocks = <&crg_ctrl HI3660_PCLK>; > + clock-names = "apb_pclk"; > + > + in-ports { > + port { > + tpiu_in: endpoint { > + remote-endpoint = > + <&replicator0_out1>; > + }; > + }; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index a4a3d08..8f2fede 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -1246,3 +1246,5 @@ > }; > }; > }; > + > +#include "hi3660-coresight.dtsi" Except the up mentioned issue, this patch looks good to me. After applying this patch though I can see Coresight devices under /sys/bus/coresight, but I cannot capture ETM trace data by using below two commands: perf record -e cs_etm/(a)ec036000.etf/ --per-thread ./main perf record -e cs_etm/(a)ec033000.etr/ --per-thread ./main I checked perf report command with '-D' option, I can see the perf.data file doesn't contain any trace data from ETM. could you tell me which test command you are using? At my side I will debug a bit on my Hikey960 board and will keep you posted if find anything. -- my test command -- echo 1 > /sys/bus/coresight/devices/ec033000.etr -- echo 1 > /sys/bus/coresight/devices/ecc40000.etm/enable_source Thanks, Leo Yan

6 years, 11 months

[PATCH v2] dts: arm64: add CoreSight trace support for hi3660

by Wanglai Shi

This patch adds devicetree entries for the CoreSight trace components on hi3660. Signed-off-by: Wanglai Shi <shiwanglai(a)hisilicon.com> --- .../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 429 +++++++++++++++++++++ arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 + 2 files changed, 431 insertions(+) create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi new file mode 100644 index 0000000..d651a8b --- /dev/null +++ b/arch/arm64/boot/dts/hisilicon/hi3660-coresight.dtsi @@ -0,0 +1,429 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* + * dtsi for Hisilicon Hi3660 Coresight + * + * Copyright (C) 2016-2018 Hisilicon Ltd. + * + * Author: Wanglai Shi <shiwanglai(a)hisilicon.com> + * + */ +/ { + soc { + /* A53 cluster internals */ + etm@ecc40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xecc40000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu0>; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in0>; + }; + }; + }; + }; + + etm@ecd40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xecd40000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu1>; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in1>; + }; + }; + }; + }; + + etm@ece40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xece40000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu2>; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in2>; + }; + }; + }; + }; + + etm@ecf40000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xecf40000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu3>; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = + <&cluster0_funnel_in3>; + }; + }; + }; + }; + + funnel@ec801000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xec801000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + cluster0_funnel_out: endpoint { + remote-endpoint = + <&cluster0_etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + cluster0_funnel_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + cluster0_funnel_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + cluster0_funnel_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + cluster0_funnel_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + }; + }; + + etf@ec802000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xec802000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + cluster0_etf_in: endpoint { + remote-endpoint = + <&cluster0_funnel_out>; + }; + }; + }; + + out-ports { + port { + cluster0_etf_out: endpoint { + remote-endpoint = + <&top_funnel_in0>; + }; + }; + }; + }; + + /* A73 cluster internals */ + etm@ed440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xed440000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu4>; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in0>; + }; + }; + }; + }; + + etm@ed540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xed540000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu5>; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in1>; + }; + }; + }; + }; + + etm@ed640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xed640000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu6>; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in2>; + }; + }; + }; + }; + + etm@ed740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0 0xed740000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + cpu = <&cpu7>; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = + <&cluster1_funnel_in3>; + }; + }; + }; + }; + + funnel@ed001000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xed001000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + out-ports { + port { + cluster1_funnel_out: endpoint { + remote-endpoint = + <&cluster1_etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + cluster1_funnel_in0: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@1 { + reg = <1>; + cluster1_funnel_in1: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@2 { + reg = <2>; + cluster1_funnel_in2: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@3 { + reg = <3>; + cluster1_funnel_in3: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + etf@ed002000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xed002000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + cluster1_etf_in: endpoint { + remote-endpoint = + <&cluster1_funnel_out>; + }; + }; + }; + + out-ports { + port { + cluster1_etf_out: endpoint { + remote-endpoint = + <&top_funnel_in1>; + }; + }; + }; + }; + + /* Top internals */ + funnel@ec031000 { + compatible = "arm,coresight-funnel", "arm,primecell"; + reg = <0 0xec031000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + out-ports { + port { + top_funnel_out: endpoint { + remote-endpoint = + <&top_etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + top_funnel_in0: endpoint { + remote-endpoint = + <&cluster0_etf_out>; + }; + }; + + port@1 { + reg = <0>; + /* there's an invisible funnel combo */ + /* between clusters and top funnel */ + top_funnel_in1: endpoint { + remote-endpoint = + <&cluster1_etf_out>; + }; + }; + }; + }; + + etf@ec036000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xec036000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + top_etf_in: endpoint { + remote-endpoint = + <&top_funnel_out>; + }; + }; + }; + + out-ports { + port { + top_etf_out: endpoint { + remote-endpoint = + <&replicator_in>; + }; + }; + }; + }; + + replicator { + compatible = "arm,coresight-replicator"; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = + <&top_etf_out>; + }; + }; + }; + + out-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + replicator0_out0: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + + port@1 { + reg = <1>; + replicator0_out1: endpoint { + remote-endpoint = <&tpiu_in>; + }; + }; + }; + }; + + etr@ec033000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0 0xec033000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = + <&replicator0_out0>; + }; + }; + }; + }; + + tpiu@ec032000 { + compatible = "arm,coresight-tpiu", "arm,primecell"; + reg = <0 0xec032000 0 0x1000>; + clocks = <&crg_ctrl HI3660_PCLK>; + clock-names = "apb_pclk"; + + in-ports { + port { + tpiu_in: endpoint { + remote-endpoint = + <&replicator0_out1>; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a4a3d08..8f2fede 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1246,3 +1246,5 @@ }; }; }; + +#include "hi3660-coresight.dtsi" -- 2.7.4

6 years, 11 months

[RFC PATCH 0/5] Mods to extend ETMv4 support to ETM v4.4

by Mike Leach

Patchset updates ETMv4 trace decoder to support protocols up to ETMv4.4 Update of instruction decode library made to cover new instructions - primarily authenticated pointer calls and returns. Set will form part of next OpenCSD library release at 0.11.0 Mike Mike Leach (5): opencsd: ETMv4.4: update common types and etm 4 config opencsd: ETMv4.4: Update all decoders to init new parameters opencsd: ETMv4.4: Update instruction decoder. opencsd: ETMv4.4: protocol decoder modifications. opencsd: Update lib version decoder/include/i_dec/trc_i_decode.h | 1 + decoder/include/i_dec/trc_idec_arminst.h | 9 + .../include/opencsd/etmv4/trc_cmp_cfg_etmv4.h | 20 +- .../opencsd/etmv4/trc_etmv4_stack_elem.h | 3 +- .../opencsd/etmv4/trc_pkt_elem_etmv4i.h | 5 +- .../opencsd/etmv4/trc_pkt_types_etmv4.h | 137 ++++--- decoder/include/opencsd/ocsd_if_types.h | 11 +- decoder/include/opencsd/ocsd_if_version.h | 6 +- decoder/source/etmv4/trc_cmp_cfg_etmv4.cpp | 2 + .../source/etmv4/trc_pkt_decode_etmv4i.cpp | 24 ++ .../source/etmv4/trc_pkt_proc_etmv4i_impl.cpp | 374 ++++++++++++------ .../source/etmv4/trc_pkt_proc_etmv4i_impl.h | 75 ++-- decoder/source/i_dec/trc_i_decode.cpp | 50 ++- decoder/source/i_dec/trc_idec_arminst.cpp | 99 ++++- decoder/source/ocsd_code_follower.cpp | 1 + decoder/source/ptm/trc_pkt_decode_ptm.cpp | 1 + 16 files changed, 586 insertions(+), 232 deletions(-) -- 2.20.1

6 years, 11 months

Timestamps always 0x0 on Xilinx Zynq Ultrascale+

by Wojciech Żmuda

Hi, I'm trying to run Coresight on XIlinx Zynq Ultrascale+ with ZCU104 board. I have already made some progress, however I'm stuck on getting valid timestamp packets in the decoded trace. I'm using mainline Linux forked at v5.0-rc4. So far, I manually added Coresight nodes to DTS basing on the Ultrascale+ datasheet, since neither mainline Linux nor the Xilinx fork seem to have it. Looks like this step went fine, since I can see drivers reporting in dmesg and related sysfs nodes being registered: root@zynq:~# dmesg | grep -i coresight [ 3.745681] coresight-etm4x fec40000.etm0: CPU0: ETM v4.0 initialized [ 3.752318] coresight-etm4x fed40000.etm1: CPU1: ETM v4.0 initialized [ 3.758952] coresight-etm4x fee40000.etm2: CPU2: ETM v4.0 initialized [ 3.765587] coresight-etm4x fef40000.etm3: CPU3: ETM v4.0 initialized [ 3.772190] coresight-stm fe9c0000.stm: stm_register_device failed, probing deferred [ 3.780004] coresight-cpu-debug fec10000.debug0: Coresight debug-CPU0 initialized [ 3.787531] coresight-cpu-debug fed10000.debug1: Coresight debug-CPU1 initialized [ 3.795058] coresight-cpu-debug fee10000.debug2: Coresight debug-CPU2 initialized [ 3.802587] coresight-cpu-debug fef10000.debug3: Coresight debug-CPU3 initialized [ 3.917423] coresight-stm fe9c0000.stm: STM500 initialized root@zynq:~# ls /sys/bus/coresight/devices/ fe920000.funnel1 fe940000.etf1 fe970000.etr fe9c0000.stm fed40000.etm1 fef40000.etm3 fe930000.funnel2 fe950000.etf2 fe980000.tpiu fec40000.etm0 fee40000.etm2 replicator Overall trace acquisition and decoding with perf+OpenCSD also looks good, apart from timestamp packets. When I request timestamping, the value is constant 0x0: root@zynq:~/cs_test# perf record -e cs_etm/timestamp,(a)fe940000.etf1/u --filter 'filter 0x764/0x2c@./sum' --per-thread ./sum Val: 20 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.002 MB perf.data ] root@zynq:~/cs_test# perf report --dump | grep TIMESTAMP Idx:231; ID:12; I_TIMESTAMP : Timestamp.; Updated val = 0x0 Idx:254; ID:12; I_TIMESTAMP : Timestamp.; Updated val = 0x0 Idx:279; ID:12; I_TIMESTAMP : Timestamp.; Updated val = 0x0 According to the datasheet, Ultrascale+ has a timestamp generator. Perf confirms it in the registers values dump: root@zynq:~/cs_test# perf report --dump | grep 'TRCCONFIGR\|TRCIDR0' TRCCONFIGR 800 TRCIDR0 28000ea1 TRCCONFIGR 800 TRCIDR0 28000ea1 TRCCONFIGR 800 TRCIDR0 28000ea1 TRCCONFIGR 800 TRCIDR0 28000ea1 These value match what ETMv4 architecture specs says: - bit 11 (TS) of TRCCONFIGR is 1, what indicates global timestamping is enabled - bits 24:28 (TSSIZE) of TRCIDR0 are 0b1000, what indicates support for 64-bit-long timestamps In the kernel source code I can see that the ETMv4 driver writes the EVENT bits (0:7) of the TRCTSCTLR register. I didn't thoroughly analyze this code, but I take it as another hint that timestamping is actually supported. At this point I wonder if anybody has witnessed timestamps working on this platform, whether under Linux or baremetal. I would appreciate even the tiniest suggestions where should I look next to get them working. Thanks and best regards, Wojciech

6 years, 11 months

Database Sellers

by Katherine Allison

Hi, Can I send you a Price of one of our Database Sellers based on your requirement? Kindly just share your requirements by filling in the below table: Industries : ----------------------- Job Titles : ----------------------- Geography : ---------------------- I'll come up with the data counts, costs & few sample contacts for your review. Regards, Katherine Allison Business Development

6 years, 11 months

[v5.0-rc6 regression] "perf/core: Don't WARN() for impossible ring-buffer sizes"

by Mathieu Poirier

Hi Mark, CoreSight trace collection is broken on v5.0-rc6 due to this commit: 9dff0aa95a32 perf/core: Don't WARN() for impossible ring-buffer sizes Before: root@juno:/home/linaro# perf record -e cs_etm/(a)20070000.etr/u --per-thread uname [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.036 MB perf.data ] root@juno:/home/linaro# After: root@juno:/home/linaro# perf record -e cs_etm/(a)20070000.etr/u --per-thread uname failed to mmap with 12 (Cannot allocate memory) root@juno:/home/linaro# The problem is related to the order_base_2() [1] test with a size of 1264, stemming from nr_pages equal to 128. The combination yields an order of 11, something leading directly to the error path. The results are the same with linux-next 20190213. This was tested on a Juno R0 and R1 with a 4K page configuration. I haven't tried but I'm pretty sure it breaks IntelPT as well. Please have a look when you have a minute. Leo Yan and I will be happy to test patches. Thanks, Mathieu [1]. https://elixir.bootlin.com/linux/v5.0-rc6/source/kernel/events/ring_buffer.…

6 years, 12 months

[v5.0-rc6 regression] "perf/core: Don't WARN() for impossible ring-buffer sizes"

by Mathieu Poirier

6 years, 12 months

Fwd: HEADS UP: disable building with opencsd by default

by Mathieu Poirier

This is important - see below. Once this change is released I will send a patch to update the HOWTO.md on github. Mathieu ---------- Forwarded message --------- From: Arnaldo Carvalho de Melo <acme(a)kernel.org> Date: Tue, 12 Feb 2019 at 11:04 Subject: HEADS UP: disable building with opencsd by default To: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Jiri Olsa <jolsa(a)kernel.org>, Kim Phillips <kim.phillips(a)arm.com>, < linux-arm-kernel(a)lists.infradead.org>, Mike Leach <mike.leach(a)arm.com>, Namhyung Kim <namhyung(a)kernel.org>, Peter Zijlstra <peterz(a)infradead.org>, Suzuki Poulouse <suzuki.poulose(a)arm.com>, Ingo Molnar <mingo(a)kernel.org> Please see the rationale on the cset, this test-all.c thing was done by Ingo long ago to speed up the build of the tools by checking first if the common set of libraries is present, and because this isn't being properly checked I left several cases pass, like opencsd, libaio and libcrypto, that I'm working as well and have fixes in my perf/core branch. - Arnaldo commit b7213083e3f3d69fffb5229034b3ac3ca9d41038 Author: Arnaldo Carvalho de Melo <acme(a)redhat.com> Date: Tue Feb 12 14:37:15 2019 -0300 perf coresight: Do not test for libopencsd by default Since it is not yet that generally available, avoid testing for the presence of libcoresight in the fast path test-all.bin feature test. # dnf search opencsd No matches found. # dnf search OpenCSD No matches found. # cat /etc/fedora-release Fedora release 29 (Twenty Nine) # I.e. right now, in my system test-all.bin is failing all the time since Fedora29 doesn't have libopencsd available: $ cat /tmp/build/perf/feature/test-all.make.output In file included from test-all.c:174: test-libopencsd.c:2:10: fatal error: opencsd/c_api/opencsd_c_api.h: No such file or directory #include <opencsd/c_api/opencsd_c_api.h> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. See: 6ab2b762befd ("perf build: Disable libbabeltrace check by default") For the rationale, as soon as libopencsd becomes more generally packaged and available, we do the same thing we did with babeltrace, enabling it by default, as done in: 24787afbcd01 ("perf tools: Enable LIBBABELTRACE by default") For now, to explicitely ask for opencsd, make sure you have it installed and use: make -C tools/perf CORESIGHT=1 The feature test output will be there as an empty file: $ ls -la /tmp/build/perf/feature/test-libopencsd.make.output Because the binary used for the feature check was successfully built: $ ls -la /tmp/build/perf/feature/test-libopencsd.bin -rwxrwxr-x. 1 acme acme 18336 Feb 12 14:49 /tmp/build/perf/feature/test-libopencsd.bin $ ldd /tmp/build/perf/feature/test-libopencsd.bin linux-vdso.so.1 (0x00007fffe18cc000) libopencsd_c_api.so.0 => /lib64/libopencsd_c_api.so.0 (0x00007fb8e67f6000) libopencsd.so.0 => /lib64/libopencsd.so.0 (0x00007fb8e676f000) libc.so.6 => /lib64/libc.so.6 (0x00007fb8e65a9000) libstdc++.so.6 => /lib64/libstdc++.so.6 (0x00007fb8e6411000) libm.so.6 => /lib64/libm.so.6 (0x00007fb8e628d000) libgcc_s.so.1 => /lib64/libgcc_s.so.1 (0x00007fb8e6272000) /lib64/ld-linux-x86-64.so.2 (0x00007fb8e6828000) $ And the resulting perf binary will be linked with it: -rw-rw-r--. 1 acme acme 0 Feb 12 14:49 /tmp/build/perf/feature/test-libopencsd.make.output $ ldd ~/bin/perf | grep opencsd libopencsd_c_api.so.0 => /lib64/libopencsd_c_api.so.0 (0x00007fd43097f000) libopencsd.so.0 => /lib64/libopencsd.so.0 (0x00007fd4308f8000) $ To make sure this gets built before pushing things upstream I have a ubuntu:19.04-x-arm64 container that has: [root@quaco x-arm64]# grep CORESIGHT Dockerfile ENV EXTRA_MAKE_ARGS=CORESIGHT=1 [root@quaco x-arm64]# So that I always build with libopencsd before pushing things upstream. Cc: Adrian Hunter <adrian.hunter(a)intel.com> Cc: Alexander Shishkin <alexander.shishkin(a)linux.intel.com> Cc: Jiri Olsa <jolsa(a)kernel.org> Cc: Kim Phillips <kim.phillips(a)arm.com> Cc: linux-arm-kernel(a)lists.infradead.org Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Mike Leach <mike.leach(a)arm.com> Cc: Namhyung Kim <namhyung(a)kernel.org> Cc: Peter Zijlstra <peterz(a)infradead.org> Cc: Suzuki Poulouse <suzuki.poulose(a)arm.com> Link: https://lkml.kernel.org/n/tip-20vyy39jw9jgrijesi30fgox@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo <acme(a)redhat.com> diff --git a/tools/build/Makefile.feature b/tools/build/Makefile.feature index 5467c6bf9ceb..bb9dca65eb5f 100644 --- a/tools/build/Makefile.feature +++ b/tools/build/Makefile.feature @@ -70,7 +70,6 @@ FEATURE_TESTS_BASIC := \ sched_getcpu \ sdt \ setns \ - libopencsd \ libaio # FEATURE_TESTS_BASIC + FEATURE_TESTS_EXTRA is the complete list @@ -84,6 +83,7 @@ FEATURE_TESTS_EXTRA := \ libbabeltrace \ libbfd-liberty \ libbfd-liberty-z \ + libopencsd \ libunwind-debug-frame \ libunwind-debug-frame-arm \ libunwind-debug-frame-aarch64 \ diff --git a/tools/build/feature/test-all.c b/tools/build/feature/test-all.c index 20cdaa4fc112..74329957553a 100644 --- a/tools/build/feature/test-all.c +++ b/tools/build/feature/test-all.c @@ -170,10 +170,6 @@ # include "test-setns.c" #undef main -#define main main_test_libopencsd -# include "test-libopencsd.c" -#undef main - #define main main_test_libaio # include "test-libaio.c" #undef main @@ -217,7 +213,6 @@ int main(int argc, char *argv[]) main_test_sched_getcpu(); main_test_sdt(); main_test_setns(); - main_test_libopencsd(); main_test_libaio(); return 0; diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index b441c88cafa1..e3bf29f942a8 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -386,7 +386,8 @@ ifeq ($(feature-setns), 1) $(call detected,CONFIG_SETNS) endif -ifndef NO_CORESIGHT +ifdef CORESIGHT + $(call feature_check,libopencsd) ifeq ($(feature-libopencsd), 1) CFLAGS += -DHAVE_CSTRACE_SUPPORT $(LIBOPENCSD_CFLAGS) LDFLAGS += $(LIBOPENCSD_LDFLAGS) diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 09df1c8a4ec9..c2ccc54618d1 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -102,7 +102,7 @@ include ../scripts/utilities.mak # When selected, pass LLVM_CONFIG=/path/to/llvm-config to `make' if # llvm-config is not in $PATH. # -# Define NO_CORESIGHT if you do not want support for CoreSight trace decoding. +# Define CORESIGHT if you DO WANT support for CoreSight trace decoding. # # Define NO_AIO if you do not want support of Posix AIO based trace # streaming for record mode. Currently Posix AIO trace streaming is

6 years, 12 months

[PATCH v5 0/3] Update AMBA driver for enhanced component ID spec.

by Mike Leach

The latest ARM CoreSight specification updates the component identification requirements for all components attached to an AMBA bus. (ARM IHI 0029E) This specification defines bits 15:12 in the ComponentID (CID) value as the device class. Identification requirements now depend on this class. Class 0xF: Traditional components identified by Peripheral ID (PID) only. Class 0x9: CoreSight components may be identified by a Universal Component Identifier (UCI) consisting of the PID plus CoreSight DevType and DevArch values. Current and future ARM CoreSight IP will now use the same PID for components on the same function - e.g. the ETM, CTI, PMU and Debug elements associated with a core. The first core to use this UCI method is the A35, which currently has binding entries in the ETMv4 driver. This patchset prepares for the addition of the upcoming CTI driver, which will need to correctly bind with A35, and reported new devices that share PID for multiple components, while overcoming the limitation of binding by PID alone, which cannot now work. Patch 0001: Adds new UCI data structure and uses it with existing drivers that use private data field in amba_id. This fixes issue from prior set. Patch 0002: Implements the UCI matching code in the AMBA core code. Patch 0003: Update ETMv4 driver to use UCI as appropriate. Thanks Mike Tested on DB410, Juno; kernel 5.0-rc6 Changes since v4: re-based on 5.0-rc6 Added reviewed/tested by tags. Changes since v3: Fix UCI structure to allow CoreSight drivers to set private data. This fixes bug where none-UCI private data would cause a driver binding mismatch. (e.g. STM). Add CS_AMBA macros to simplify building AMBA ID tables, with and without UCI settings. Changes since v2: Simplification of amba_cs_uci_id_match(). Fix CID class bitfield comments. Dropped RFC tag on patchset. Mike Leach (3): drivers: amba: Updates to component identification for driver matching. drivers: amba: Update component matching to use the CoreSight UCI values. coresight: etmv4: Update ID register table to add UCI support drivers/amba/bus.c | 45 +++++++++++++++---- drivers/hwtracing/coresight/coresight-etm3x.c | 44 ++++++------------ drivers/hwtracing/coresight/coresight-etm4x.c | 21 +++++---- drivers/hwtracing/coresight/coresight-priv.h | 40 +++++++++++++++++ drivers/hwtracing/coresight/coresight-stm.c | 14 ++---- drivers/hwtracing/coresight/coresight-tmc.c | 30 ++++--------- include/linux/amba/bus.h | 39 ++++++++++++++++ 7 files changed, 153 insertions(+), 80 deletions(-) -- 2.19.1

6 years, 12 months

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