CoreSight

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2448 discussions

Re: [PATCH 01/10] coresight: add support to enable more coresight paths

by Mathieu Poirier

On Thu, Oct 21, 2021 at 03:38:47PM +0800, Tao Zhang wrote: > Current coresight implementation only supports enabling source > ETMs or STM. This patch adds support to enable more kinds of > coresight source to sink paths. We build a path from source to > sink when any source is enabled and store it in a list. When the > source is disabled, we fetch the corresponding path from the list > and decrement the refcount on each device in the path. The device > is disabled if the refcount reaches zero. Don't store path to > coresight data structure of source to avoid unnecessary change to > ABI. > Since some targets may have coresight sources other than STM and > ETMs, we need to add this change to support these coresight > devices. > > Signed-off-by: Tingwei Zhang <tingwei(a)codeaurora.org> > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > --- > drivers/hwtracing/coresight/coresight-core.c | 100 +++++++++++-------- > 1 file changed, 56 insertions(+), 44 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c > index 8a18c71df37a..1e621d61307a 100644 > --- a/drivers/hwtracing/coresight/coresight-core.c > +++ b/drivers/hwtracing/coresight/coresight-core.c > @@ -37,18 +37,16 @@ struct coresight_node { > }; > > /* > - * When operating Coresight drivers from the sysFS interface, only a single > - * path can exist from a tracer (associated to a CPU) to a sink. > + * struct coresight_path - path from source to sink > + * @path: Address of path list. > + * @link: hook to the list. > */ > -static DEFINE_PER_CPU(struct list_head *, tracer_path); > +struct coresight_path { > + struct list_head *path; > + struct list_head link; > +}; For sources associated with a CPU, like ETMs, having a per-cpu way of storing paths is a definite advantage and should be kept that way. > > -/* > - * As of this writing only a single STM can be found in CS topologies. Since > - * there is no way to know if we'll ever see more and what kind of > - * configuration they will enact, for the time being only define a single path > - * for STM. > - */ > -static struct list_head *stm_path; > +static LIST_HEAD(cs_active_paths); Then there are sources that aren't associated with a CPU like STMs and TPDMs. Perhaps using an IDR or the hash of the device name as a key to a hashing vector would be better than doing a sequential search, especially as the list of devices is bound to increase over time. > > /* > * When losing synchronisation a new barrier packet needs to be inserted at the > @@ -354,6 +352,7 @@ static void coresight_disable_sink(struct coresight_device *csdev) > if (ret) > return; > coresight_control_assoc_ectdev(csdev, false); > + csdev->activated = false; I don't see why this is needed and without proper documentation there is no way for me to guess the logic behind the change. The ->activated flag should be manipulated from the command line interface only. > csdev->enable = false; > } > > @@ -590,6 +589,20 @@ int coresight_enable_path(struct list_head *path, u32 mode, void *sink_data) > goto out; > } > > +static struct coresight_device *coresight_get_source(struct list_head *path) > +{ > + struct coresight_device *csdev; > + > + if (!path) > + return NULL; > + > + csdev = list_first_entry(path, struct coresight_node, link)->csdev; > + if (csdev->type != CORESIGHT_DEV_TYPE_SOURCE) > + return NULL; > + > + return csdev; > +} > + > struct coresight_device *coresight_get_sink(struct list_head *path) > { > struct coresight_device *csdev; > @@ -1086,9 +1099,23 @@ static int coresight_validate_source(struct coresight_device *csdev, > return 0; > } > > +static int coresight_store_path(struct list_head *path) > +{ > + struct coresight_path *node; > + > + node = kzalloc(sizeof(struct coresight_path), GFP_KERNEL); > + if (!node) > + return -ENOMEM; > + > + node->path = path; > + list_add(&node->link, &cs_active_paths); > + > + return 0; > +} > + > int coresight_enable(struct coresight_device *csdev) > { > - int cpu, ret = 0; > + int ret = 0; > struct coresight_device *sink; > struct list_head *path; > enum coresight_dev_subtype_source subtype; > @@ -1133,25 +1160,9 @@ int coresight_enable(struct coresight_device *csdev) > if (ret) > goto err_source; > > - switch (subtype) { > - case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: > - /* > - * When working from sysFS it is important to keep track > - * of the paths that were created so that they can be > - * undone in 'coresight_disable()'. Since there can only > - * be a single session per tracer (when working from sysFS) > - * a per-cpu variable will do just fine. > - */ > - cpu = source_ops(csdev)->cpu_id(csdev); > - per_cpu(tracer_path, cpu) = path; > - break; > - case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: > - stm_path = path; > - break; > - default: > - /* We can't be here */ > - break; > - } > + ret = coresight_store_path(path); > + if (ret) > + goto err_source; > > out: > mutex_unlock(&coresight_mutex); > @@ -1168,8 +1179,11 @@ EXPORT_SYMBOL_GPL(coresight_enable); > > void coresight_disable(struct coresight_device *csdev) > { > - int cpu, ret; > + int ret; > struct list_head *path = NULL; > + struct coresight_path *cspath = NULL; > + struct coresight_path *cspath_next = NULL; > + struct coresight_device *src_csdev = NULL; > > mutex_lock(&coresight_mutex); > > @@ -1180,20 +1194,18 @@ void coresight_disable(struct coresight_device *csdev) > if (!csdev->enable || !coresight_disable_source(csdev)) > goto out; > > - switch (csdev->subtype.source_subtype) { > - case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: > - cpu = source_ops(csdev)->cpu_id(csdev); > - path = per_cpu(tracer_path, cpu); > - per_cpu(tracer_path, cpu) = NULL; > - break; > - case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE: > - path = stm_path; > - stm_path = NULL; > - break; > - default: > - /* We can't be here */ > - break; > + list_for_each_entry_safe(cspath, cspath_next, &cs_active_paths, link) { > + src_csdev = coresight_get_source(cspath->path); > + if (!src_csdev) > + continue; > + if (src_csdev == csdev) { > + path = cspath->path; > + list_del(&cspath->link); > + kfree(cspath); See my comment above - I agree that sources _not_ associated with a CPU should be handled differently. CPU bound sources should be kept untouched. That is all the time I had for today, I will continue tomorrow. Thanks, Mathieu > + } > } > + if (path == NULL) > + goto out; > > coresight_disable_path(path); > coresight_release_path(path); > -- > 2.17.1 >

3 years, 10 months

Re: [PATCH 00/10] Add support for TPDM and TPDA

by Mathieu Poirier

I have started to review this set. It is substantial in size and as such will take me several days, most likely weeks. Did you run checkpatch before sending this set out? If so, any reason why there are still errors? Thanks, Mathieu On Thu, Oct 21, 2021 at 03:38:46PM +0800, Tao Zhang wrote: > This series adds support for the trace performance monitoring and > diagnostics hardware (TPDM and TPDA). It is composed of two major > elements. > a) Changes for original coresight framework to support for TPDM and TPDA. > b) Add driver code for TPDM and TPDA. > > Introduction of changes for original coresight framework > a) Support TPDM as new coresight source. > Since only STM and ETM are supported as coresight source originally. > TPDM is a newly added coresight source. We need to change > the original way of saving coresight path to support more types source > for coresight driver. > The following patch is to add support more coresight sources. > coresight: add support to enable more coresight paths > > b) To support multi-port input and multi-port output for funnels > In some cases, different TPDM hardware will be connected to the same > funnel, but eventually they need to be linked to different TPDAs or > funnels. This requires funnel to support multi-port input and multi-port > output, and can specify which input port corresponds to which output port. > Use property ?label? in the funnel?s configuration to point out from > which input port to which output port. > The following patch is to support multi-port input and multi-port output > for funnels. > coresight: funnel: add support for multiple output ports > > Introduction of TPDM and TPDA > TPDM - The trace performance monitoring and diagnostics monitor or TPDM in > short serves as data collection component for various dataset types > specified in the QPMDA(Qualcomm performance monitoring and diagnostics > architecture) spec. The primary use case of the TPDM is to collect data > from different data sources and send it to a TPDA for packetization, > timestamping and funneling. > The following patch is to add driver for TPDM. > Coresight: Add driver to support Coresight device TPDM > Coresight: Enable BC and GPR for TPDM driver > Coresight: Add interface for TPDM BC subunit > Coresight: Enable and add interface for TPDM TC subunit > Coresight: Enable DSB subunit for TPDM > Coresight: Enable CMB subunit for TPDM > > TPDA - The trace performance monitoring and diagnostics aggregator or > TPDA in short serves as an arbitration and packetization engine for the > performance monitoring and diagnostics network as specified in the QPMDA > (Qualcomm performance monitoring and diagnostics architecture) > specification. The primary use case of the TPDA is to provide > packetization, funneling and timestamping of Monitor data as specified > in the QPMDA specification. > The following patch is to add driver for TPDA. > coresight: Add driver to support Coresight device TPDA > > The last patch of this series is a device tree modification, which add > the TPDM and TPDA configuration to device tree for validating. > ARM: dts: msm: Add TPDA and TPDM configuration to device > > Once this series patches are applied properly, the tpdm and tpda nodes > should be observed at the coresight path /sys/bus/coresight/devices > e.g. > /sys/bus/coresight/devices # ls -l | grep tpd > tpda0 -> ../../../devices/platform/soc(a)0/6004000.tpda/tpda0 > tpdm0 -> ../../../devices/platform/soc(a)0/6844000.lpass.tpdm/tpdm0 > > We can use the commands are similar to the below to validate TPDMs. > Enable coresight sink first. > echo 1 > /sys/bus/coresight/devices/tpdm0/enable_source > echo 1 > /sys/bus/coresight/devices/tpdm0/integration_test > echo 2 > /sys/bus/coresight/devices/tpdm0/integration_test > The test data will be collected in the coresight sink which is enabled. > > This series applies to coresight/next > https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git?h=next > > Tao Zhang (10): > coresight: add support to enable more coresight paths > coresight: funnel: add support for multiple output ports > Coresight: Add driver to support Coresight device TPDM > Coresight: Enable BC and GPR for TPDM driver > Coresight: Add interface for TPDM BC subunit > Coresight: Enable and add interface for TPDM TC subunit > Coresight: Enable DSB subunit for TPDM > Coresight: Enable CMB subunit for TPDM > coresight: Add driver to support Coresight device TPDA > ARM: dts: msm: Add TPDA and TPDM support to DTS for RB5 > > .../bindings/arm/coresight-tpda.yaml | 169 + > .../bindings/arm/coresight-tpdm.yaml | 86 + > MAINTAINERS | 6 + > arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 439 ++ > drivers/hwtracing/coresight/Kconfig | 18 + > drivers/hwtracing/coresight/Makefile | 2 + > drivers/hwtracing/coresight/coresight-core.c | 175 +- > .../hwtracing/coresight/coresight-platform.c | 8 + > drivers/hwtracing/coresight/coresight-tpda.c | 828 ++++ > drivers/hwtracing/coresight/coresight-tpdm.c | 4253 +++++++++++++++++ > include/linux/coresight.h | 2 + > 11 files changed, 5928 insertions(+), 58 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml > create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml > create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c > create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c > > -- > 2.17.1 >

3 years, 10 months

Re: [PATCH] coresight: Use devm_bitmap_zalloc when applicable

by Mathieu Poirier

Good day, On Sat, Oct 23, 2021 at 10:09:14PM +0200, Christophe JAILLET wrote: > Le 23/10/2021 à 21:36, Joe Perches a écrit : > > On Sat, 2021-10-23 at 21:24 +0200, Christophe JAILLET wrote: > > > 'drvdata->chs.guaranteed' is a bitmap. So use 'devm_bitmap_kzalloc()' to > > > simplify code, improve the semantic and avoid some open-coded arithmetic > > > in allocator arguments. > > [] > > > diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c > > [] > > > @@ -862,7 +862,6 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) > > > struct stm_drvdata *drvdata; > > > struct resource *res = &adev->res; > > > struct resource ch_res; > > > - size_t bitmap_size; > > > struct coresight_desc desc = { 0 }; > > > desc.name = coresight_alloc_device_name(&stm_devs, dev); > > > @@ -904,9 +903,7 @@ static int stm_probe(struct amba_device *adev, const struct amba_id *id) > > > else > > > drvdata->numsp = stm_num_stimulus_port(drvdata); > > > - bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long); > > > - > > > - guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL); > > > + guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp, GFP_KERNEL); > > > if (!guaranteed) > > > return -ENOMEM; > > > drvdata->chs.guaranteed = guaranteed; > > > > guaranteed is also pretty useless > > > > I agree, but removing it would make the line with devm_bitmap_zalloc() 86 > chars. This would not be consistent with the rest of the file and would > (IMHO) require splitting. > > Let see if the maintainer prefer saving one additional line of code, or > keeping the logic in place. I think we can get rid of @guaranteed and splitting is fine with me: drvdata->chs.guaranteed = devm_bitmap_zalloc(dev, drvdata->numsp, GFP_KERNEL); Thanks, Mathieu > > CJ >

3 years, 10 months

[GIT PULL v3] Coresight changes for v5.16

by Mathieu Poirier

The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16.v3 for you to fetch changes up to 561ced0bb90a4be298b7db5fb54f29731d74a3f6: arm64: errata: Enable TRBE workaround for write to out-of-range address (2021-10-27 11:46:06 -0600) ---------------------------------------------------------------- Coresight changes for v5.16 - A new option to make coresight cpu-debug capabilities available as early as possible in the kernel boot process. - Make trace sessions more enduring by coping with scenarios where events are scheduled on CPUs that can't reach the selected sink. - A set of improvement to make the TMC-ETR driver more efficient. - Enhancements to the TRBE driver to correct several errata. - An enhancement to make the AXI burts size configurable for TMC devices that can't work with the default value. - A fix in the CTI module to use the correct device when calling pm_runtime_put() - The addition of the Kryo-5xx device to the list of support ETMs. Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> ---------------------------------------------------------------- Brian Norris (1): coresight: cpu-debug: Control default behavior via Kconfig James Clark (1): coresight: Don't immediately close events that are run on invalid CPU/sink combos Leo Yan (5): coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer coresight: Update comments for removing cs_etm_find_snapshot() coresight: tmc-etr: Speed up for bounce buffer in flat mode Suzuki K Poulose (28): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: etm4x: Save restore TRFCR_EL1 coresight: etm4x: Use Trace Filtering controls dynamically coresight: etm-pmu: Ensure the AUX handle is valid coresight: trbe: Ensure the format flag is always set coresight: trbe: Drop duplicate TRUNCATE flags coresight: trbe: Unify the enabling sequence coresight: trbe: irq handler: Do not disable TRBE if no action is needed coresight: trbe: Fix handling of spurious interrupts coresight: trbe: Do not truncate buffer on IRQ coresight: trbe: End the AUX handle on truncation coresight: trbe: Prohibit trace before disabling TRBE coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Defer the probe on offline CPUs coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Tanmay Jagdale (2): dt-bindings: coresight: Add burst size for TMC coresight: tmc: Configure AXI write burst size Tao Zhang (2): coresight: cti: Correct the parameter for pm_runtime_put coresight: etm4x: Add ETM PID for Kryo-5XX Documentation/arm64/silicon-errata.rst | 12 + .../devicetree/bindings/arm/coresight.txt | 5 + arch/arm64/Kconfig | 111 +++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/Kconfig | 13 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 2 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 5 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 56 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 101 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +- .../coresight/coresight-self-hosted-trace.h | 33 ++ drivers/hwtracing/coresight/coresight-tmc-core.c | 21 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 +- drivers/hwtracing/coresight/coresight-tmc.h | 6 +- drivers/hwtracing/coresight/coresight-trbe.c | 534 +++++++++++++++++---- 20 files changed, 905 insertions(+), 154 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h

3 years, 10 months

Re: [GIT PULL v2] Coresight changes for v5.16

by Mathieu Poirier

On Wed, 27 Oct 2021 at 11:41, Greg KH <gregkh(a)linuxfoundation.org> wrote: > > On Wed, Oct 27, 2021 at 11:32:43AM -0600, Mathieu Poirier wrote: > > On Wed, 27 Oct 2021 at 00:50, Greg KH <gregkh(a)linuxfoundation.org> wrote: > > > > > > On Tue, Oct 26, 2021 at 01:55:45PM -0600, Mathieu Poirier wrote: > > > > The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: > > > > > > > > Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) > > > > > > > > are available in the Git repository at: > > > > > > > > git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16 > > > > > > Better but I get the following errors when my scripts try to merge them. > > > Note, the linux-next scripts will give you the same complaint, so this > > > isn't a new thing: > > > > Can you point me to the linux-next script you are referring to above? > > Usually when that happens I get an email but this time I didn't get > > anything. > > Is this tree/branch in linux-next now? If so, you should have gotten an > email. Definitely: https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git/log/?h=… > > My scripts were sent to the workflow mailing list a year or so ago, I > can dig them up if needed. > Thanks - I'll look it up.

3 years, 10 months

Re: [GIT PULL v2] Coresight changes for v5.16

by Mathieu Poirier

On Wed, 27 Oct 2021 at 00:50, Greg KH <gregkh(a)linuxfoundation.org> wrote: > > On Tue, Oct 26, 2021 at 01:55:45PM -0600, Mathieu Poirier wrote: > > The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: > > > > Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) > > > > are available in the Git repository at: > > > > git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16 > > Better but I get the following errors when my scripts try to merge them. > Note, the linux-next scripts will give you the same complaint, so this > isn't a new thing: Can you point me to the linux-next script you are referring to above? Usually when that happens I get an email but this time I didn't get anything. > > Commit 6871138a7ab9 ("coresight: etm4x: Add ETM PID for Kryo-5XX") > committer Signed-off-by missing > author email: quic_taozha(a)quicinc.com > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Tao Zhang <quic_taozha(a)quicinc.com> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit 202d403ae3a9 ("coresight: Don't immediately close events that are run on invalid CPU/sink combos") > committer Signed-off-by missing > author email: james.clark(a)arm.com > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: James Clark <james.clark(a)arm.com> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit ef095e61dc8f ("coresight: Update comments for removing cs_etm_find_snapshot()") > committer Signed-off-by missing > author email: leo.yan(a)linaro.org > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit 7be15eef996f ("coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer") > committer Signed-off-by missing > author email: leo.yan(a)linaro.org > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit 60067d5ab339 ("coresight: tmc-etf: Add comment for store ordering") > committer Signed-off-by missing > author email: leo.yan(a)linaro.org > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Commit 7c202525ff8c ("coresight: tmc-etr: Add barrier after updating AUX ring buffer") > committer Signed-off-by missing > author email: leo.yan(a)linaro.org > committer email: mathieu.poirier(a)linaro.org > Signed-off-by: Leo Yan <leo.yan(a)linaro.org> > Signed-off-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > > Errors in tree with Signed-off-by, please fix! > > > Is there some reason you are committing changes to your tree and not signing > off on them? That's not really a good idea :( > Not sure why sarcasm is required here - simply pointing out the problem would have been sufficient. These patches were committed by Suzuki who co-maintains the subsystem with me. The committer information likely got transferred when I cherry-picked the patches when putting the pull request together. > thanks, > > greg k-h

3 years, 10 months

[GIT PULL v2] Coresight changes for v5.16

by Mathieu Poirier

The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/coresight-next-v5.16 for you to fetch changes up to 7cf0754113f7ed6fad999483e40d95985c987353: arm64: errata: Enable TRBE workaround for write to out-of-range address (2021-10-25 12:06:02 -0600) ---------------------------------------------------------------- Coresight changes for v5.16 - A new option to make coresight cpu-debug capabilities available as early as possible in the kernel boot process. - Make trace sessions more enduring by coping with scenarios where events are scheduled on CPUs that can't reach the selected sink. - A set of improvement to make the TMC-ETR driver more efficient. - Enhancements to the TRBE driver to correct several errata. - An enhancement to make the AXI burts size configurable for TMC devices that can't work with the default value. - A fix in the CTI module to use the correct device when calling pm_runtime_put() - The addition of the Kryo-5xx device to the list of support ETMs. Signed-off-by: Mathieu Poirier <mathieu.poirier(a)linaro.org> ---------------------------------------------------------------- Brian Norris (1): coresight: cpu-debug: Control default behavior via Kconfig James Clark (1): coresight: Don't immediately close events that are run on invalid CPU/sink combos Leo Yan (5): coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer coresight: Update comments for removing cs_etm_find_snapshot() coresight: tmc-etr: Speed up for bounce buffer in flat mode Suzuki K Poulose (28): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: etm4x: Save restore TRFCR_EL1 coresight: etm4x: Use Trace Filtering controls dynamically coresight: etm-pmu: Ensure the AUX handle is valid coresight: trbe: Ensure the format flag is always set coresight: trbe: Drop duplicate TRUNCATE flags coresight: trbe: Unify the enabling sequence coresight: trbe: irq handler: Do not disable TRBE if no action is needed coresight: trbe: Fix handling of spurious interrupts coresight: trbe: Do not truncate buffer on IRQ coresight: trbe: End the AUX handle on truncation coresight: trbe: Prohibit trace before disabling TRBE coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Defer the probe on offline CPUs coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Tanmay Jagdale (2): dt-bindings: coresight: Add burst size for TMC coresight: tmc: Configure AXI write burst size Tao Zhang (2): coresight: cti: Correct the parameter for pm_runtime_put coresight: etm4x: Add ETM PID for Kryo-5XX Documentation/arm64/silicon-errata.rst | 12 + .../devicetree/bindings/arm/coresight.txt | 5 + arch/arm64/Kconfig | 111 +++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/Kconfig | 13 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 2 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 5 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 56 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 101 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +- .../coresight/coresight-self-hosted-trace.h | 33 ++ drivers/hwtracing/coresight/coresight-tmc-core.c | 21 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 +- drivers/hwtracing/coresight/coresight-tmc.h | 6 +- drivers/hwtracing/coresight/coresight-trbe.c | 534 +++++++++++++++++---- 20 files changed, 905 insertions(+), 154 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h

3 years, 10 months

[GIT PULL] Coresight subsystem for v5.16

by Mathieu Poirier

The following changes since commit 5816b3e6577eaa676ceb00a848f0fd65fe2adc29: Linux 5.15-rc3 (2021-09-26 14:08:19 -0700) are available in the Git repository at: git@gitolite.kernel.org:pub/scm/linux/kernel/git/coresight/linux.git tags/v5.16-next for you to fetch changes up to 7cf0754113f7ed6fad999483e40d95985c987353: arm64: errata: Enable TRBE workaround for write to out-of-range address (2021-10-25 12:06:02 -0600) ---------------------------------------------------------------- Hi Greg, Please consider these for the next merge window. Also let me know if there is any modifications I can do to this pull request to make things easier on your side. Thanks, Mathieu Included herein: - A new option to make coresight cpu-debug capabilities available as early as possible in the kernel boot process. - Make trace sessions more enduring by coping with scenarios where events are scheduled on CPUs that can't reach the selected sink. - A set of improvement to make the TMC-ETR driver more efficient. - Enhancements to the TRBE driver to correct several errata. - An enhancement to make the AXI burts size configurable for TMC devices that can't work with the default value. - A fix in the CTI module to use the correct device when calling pm_runtime_put() - The addition of the Kryo-5xx device to the list of support ETMs. ---------------------------------------------------------------- Brian Norris (1): coresight: cpu-debug: Control default behavior via Kconfig James Clark (1): coresight: Don't immediately close events that are run on invalid CPU/sink combos Leo Yan (5): coresight: tmc-etr: Add barrier after updating AUX ring buffer coresight: tmc-etf: Add comment for store ordering coresight: tmc-etr: Use perf_output_handle::head for AUX ring buffer coresight: Update comments for removing cs_etm_find_snapshot() coresight: tmc-etr: Speed up for bounce buffer in flat mode Suzuki K Poulose (28): arm64: Add Neoverse-N2, Cortex-A710 CPU part definition arm64: errata: Add detection for TRBE overwrite in FILL mode arm64: errata: Add workaround for TSB flush failures arm64: errata: Add detection for TRBE write to out-of-range coresight: etm4x: Save restore TRFCR_EL1 coresight: etm4x: Use Trace Filtering controls dynamically coresight: etm-pmu: Ensure the AUX handle is valid coresight: trbe: Ensure the format flag is always set coresight: trbe: Drop duplicate TRUNCATE flags coresight: trbe: Unify the enabling sequence coresight: trbe: irq handler: Do not disable TRBE if no action is needed coresight: trbe: Fix handling of spurious interrupts coresight: trbe: Do not truncate buffer on IRQ coresight: trbe: End the AUX handle on truncation coresight: trbe: Prohibit trace before disabling TRBE coresight: trbe: Fix incorrect access of the sink specific data coresight: trbe: Defer the probe on offline CPUs coresight: trbe: Add a helper to calculate the trace generated coresight: trbe: Add a helper to pad a given buffer area coresight: trbe: Decouple buffer base from the hardware base coresight: trbe: Allow driver to choose a different alignment coresight: trbe: Add infrastructure for Errata handling coresight: trbe: Workaround TRBE errata overwrite in FILL mode coresight: trbe: Add a helper to determine the minimum buffer size coresight: trbe: Make sure we have enough space coresight: trbe: Work around write to out of range arm64: errata: Enable workaround for TRBE overwrite in FILL mode arm64: errata: Enable TRBE workaround for write to out-of-range address Tanmay Jagdale (2): dt-bindings: coresight: Add burst size for TMC coresight: tmc: Configure AXI write burst size Tao Zhang (2): coresight: cti: Correct the parameter for pm_runtime_put coresight: etm4x: Add ETM PID for Kryo-5XX Documentation/arm64/silicon-errata.rst | 12 + .../devicetree/bindings/arm/coresight.txt | 5 + arch/arm64/Kconfig | 111 +++++ arch/arm64/include/asm/barrier.h | 16 +- arch/arm64/include/asm/cputype.h | 4 + arch/arm64/kernel/cpu_errata.c | 64 +++ arch/arm64/tools/cpucaps | 3 + drivers/hwtracing/coresight/Kconfig | 13 + drivers/hwtracing/coresight/coresight-cpu-debug.c | 2 +- drivers/hwtracing/coresight/coresight-cti-core.c | 2 +- drivers/hwtracing/coresight/coresight-etb10.c | 5 +- drivers/hwtracing/coresight/coresight-etm-perf.c | 56 ++- drivers/hwtracing/coresight/coresight-etm4x-core.c | 101 +++- drivers/hwtracing/coresight/coresight-etm4x.h | 9 +- .../coresight/coresight-self-hosted-trace.h | 33 ++ drivers/hwtracing/coresight/coresight-tmc-core.c | 21 +- drivers/hwtracing/coresight/coresight-tmc-etf.c | 10 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 52 +- drivers/hwtracing/coresight/coresight-tmc.h | 6 +- drivers/hwtracing/coresight/coresight-trbe.c | 534 +++++++++++++++++---- 20 files changed, 905 insertions(+), 154 deletions(-) create mode 100644 drivers/hwtracing/coresight/coresight-self-hosted-trace.h

3 years, 10 months

Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Mathieu Poirier

On Fri, Oct 22, 2021 at 09:14:38AM +0200, Greg KH wrote: > On Thu, Oct 21, 2021 at 05:47:31PM +0100, Will Deacon wrote: > > Hi Mathieu, > > > > [CC Greg] > > > > On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: > > > On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > > > > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > > > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > > > > Suzuki K Poulose (15): > > > > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > > > > arm64: errata: Add workaround for TSB flush failures > > > > > > arm64: errata: Add detection for TRBE write to out-of-range > > > > > > coresight: trbe: Add a helper to calculate the trace generated > > > > > > coresight: trbe: Add a helper to pad a given buffer area > > > > > > coresight: trbe: Decouple buffer base from the hardware base > > > > > > coresight: trbe: Allow driver to choose a different alignment > > > > > > coresight: trbe: Add infrastructure for Errata handling > > > > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > > > > coresight: trbe: Make sure we have enough space > > > > > > coresight: trbe: Work around write to out of range > > > > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > > > > address > > > > > > > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > > > > arch/arm64/Kconfig | 111 ++++++ > > > > > > arch/arm64/include/asm/barrier.h | 16 +- > > > > > > arch/arm64/include/asm/cputype.h | 4 + > > > > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > > > > arch/arm64/tools/cpucaps | 3 + > > > > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > > > > > > > I have applied this set. > > > > > > > > Mathieu -- the plan here (which we have discussed on the list [1]) is > > > > for the first four patches to be shared with arm64. Since you've gone > > > > ahead and applied the whole series, please can you provide me a stable > > > > branch with the first four patches only so that I can include them in > > > > the arm64 tree? > > > > > > > > Failing that, I can create a branch for you to pull and apply the remaining > > > > patches on top. > > > > > > > > Please let me know. > > > > > > Coresight patches flow through Greg's tree and as such the coresight-next tree > > > gets rebased anyway. I will remove the first 4 patches and push again. By the > > > way do you also want to pick up patches 14 and 16 since they are concerned with > > > "arch/arm64/Kconfig" or should I keep them? > > > > I'll take the first 4 and put them on a stable branch, which you can choose > > to pull if you like (but please don't rebase it or we'll end up with > > duplicate commits). The rest of the patches, including the later Kconfig > > changes, are yours but I doubt they'll apply cleanly without the initial > > changes. > > > > Are you sure Greg rebases everything? That sounds a bit weird to me, as it > > means it's impossible to share branches with other trees. How do you usually > > handle this situation? > > No, I never rebase my trees. For coresight patches I take them as > emailed patches due to previous history requiring me to review them all > myself. If this is an issue here, I can always take a pull request as > long as you all don't want my review :) Can you expand on the "previous history requiring" you to review coresight patches? Rebasing the coresight-next tree when patches are pulled in the char-misc tree causes problems when features involve other subsystems. I definitely appreciate reviews of coresight patches from anyone. The subsystem has grown to be very complex and more reviewers mean higher probabilities of catching problems. There has to be a way for that to continue while making it easier to collaborate with other subsystems. For this particular patchset, Will has picked up the first 4 patches, I will pick up patches 5 to 13 and patches 14 and 15 will have to go in the next cycle. I doubt this is the best we can do. Regards, Mathieu > > thanks, > > greg k-h

3 years, 10 months

Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds

by Mathieu Poirier

On Thu, 21 Oct 2021 at 10:47, Will Deacon <will(a)kernel.org> wrote: > > Hi Mathieu, > > [CC Greg] > > On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: > > On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: > > > On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: > > > > On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: > > > > > Suzuki K Poulose (15): > > > > > arm64: Add Neoverse-N2, Cortex-A710 CPU part definition > > > > > arm64: errata: Add detection for TRBE overwrite in FILL mode > > > > > arm64: errata: Add workaround for TSB flush failures > > > > > arm64: errata: Add detection for TRBE write to out-of-range > > > > > coresight: trbe: Add a helper to calculate the trace generated > > > > > coresight: trbe: Add a helper to pad a given buffer area > > > > > coresight: trbe: Decouple buffer base from the hardware base > > > > > coresight: trbe: Allow driver to choose a different alignment > > > > > coresight: trbe: Add infrastructure for Errata handling > > > > > coresight: trbe: Workaround TRBE errata overwrite in FILL mode > > > > > coresight: trbe: Add a helper to determine the minimum buffer size > > > > > coresight: trbe: Make sure we have enough space > > > > > coresight: trbe: Work around write to out of range > > > > > arm64: errata: Enable workaround for TRBE overwrite in FILL mode > > > > > arm64: errata: Enable TRBE workaround for write to out-of-range > > > > > address > > > > > > > > > > Documentation/arm64/silicon-errata.rst | 12 + > > > > > arch/arm64/Kconfig | 111 ++++++ > > > > > arch/arm64/include/asm/barrier.h | 16 +- > > > > > arch/arm64/include/asm/cputype.h | 4 + > > > > > arch/arm64/kernel/cpu_errata.c | 64 +++ > > > > > arch/arm64/tools/cpucaps | 3 + > > > > > drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- > > > > > 7 files changed, 567 insertions(+), 37 deletions(-) > > > > > > > > I have applied this set. > > > > > > Mathieu -- the plan here (which we have discussed on the list [1]) is > > > for the first four patches to be shared with arm64. Since you've gone > > > ahead and applied the whole series, please can you provide me a stable > > > branch with the first four patches only so that I can include them in > > > the arm64 tree? > > > > > > Failing that, I can create a branch for you to pull and apply the remaining > > > patches on top. > > > > > > Please let me know. > > > > Coresight patches flow through Greg's tree and as such the coresight-next tree > > gets rebased anyway. I will remove the first 4 patches and push again. By the > > way do you also want to pick up patches 14 and 16 since they are concerned with > > "arch/arm64/Kconfig" or should I keep them? > > I'll take the first 4 and put them on a stable branch, which you can choose > to pull if you like (but please don't rebase it or we'll end up with > duplicate commits). The rest of the patches, including the later Kconfig > changes, are yours but I doubt they'll apply cleanly without the initial > changes. Right - I just had another look at them and what I suggested above won't work. > > Are you sure Greg rebases everything? That sounds a bit weird to me, as it > means it's impossible to share branches with other trees. How do you usually > handle this situation? Greg applies the patches I send to him near the end of every cycle - see this one [1] as an example. Unfortunately that way of working makes it hard to deal with patchsets such as this one. To move forward you can either pick up this whole series (just add my RB to all the CS patches) or I start sending pull requests to Greg. Greg - what's your take on this? [1]. https://www.spinics.net/lists/arm-kernel/msg915961.html > > Will

3 years, 10 months

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