CoreSight

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2446 discussions

Re: [PATCH v4 02/48] perf stat: Add aggr creators that are passed a cpu.

by Arnaldo Carvalho de Melo

Em Mon, Jan 10, 2022 at 09:36:49AM -0800, Ian Rogers escreveu: > On Mon, Jan 10, 2022 at 9:10 AM John Garry <john.garry(a)huawei.com> wrote: > > > > On 05/01/2022 06:13, Ian Rogers wrote: > > > > > > +struct aggr_cpu_id cpu_map__get_socket(struct perf_cpu_map *map, int idx, > > > + void *data) > > > +{ > > > + if (idx < 0 || idx > map->nr) > > > + return cpu_map__empty_aggr_cpu_id(); > > > + > > > + return cpu_map__get_socket_aggr_by_cpu(map->map[idx], data); > > > +} > > > + > > > > > > This is later deleted in the series. Can the series be reworked so that > > we don't add stuff and then later delete it? One reason for that > > approach is that we don't spend time reviewing something which will be > > deleted, especially in such a big series... > > Hi John, > > I think you are asking to squash: > https://lore.kernel.org/lkml/20220105061351.120843-8-irogers@google.com/ > into this change. There are other similar related changes that may > also be squashed. The changes are trying to introduce a new API and > then add changes to switch over to using it. This is with a view to > making bisection easier, have each change only do 1 thing and so on. I > believe the format of the patches is house style, but it is fine to > squash changes together too. Having sent patches to Arnaldo and having > had them split I'm reluctant to do a v5 with them squashed without him > expressing a preference. Right, sometimes this is needed, I'm getting the patchkit now to test build it in my containers and will go patch by patch reviewing. - Arnaldo > Thanks, > Ian > > > If it really makes sense to do it this way then fine. > > > > Thanks, > > John -- - Arnaldo

3 years, 7 months

Re: [PATCH V2 7/7] coresight: trbe: Work around the trace data corruption

by Suzuki K Poulose

On 07/01/2022 01:10, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #1902691 might corrupt trace > data or deadlock, when it's being written into the memory. Workaround this > problem in the driver, by preventing TRBE initialization on affected cpus. > The firmware must have disabled the access to TRBE for the kernel on such > implementations. This will cover the kernel for any firmware that doesn't > do this already. This just updates the TRBE driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > arch/arm64/Kconfig | 2 +- > drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 209e481acf0d..8a2245c3e857 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -821,7 +821,7 @@ config ARM64_ERRATUM_2038923 > > config ARM64_ERRATUM_1902691 > bool "Cortex-A510: 1902691: workaround TRBE trace corruption" > - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in > + depends on CORESIGHT_TRBE > default y > help > This option adds the workaround for ARM Cortex-A510 erratum 1902691. > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index c4cc529749f8..d2f1c68e589c 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -93,12 +93,14 @@ struct trbe_buf { > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > #define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 > #define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE 3 > +#define TRBE_IS_BROKEN 4 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > [TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142, > [TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] = ARM64_WORKAROUND_2038923, > + [TRBE_IS_BROKEN] = ARM64_WORKAROUND_1902691, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -181,6 +183,11 @@ static inline bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *cpudat > return trbe_has_erratum(cpudata, TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE); > } > > +static inline bool trbe_is_broken(struct trbe_cpudata *cpudata) > +{ > + return trbe_has_erratum(cpudata, TRBE_IS_BROKEN); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -1288,6 +1295,11 @@ static void arm_trbe_probe_cpu(void *info) > */ > trbe_check_errata(cpudata); > > + if (trbe_is_broken(cpudata)) { > + pr_err("Disabling TRBE on cpu%d due to erratum\n", cpu); > + goto cpu_clear; > + } > + > /* > * If the TRBE is affected by erratum TRBE_WORKAROUND_OVERWRITE_FILL_MODE, > * we must always program the TBRPTR_EL1, 256bytes from a page Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 years, 7 months

Re: [PATCH V2 6/7] coresight: trbe: Work around the invalid prohibited states

by Suzuki K Poulose

On 07/01/2022 01:10, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2038923 might get TRBE into > an inconsistent view on whether trace is prohibited within the CPU. As a > result, the trace buffer or trace buffer state might be corrupted. This > happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, > followed by just a single context synchronization event before execution > changes from a context, in which trace is prohibited to one where it isn't, > or vice versa. In these mentioned conditions, the view of whether trace is > prohibited is inconsistent between parts of the CPU, and the trace buffer > or the trace buffer state might be corrupted. > > Work around this problem in the TRBE driver by preventing an inconsistent > view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by > immediately following a change to TRBLIMITR_EL1.E with at least one ISB > instruction before an ERET, or two ISB instructions if no ERET is to take > place. This just updates the TRBE driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > arch/arm64/Kconfig | 2 +- > drivers/hwtracing/coresight/coresight-trbe.c | 48 +++++++++++++++----- > 2 files changed, 37 insertions(+), 13 deletions(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index b6d62672bf7d..209e481acf0d 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -798,7 +798,7 @@ config ARM64_ERRATUM_2064142 > > config ARM64_ERRATUM_2038923 > bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" > - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in > + depends on CORESIGHT_TRBE > default y > help > This option adds the workaround for ARM Cortex-A510 erratum 2038923. > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 850e9fca6847..c4cc529749f8 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -92,11 +92,13 @@ struct trbe_buf { > #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > #define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 > +#define TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE 3 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > [TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142, > + [TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE] = ARM64_WORKAROUND_2038923, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -174,6 +176,11 @@ static inline bool trbe_needs_drain_after_disable(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_NEEDS_DRAIN_AFTER_DISABLE); > } > > +static inline bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *cpudata) > +{ > + return trbe_has_erratum(cpudata, TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -187,6 +194,28 @@ static inline void trbe_drain_buffer(void) > dsb(nsh); > } > > +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata, u64 trblimitr) > +{ > + /* > + * Enable the TRBE without clearing LIMITPTR which > + * might be required for fetching the buffer limits. > + */ > + trblimitr |= TRBLIMITR_ENABLE; > + write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); > + > + /* Synchronize the TRBE enable event */ > + isb(); > + > + /* > + * Errata affected TRBE implementation will need an additional > + * context synchronization in order to prevent an inconsistent > + * TRBE prohibited region view on the CPU which could possibly > + * corrupt the TRBE buffer or the TRBE state. > + */ > + if (trbe_needs_ctxt_sync_after_enable(cpudata)) > + isb(); > +} Similar to the previous patch, we may move the comment to the function where it is defined. Either ways: Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 years, 7 months

Re: [PATCH V2 5/7] coresight: trbe: Work around the ignored system register writes

by Suzuki K Poulose

On 07/01/2022 01:10, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2064142 might fail to write > into certain system registers after the TRBE has been disabled. Under some > conditions after TRBE has been disabled, writes into certain TRBE registers > TRBLIMITR_EL1, TRBPTR_EL1, TRBBASER_EL1, TRBSR_EL1 and TRBTRG_EL1 will be > ignored and not be effected. > > Work around this problem in the TRBE driver by executing TSB CSYNC and DSB > just after the trace collection has stopped and before performing a system > register write to one of the affected registers. This just updates the TRBE > driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > arch/arm64/Kconfig | 2 +- > drivers/hwtracing/coresight/coresight-trbe.c | 54 ++++++++++++++------ > drivers/hwtracing/coresight/coresight-trbe.h | 8 --- > 3 files changed, 39 insertions(+), 25 deletions(-) > > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index f1651cb71ef3..b6d62672bf7d 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -780,7 +780,7 @@ config ARM64_ERRATUM_2224489 > > config ARM64_ERRATUM_2064142 > bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled" > - depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in > + depends on CORESIGHT_TRBE > default y > help > This option adds the workaround for ARM Cortex-A510 erratum 2064142. > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 276862c07e32..850e9fca6847 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -91,10 +91,12 @@ struct trbe_buf { > */ > #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > +#define TRBE_NEEDS_DRAIN_AFTER_DISABLE 2 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > + [TRBE_NEEDS_DRAIN_AFTER_DISABLE] = ARM64_WORKAROUND_2064142, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -167,6 +169,11 @@ static inline bool trbe_may_write_out_of_range(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_WORKAROUND_WRITE_OUT_OF_RANGE); > } > > +static inline bool trbe_needs_drain_after_disable(struct trbe_cpudata *cpudata) > +{ > + return trbe_has_erratum(cpudata, TRBE_NEEDS_DRAIN_AFTER_DISABLE); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -174,30 +181,42 @@ static int trbe_alloc_node(struct perf_event *event) > return cpu_to_node(event->cpu); > } > > -static void trbe_drain_buffer(void) > +static inline void trbe_drain_buffer(void) > { > tsb_csync(); > dsb(nsh); > } > > -static void trbe_drain_and_disable_local(void) > +static inline void set_trbe_disabled(struct trbe_cpudata *cpudata) > { > u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); > > - trbe_drain_buffer(); > - > /* > * Disable the TRBE without clearing LIMITPTR which > * might be required for fetching the buffer limits. > */ > trblimitr &= ~TRBLIMITR_ENABLE; > write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); > + > + /* > + * Errata affected TRBE implementation will need TSB CSYNC and > + * DSB in order to prevent subsequent writes into certain TRBE > + * system registers from being ignored and not effected. > + */ minor nit: This comment could be moved to the definition of the function "trbe_needs_drain_after_disable()" to make more sense. The name is implicit here indicating, why we are doing a drain. Either ways: Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 years, 7 months

Re: [PATCH V2 4/7] arm64: errata: Add detection for TRBE trace data corruption

by Suzuki K Poulose

On 07/01/2022 01:10, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #1902691 might corrupt trace > data or deadlock, when it's being written into the memory. So effectively > TRBE is broken and hence cannot be used to capture trace data. This adds > a new errata ARM64_ERRATUM_1902691 in arm64 errata framework. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 18 ++++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > arch/arm64/tools/cpucaps | 1 + > 4 files changed, 30 insertions(+) Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com>

3 years, 7 months

Re: [PATCH V2 3/7] arm64: errata: Add detection for TRBE invalid prohibited states

by Suzuki K Poulose

On 07/01/2022 01:10, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #2038923 might get TRBE into > an inconsistent view on whether trace is prohibited within the CPU. As a > result, the trace buffer or trace buffer state might be corrupted. This > happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, > followed by just a single context synchronization event before execution > changes from a context, in which trace is prohibited to one where it isn't, > or vice versa. In these mentioned conditions, the view of whether trace is > prohibited is inconsistent between parts of the CPU, and the trace buffer > or the trace buffer state might be corrupted. This adds a new errata > ARM64_ERRATUM_2038923 in arm64 errata framework. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- Reviewed-by: Suzuki K Poulose <suzuki.poulose(a)arm.com> > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 23 +++++++++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > arch/arm64/tools/cpucaps | 1 + > 4 files changed, 35 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index c9b30e6c2b6c..e0ef3e9a4b8b 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -54,6 +54,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index e27ccfe9fa9c..188eae6ef28d 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 > > If unsure, say Y. > > +config ARM64_ERRATUM_2038923 > + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" > + depends on COMPILE_TEST # Until the CoreSight TRBE driver changes are in > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 2038923. > + > + Affected Cortex-A510 core might cause an inconsistent view on whether trace is > + prohibited within the CPU. As a result, the trace buffer or trace buffer state > + might be corrupted. This happens after TRBE buffer has been enabled by setting > + TRBLIMITR_EL1.E, followed by just a single context synchronization event before > + execution changes from a context, in which trace is prohibited to one where it > + isn't, or vice versa. In these mentioned conditions, the view of whether trace > + is prohibited is inconsistent between parts of the CPU, and the trace buffer or > + the trace buffer state might be corrupted. > + > + Work around this in the driver by preventing an inconsistent view of whether the > + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a > + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or > + two ISB instructions if no ERET is to take place. > + > + If unsure, say Y. > + > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index cbb7d5a9aee7..60b0c1f1d912 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > #endif > +#ifdef CONFIG_ARM64_ERRATUM_2038923 > + { > + .desc = "ARM erratum 2038923", > + .capability = ARM64_WORKAROUND_2038923, > + > + /* Cortex-A510 r0p0 - r0p2 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > + }, > +#endif > { > } > }; > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index fca3cb329e1d..45a06d36d080 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -56,6 +56,7 @@ WORKAROUND_1463225 > WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_2064142 > +WORKAROUND_2038923 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE

3 years, 7 months

Re: [PATCH V2 2/7] arm64: errata: Add detection for TRBE ignored system register writes

by Suzuki K Poulose

3 years, 7 months

Re: [PATCH 3/4] coresight: trbe: Work around the invalid prohibited states

by Suzuki K Poulose

On 06/01/2022 09:10, Anshuman Khandual wrote: > > > On 1/5/22 7:24 PM, Suzuki K Poulose wrote: >> On 05/01/2022 11:16, Anshuman Khandual wrote: >>> >>> >>> On 1/5/22 3:43 PM, Suzuki K Poulose wrote: >>>> Hi Anshuman >>>> >>>> On 05/01/2022 05:05, Anshuman Khandual wrote: >>>>> TRBE implementations affected by Arm erratum #2038923 might get TRBE into >>>>> an inconsistent view on whether trace is prohibited within the CPU. As a >>>>> result, the trace buffer or trace buffer state might be corrupted. This >>>>> happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, >>>>> followed by just a single context synchronization event before execution >>>>> changes from a context, in which trace is prohibited to one where it isn't, >>>>> or vice versa. In these mentioned conditions, the view of whether trace is >>>>> prohibited is inconsistent between parts of the CPU, and the trace buffer >>>>> or the trace buffer state might be corrupted. >>>>> >>>>> Work around this problem in the TRBE driver by preventing an inconsistent >>>>> view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by >>>>> immediately following a change to TRBLIMITR_EL1.E with at least one ISB >>>>> instruction before an ERET, or two ISB instructions if no ERET is to take >>>>> place. This adds a new cpu errata in arm64 errata framework and also >>>>> updates TRBE driver as required. >>>>> >>>>> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >>>>> Cc: Will Deacon <will(a)kernel.org> >>>>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>>>> Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> >>>>> Cc: coresight(a)lists.linaro.org >>>>> Cc: linux-doc(a)vger.kernel.org >>>>> Cc: linux-arm-kernel(a)lists.infradead.org >>>>> Cc: linux-kernel(a)vger.kernel.org >>>>> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >>>>> --- >>>>> Documentation/arm64/silicon-errata.rst | 2 + >>>>> arch/arm64/Kconfig | 23 ++++++++++ >>>>> arch/arm64/kernel/cpu_errata.c | 9 ++++ >>>>> arch/arm64/tools/cpucaps | 1 + >>>>> drivers/hwtracing/coresight/coresight-trbe.c | 47 +++++++++++++++----- >>>>> 5 files changed, 72 insertions(+), 10 deletions(-) >>>> >>>> As with the previous patch, it may be a good idea to split the >>>> patch to arm64 and trbe parts. >>> >>> Sure, will do. >>> >>>> >>>>> >>>>> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >>>>> index c9b30e6c2b6c..e0ef3e9a4b8b 100644 >>>>> --- a/Documentation/arm64/silicon-errata.rst >>>>> +++ b/Documentation/arm64/silicon-errata.rst >>>>> @@ -54,6 +54,8 @@ stable kernels. >>>>> +----------------+-----------------+-----------------+-----------------------------+ >>>>> | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | >>>>> +----------------+-----------------+-----------------+-----------------------------+ >>>>> +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | >>>>> ++----------------+-----------------+-----------------+-----------------------------+ >>>>> | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | >>>>> +----------------+-----------------+-----------------+-----------------------------+ >>>>> | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | >>>>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>>>> index 2105b68d88db..026e34fb6fad 100644 >>>>> --- a/arch/arm64/Kconfig >>>>> +++ b/arch/arm64/Kconfig >>>>> @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 >>>>> If unsure, say Y. >>>>> +config ARM64_ERRATUM_2038923 >>>>> + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" >>>>> + depends on CORESIGHT_TRBE >>>>> + default y >>>>> + help >>>>> + This option adds the workaround for ARM Cortex-A510 erratum 2038923. >>>>> + >>>>> + Affected Cortex-A510 core might cause an inconsistent view on whether trace is >>>>> + prohibited within the CPU. As a result, the trace buffer or trace buffer state >>>>> + might be corrupted. This happens after TRBE buffer has been enabled by setting >>>>> + TRBLIMITR_EL1.E, followed by just a single context synchronization event before >>>>> + execution changes from a context, in which trace is prohibited to one where it >>>>> + isn't, or vice versa. In these mentioned conditions, the view of whether trace >>>>> + is prohibited is inconsistent between parts of the CPU, and the trace buffer or >>>>> + the trace buffer state might be corrupted. >>>>> + >>>>> + Work around this in the driver by preventing an inconsistent view of whether the >>>>> + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a >>>>> + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or >>>>> + two ISB instructions if no ERET is to take place. >>>>> + >>>>> + If unsure, say Y. >>>>> + >>>>> config CAVIUM_ERRATUM_22375 >>>>> bool "Cavium erratum 22375, 24313" >>>>> default y >>>>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >>>>> index cbb7d5a9aee7..60b0c1f1d912 100644 >>>>> --- a/arch/arm64/kernel/cpu_errata.c >>>>> +++ b/arch/arm64/kernel/cpu_errata.c >>>>> @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >>>>> ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>>>> }, >>>>> #endif >>>>> +#ifdef CONFIG_ARM64_ERRATUM_2038923 >>>>> + { >>>>> + .desc = "ARM erratum 2038923", >>>>> + .capability = ARM64_WORKAROUND_2038923, >>>>> + >>>>> + /* Cortex-A510 r0p0 - r0p2 */ >>>>> + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>>>> + }, >>>>> +#endif >>>>> { >>>>> } >>>>> }; >>>>> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps >>>>> index fca3cb329e1d..45a06d36d080 100644 >>>>> --- a/arch/arm64/tools/cpucaps >>>>> +++ b/arch/arm64/tools/cpucaps >>>>> @@ -56,6 +56,7 @@ WORKAROUND_1463225 >>>>> WORKAROUND_1508412 >>>>> WORKAROUND_1542419 >>>>> WORKAROUND_2064142 >>>>> +WORKAROUND_2038923 >>>>> WORKAROUND_TRBE_OVERWRITE_FILL_MODE >>>>> WORKAROUND_TSB_FLUSH_FAILURE >>>>> WORKAROUND_TRBE_WRITE_OUT_OF_RANGE >>>>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>>>> index ec24b62b2cec..0689c6dab96d 100644 >>>>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>>>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>>>> @@ -92,11 +92,13 @@ struct trbe_buf { >>>>> #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 >>>>> #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 >>>>> #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 >>>>> +#define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 >>>>> static int trbe_errata_cpucaps[] = { >>>>> [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, >>>>> [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, >>>>> [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, >>>>> + [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, >>>>> -1, /* Sentinel, must be the last entry */ >>>>> }; >>>>> @@ -174,6 +176,11 @@ static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) >>>>> return trbe_has_erratum(cpudata, TRBE_WORKAROUND_SYSREG_WRITE_FAILURE); >>>>> } >>>>> +static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) >>>>> +{ >>>> >>>> minor nit: trbe_needs_{ctxt_sync, isb}_after_enable() ? >>> >>> trbe_needs_ctxt_sync_after_enable() sounds better. Also will have to change >>> the index above as well .. TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE. >>> >>>> >>>>> + return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); >>>>> +} >>>>> + >>>>> static int trbe_alloc_node(struct perf_event *event) >>>>> { >>>>> if (event->cpu == -1) >>>>> @@ -187,6 +194,30 @@ static inline void trbe_drain_buffer(void) >>>>> dsb(nsh); >>>>> } >>>>> +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) >>>>> +{ >>>>> + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); >>>> >>>> minor nit: This implies we do the TRBE programming in the following >>>> manner in the common case (i.e, TRBE enabled in the beginning of a >>>> session). >>>> -> set TRBE LIMIT >>>> -> read TRBE LIMIT >>>> -> set TRBE ENABLED >>>> >>>> Could we please optimize this ? I believe the buf->trbe_limit >>>> must hold the LIMITR value at any point in time. And thus this >>> >>> But is not bit risky though ! We have got the following places where >>> given trbe_limit instance changes its value. >>> >>> drivers/../coresight-trbe.c: buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE; >>> drivers/../coresight-trbe.c: buf->trbe_limit = compute_trbe_buffer_limit(handle); >>> drivers/../coresight-trbe.c: buf->trbe_limit -= PAGE_SIZE; >> >> Those are the places where we compute the trbe_limit, *before* >> we enable the TRBE. And we don't change recompute the limit >> *without disabling* the TRBE. To make it more clear, the >> only place where we set TRBE enabled without "computing" >> the trbe_limit is when we hit a spurious interrupt. >> But the value in the TRBLIMITR should already match the >> buf->trbe_limit and we are only going to re-enable the >> TRBE with the same limit. The other option is to >> pass down the "limit" to the set_trbe_enabled(). > > Since there are just two instances where set_trbe_enabled() gets > called, passing down an additional parameter 'trblimitr' should > still be okay. Some additional code change (like the following) > will achieve this. Does this look okay ? > > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -201,10 +201,8 @@ static inline void trbe_drain_buffer(void) > dsb(nsh); > } > > -static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) > +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata, u64 trblimitr) > { > - u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); > - > /* > * Enable the TRBE without clearing LIMITPTR which > * might be required for fetching the buffer limits. > @@ -626,7 +624,7 @@ static void set_trbe_limit_pointer_enabled(struct trbe_buf *buf) > trblimitr |= (addr & PAGE_MASK); > > write_sysreg_s(trblimitr, SYS_TRBLIMITR_EL1); You could skip this ^ write. Otherwise looks good to me. Suzuki > - set_trbe_enabled(buf->cpudata); > + set_trbe_enabled(buf->cpudata, trblimitr); > } > > static void trbe_enable_hw(struct trbe_buf *buf) > @@ -1050,13 +1048,14 @@ static int arm_trbe_disable(struct coresight_device *csdev) > static void trbe_handle_spurious(struct perf_output_handle *handle) > { > struct trbe_buf *buf = etm_perf_sink_config(handle); > + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); > > /* > * If the IRQ was spurious, simply re-enable the TRBE > * back without modifying the buffer parameters to > * retain the trace collected so far. > */ > - set_trbe_enabled(buf->cpudata); > + set_trbe_enabled(buf->cpudata, trblimitr); > } > > static int trbe_handle_overflow(struct perf_output_handle *handle) > > >> >>> >>>> function could simply be : >>>> >>>> set_trbe_enabled(trbe_buf) >>>> { >>>> limitr = trbe_buf->limit | LIMITR_ENABLE >>>> write(limitr, TRBLIMITR_EL1); >>>> ... >>>> } >>> >>> Is the potential for performance improvement here, out weigh possible >>> risks of using buf->trbe_limit directly while enabling the TRBE ? >> >> I somehow don't like the fact that we have additional write and read >> for the most common case of the TRBE usage (i.e, for arm_trbe_enable()). >> If we could avoid that, that may be better. >> >> Cheers >> Suzuki

3 years, 7 months

Re: [PATCH 3/4] coresight: trbe: Work around the invalid prohibited states

by Suzuki K Poulose

On 05/01/2022 11:16, Anshuman Khandual wrote: > > > On 1/5/22 3:43 PM, Suzuki K Poulose wrote: >> Hi Anshuman >> >> On 05/01/2022 05:05, Anshuman Khandual wrote: >>> TRBE implementations affected by Arm erratum #2038923 might get TRBE into >>> an inconsistent view on whether trace is prohibited within the CPU. As a >>> result, the trace buffer or trace buffer state might be corrupted. This >>> happens after TRBE buffer has been enabled by setting TRBLIMITR_EL1.E, >>> followed by just a single context synchronization event before execution >>> changes from a context, in which trace is prohibited to one where it isn't, >>> or vice versa. In these mentioned conditions, the view of whether trace is >>> prohibited is inconsistent between parts of the CPU, and the trace buffer >>> or the trace buffer state might be corrupted. >>> >>> Work around this problem in the TRBE driver by preventing an inconsistent >>> view of whether the trace is prohibited or not based on TRBLIMITR_EL1.E by >>> immediately following a change to TRBLIMITR_EL1.E with at least one ISB >>> instruction before an ERET, or two ISB instructions if no ERET is to take >>> place. This adds a new cpu errata in arm64 errata framework and also >>> updates TRBE driver as required. >>> >>> Cc: Catalin Marinas <catalin.marinas(a)arm.com> >>> Cc: Will Deacon <will(a)kernel.org> >>> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> >>> Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> >>> Cc: coresight(a)lists.linaro.org >>> Cc: linux-doc(a)vger.kernel.org >>> Cc: linux-arm-kernel(a)lists.infradead.org >>> Cc: linux-kernel(a)vger.kernel.org >>> Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> >>> --- >>> Documentation/arm64/silicon-errata.rst | 2 + >>> arch/arm64/Kconfig | 23 ++++++++++ >>> arch/arm64/kernel/cpu_errata.c | 9 ++++ >>> arch/arm64/tools/cpucaps | 1 + >>> drivers/hwtracing/coresight/coresight-trbe.c | 47 +++++++++++++++----- >>> 5 files changed, 72 insertions(+), 10 deletions(-) >> >> As with the previous patch, it may be a good idea to split the >> patch to arm64 and trbe parts. > > Sure, will do. > >> >>> >>> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >>> index c9b30e6c2b6c..e0ef3e9a4b8b 100644 >>> --- a/Documentation/arm64/silicon-errata.rst >>> +++ b/Documentation/arm64/silicon-errata.rst >>> @@ -54,6 +54,8 @@ stable kernels. >>> +----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 | >>> +----------------+-----------------+-----------------+-----------------------------+ >>> +| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | >>> ++----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | >>> +----------------+-----------------+-----------------+-----------------------------+ >>> | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | >>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>> index 2105b68d88db..026e34fb6fad 100644 >>> --- a/arch/arm64/Kconfig >>> +++ b/arch/arm64/Kconfig >>> @@ -796,6 +796,29 @@ config ARM64_ERRATUM_2064142 >>> If unsure, say Y. >>> +config ARM64_ERRATUM_2038923 >>> + bool "Cortex-A510: 2038923: workaround TRBE corruption with enable" >>> + depends on CORESIGHT_TRBE >>> + default y >>> + help >>> + This option adds the workaround for ARM Cortex-A510 erratum 2038923. >>> + >>> + Affected Cortex-A510 core might cause an inconsistent view on whether trace is >>> + prohibited within the CPU. As a result, the trace buffer or trace buffer state >>> + might be corrupted. This happens after TRBE buffer has been enabled by setting >>> + TRBLIMITR_EL1.E, followed by just a single context synchronization event before >>> + execution changes from a context, in which trace is prohibited to one where it >>> + isn't, or vice versa. In these mentioned conditions, the view of whether trace >>> + is prohibited is inconsistent between parts of the CPU, and the trace buffer or >>> + the trace buffer state might be corrupted. >>> + >>> + Work around this in the driver by preventing an inconsistent view of whether the >>> + trace is prohibited or not based on TRBLIMITR_EL1.E by immediately following a >>> + change to TRBLIMITR_EL1.E with at least one ISB instruction before an ERET, or >>> + two ISB instructions if no ERET is to take place. >>> + >>> + If unsure, say Y. >>> + >>> config CAVIUM_ERRATUM_22375 >>> bool "Cavium erratum 22375, 24313" >>> default y >>> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c >>> index cbb7d5a9aee7..60b0c1f1d912 100644 >>> --- a/arch/arm64/kernel/cpu_errata.c >>> +++ b/arch/arm64/kernel/cpu_errata.c >>> @@ -607,6 +607,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { >>> ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>> }, >>> #endif >>> +#ifdef CONFIG_ARM64_ERRATUM_2038923 >>> + { >>> + .desc = "ARM erratum 2038923", >>> + .capability = ARM64_WORKAROUND_2038923, >>> + >>> + /* Cortex-A510 r0p0 - r0p2 */ >>> + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) >>> + }, >>> +#endif >>> { >>> } >>> }; >>> diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps >>> index fca3cb329e1d..45a06d36d080 100644 >>> --- a/arch/arm64/tools/cpucaps >>> +++ b/arch/arm64/tools/cpucaps >>> @@ -56,6 +56,7 @@ WORKAROUND_1463225 >>> WORKAROUND_1508412 >>> WORKAROUND_1542419 >>> WORKAROUND_2064142 >>> +WORKAROUND_2038923 >>> WORKAROUND_TRBE_OVERWRITE_FILL_MODE >>> WORKAROUND_TSB_FLUSH_FAILURE >>> WORKAROUND_TRBE_WRITE_OUT_OF_RANGE >>> diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c >>> index ec24b62b2cec..0689c6dab96d 100644 >>> --- a/drivers/hwtracing/coresight/coresight-trbe.c >>> +++ b/drivers/hwtracing/coresight/coresight-trbe.c >>> @@ -92,11 +92,13 @@ struct trbe_buf { >>> #define TRBE_WORKAROUND_OVERWRITE_FILL_MODE 0 >>> #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 >>> #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 >>> +#define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 >>> static int trbe_errata_cpucaps[] = { >>> [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, >>> [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, >>> [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, >>> + [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, >>> -1, /* Sentinel, must be the last entry */ >>> }; >>> @@ -174,6 +176,11 @@ static inline bool trbe_may_fail_sysreg_write(struct trbe_cpudata *cpudata) >>> return trbe_has_erratum(cpudata, TRBE_WORKAROUND_SYSREG_WRITE_FAILURE); >>> } >>> +static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) >>> +{ >> >> minor nit: trbe_needs_{ctxt_sync, isb}_after_enable() ? > > trbe_needs_ctxt_sync_after_enable() sounds better. Also will have to change > the index above as well .. TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE. > >> >>> + return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); >>> +} >>> + >>> static int trbe_alloc_node(struct perf_event *event) >>> { >>> if (event->cpu == -1) >>> @@ -187,6 +194,30 @@ static inline void trbe_drain_buffer(void) >>> dsb(nsh); >>> } >>> +static inline void set_trbe_enabled(struct trbe_cpudata *cpudata) >>> +{ >>> + u64 trblimitr = read_sysreg_s(SYS_TRBLIMITR_EL1); >> >> minor nit: This implies we do the TRBE programming in the following >> manner in the common case (i.e, TRBE enabled in the beginning of a >> session). >> -> set TRBE LIMIT >> -> read TRBE LIMIT >> -> set TRBE ENABLED >> >> Could we please optimize this ? I believe the buf->trbe_limit >> must hold the LIMITR value at any point in time. And thus this > > But is not bit risky though ! We have got the following places where > given trbe_limit instance changes its value. > > drivers/../coresight-trbe.c: buf->trbe_limit = buf->trbe_base + nr_pages * PAGE_SIZE; > drivers/../coresight-trbe.c: buf->trbe_limit = compute_trbe_buffer_limit(handle); > drivers/../coresight-trbe.c: buf->trbe_limit -= PAGE_SIZE; Those are the places where we compute the trbe_limit, *before* we enable the TRBE. And we don't change recompute the limit *without disabling* the TRBE. To make it more clear, the only place where we set TRBE enabled without "computing" the trbe_limit is when we hit a spurious interrupt. But the value in the TRBLIMITR should already match the buf->trbe_limit and we are only going to re-enable the TRBE with the same limit. The other option is to pass down the "limit" to the set_trbe_enabled(). > >> function could simply be : >> >> set_trbe_enabled(trbe_buf) >> { >> limitr = trbe_buf->limit | LIMITR_ENABLE >> write(limitr, TRBLIMITR_EL1); >> ... >> } > > Is the potential for performance improvement here, out weigh possible > risks of using buf->trbe_limit directly while enabling the TRBE ? I somehow don't like the fact that we have additional write and read for the most common case of the TRBE usage (i.e, for arm_trbe_enable()). If we could avoid that, that may be better. Cheers Suzuki

3 years, 7 months

Re: [PATCH 4/4] coresight: trbe: Workaround TRBE trace data corruption

by Suzuki K Poulose

On 05/01/2022 05:05, Anshuman Khandual wrote: > TRBE implementations affected by Arm erratum #1902691 might corrupt trace > data or deadlock, when it's being written into the memory. Workaround this > problem in the driver, by preventing TRBE initialization on affected cpus. > This adds a new cpu errata in arm64 errata framework and also updates TRBE > driver as required. > > Cc: Catalin Marinas <catalin.marinas(a)arm.com> > Cc: Will Deacon <will(a)kernel.org> > Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> > Cc: Suzuki Poulose <suzuki.poulose(a)arm.com> > Cc: coresight(a)lists.linaro.org > Cc: linux-doc(a)vger.kernel.org > Cc: linux-arm-kernel(a)lists.infradead.org > Cc: linux-kernel(a)vger.kernel.org > Signed-off-by: Anshuman Khandual <anshuman.khandual(a)arm.com> > --- > Documentation/arm64/silicon-errata.rst | 2 ++ > arch/arm64/Kconfig | 16 ++++++++++++++++ > arch/arm64/kernel/cpu_errata.c | 9 +++++++++ > arch/arm64/tools/cpucaps | 1 + > drivers/hwtracing/coresight/coresight-trbe.c | 12 ++++++++++++ > 5 files changed, 40 insertions(+) > > diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst > index e0ef3e9a4b8b..50018f60c4d4 100644 > --- a/Documentation/arm64/silicon-errata.rst > +++ b/Documentation/arm64/silicon-errata.rst > @@ -56,6 +56,8 @@ stable kernels. > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 | > +----------------+-----------------+-----------------+-----------------------------+ > +| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 | > ++----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | > +----------------+-----------------+-----------------+-----------------------------+ > | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | > diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig > index 026e34fb6fad..1ea5c3b4aac0 100644 > --- a/arch/arm64/Kconfig > +++ b/arch/arm64/Kconfig > @@ -819,6 +819,22 @@ config ARM64_ERRATUM_2038923 > > If unsure, say Y. > > +config ARM64_ERRATUM_1902691 > + bool "Cortex-A510: 1902691: workaround TRBE trace corruption" > + depends on CORESIGHT_TRBE > + default y > + help > + This option adds the workaround for ARM Cortex-A510 erratum 1902691. > + > + Affected Cortex-A510 core might cause trace data corruption, when being written > + into the memory. Effectively TRBE is broken and hence cannot be used to capture > + trace data. > + > + Work around this problem in the driver by just preventing TRBE initialization on > + affected cpus. > + > + If unsure, say Y. > + It might be better to add : "The firmware must have disabled the access to TRBE for the kernel on such implementations. This will cover the kernel for any firmware that doesn't do this already" > config CAVIUM_ERRATUM_22375 > bool "Cavium erratum 22375, 24313" > default y > diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c > index 60b0c1f1d912..a3336dfb5a8a 100644 > --- a/arch/arm64/kernel/cpu_errata.c > +++ b/arch/arm64/kernel/cpu_errata.c > @@ -615,6 +615,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = { > /* Cortex-A510 r0p0 - r0p2 */ > ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2) > }, > +#endif > +#ifdef CONFIG_ARM64_ERRATUM_1902691 > + { > + .desc = "ARM erratum 1902691", > + .capability = ARM64_WORKAROUND_1902691, > + > + /* Cortex-A510 r0p0 - r0p1 */ > + ERRATA_MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 1) > + }, > #endif > { > } > diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps > index 45a06d36d080..e7719e8f18de 100644 > --- a/arch/arm64/tools/cpucaps > +++ b/arch/arm64/tools/cpucaps > @@ -57,6 +57,7 @@ WORKAROUND_1508412 > WORKAROUND_1542419 > WORKAROUND_2064142 > WORKAROUND_2038923 > +WORKAROUND_1902691 > WORKAROUND_TRBE_OVERWRITE_FILL_MODE > WORKAROUND_TSB_FLUSH_FAILURE > WORKAROUND_TRBE_WRITE_OUT_OF_RANGE > diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtracing/coresight/coresight-trbe.c > index 0689c6dab96d..b9b4e34fac15 100644 > --- a/drivers/hwtracing/coresight/coresight-trbe.c > +++ b/drivers/hwtracing/coresight/coresight-trbe.c > @@ -93,12 +93,14 @@ struct trbe_buf { > #define TRBE_WORKAROUND_WRITE_OUT_OF_RANGE 1 > #define TRBE_WORKAROUND_SYSREG_WRITE_FAILURE 2 > #define TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE 3 > +#define TRBE_IS_BROKEN 4 > > static int trbe_errata_cpucaps[] = { > [TRBE_WORKAROUND_OVERWRITE_FILL_MODE] = ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, > [TRBE_WORKAROUND_WRITE_OUT_OF_RANGE] = ARM64_WORKAROUND_TRBE_WRITE_OUT_OF_RANGE, > [TRBE_WORKAROUND_SYSREG_WRITE_FAILURE] = ARM64_WORKAROUND_2064142, > [TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE] = ARM64_WORKAROUND_2038923, > + [TRBE_IS_BROKEN] = ARM64_WORKAROUND_1902691, > -1, /* Sentinel, must be the last entry */ > }; > > @@ -181,6 +183,11 @@ static inline bool trbe_may_corrupt_with_enable(struct trbe_cpudata *cpudata) > return trbe_has_erratum(cpudata, TRBE_WORKAROUND_CORRUPTION_WITH_ENABLE); > } > > +static inline bool trbe_is_broken(struct trbe_cpudata *cpudata) > +{ > + return trbe_has_erratum(cpudata, TRBE_IS_BROKEN); > +} > + > static int trbe_alloc_node(struct perf_event *event) > { > if (event->cpu == -1) > @@ -1291,6 +1298,11 @@ static void arm_trbe_probe_cpu(void *info) > */ > trbe_check_errata(cpudata); > > + if (trbe_is_broken(cpudata)) { > + pr_err("TRBE might corrupt the trace on cpu %d\n", cpu); It may be better to say: "Disabling TRBE on CPU%d due to erratum" Otherwise looks good to me. Suzuki

3 years, 7 months

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