CoreSight

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6 participants
2630 discussions

[PATCH 0/7] coresight: etm4x: Migrate AMBA devices to platform driver

by Anshuman Khandual

CoreSight ETM4x devices could be accessed either via MMIO (handled via amba_driver) or CPU system instructions (handled via platform driver). But this has the following issues : - Each new CPU comes up with its own PID and thus we need to keep on adding the "known" PIDs to get it working with AMBA driver. While the ETM4 architecture (and CoreSight architecture) defines way to identify a device as ETM4. Thus older kernels won't be able to "discover" a newer CPU, unless we add the PIDs. - With ACPI, the ETM4x devices have the same HID to identify the device irrespective of the mode of access. This creates a problem where two different drivers (both AMBA based driver and platform driver) would hook into the "HID" and could conflict. e.g., if AMBA driver gets hold of a non-MMIO device, the probe fails. If we have single driver hooked into the given "HID", we could handle them seamlessly, irrespective of the mode of access. - CoreSight is heavily dependent on the runtime power management. With ACPI, amba_driver doesn't get us anywhere with handling the power and thus one need to always turn the power ON to use them. Moving to platform driver gives us the power management for free. Due to all of the above, we are moving the MMIO based etm4x devices to be supported via platform driver. The series makes the existing platform driver generic to handle both type of the access modes. With that we can also remove the etm4x amba driver. Finally, we need a way to make sure the new driver gets control of the ETM4x device on a DT based system. CoreSight devices have always had the "arm,primecell" in the compatible list. But the way this is handled currently in OF code is a bit messy. The ETM4x devices are identified by "arm,coresight-etm4x". The platform driver can never get a chance to probe these devices, since the "arm,primecell" takes priority and is hard-coded in the OF code. We have two options here : 1) Remove the arm,primecell from all DTS. This is fine for "new" kernels with this change. But, for existing boards, using an older kernel will break. Thus, is not preferred. 2) Add a white list of "compatibles" where the "priority" of the "arm,primecell" can be ignored. The series implements (2) above and applies on 6.3-rc2. Cc: Steve Clevenger <scclevenger(a)os.amperecomputing.com> Cc: Rob Herring <robh+dt(a)kernel.org> Cc: Frank Rowand <frowand.list(a)gmail.com> Cc: Russell King (Oracle) <linux(a)armlinux.org.uk> Cc: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> Cc: "Rafael J. Wysocki" <rafael(a)kernel.org> Cc: Len Brown <lenb(a)kernel.org> Cc: Sudeep Holla <sudeep.holla(a)arm.com> Cc: Lorenzo Pieralisi <lpieralisi(a)kernel.org> Cc: Mathieu Poirier <mathieu.poirier(a)linaro.org> Cc: Suzuki K Poulose <suzuki.poulose(a)arm.com> Cc: Mike Leach <mike.leach(a)linaro.org> Cc: Leo Yan <leo.yan(a)linaro.org> Cc: devicetree(a)vger.kernel.org Cc: linux-acpi(a)vger.kernel.org Cc: coresight(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-kernel(a)vger.kernel.org Anshuman Khandual (6): coresight: etm4x: Allocate and device assign 'struct etmv4_drvdata' earlier coresight: etm4x: Drop iomem 'base' argument from etm4_probe() coresight: etm4x: Drop pid argument from etm4_probe() coresight: etm4x: Change etm4_platform_driver driver for MMIO devices of/platform: Skip coresight etm4x devices from AMBA bus coresight: etm4x: Drop the AMBA driver Suzuki Poulose (1): coresight: etm4x: Add ACPI support in platform driver drivers/acpi/acpi_amba.c | 1 - .../coresight/coresight-etm4x-core.c | 171 ++++++++---------- drivers/hwtracing/coresight/coresight-etm4x.h | 3 + drivers/of/platform.c | 10 +- include/linux/coresight.h | 56 ++++++ 5 files changed, 143 insertions(+), 98 deletions(-) -- 2.25.1

2 years, 10 months

Re: [PATCH 4/7] coresight: etm4x: Change etm4_platform_driver driver for MMIO devices

by Anshuman Khandual

On 3/18/23 15:54, kernel test robot wrote: > Hi Anshuman, > > Thank you for the patch! Perhaps something to improve: > > [auto build test WARNING on robh/for-next] > [also build test WARNING on soc/for-next rafael-pm/linux-next linus/master v6.3-rc2 next-20230317] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Anshuman-Khandual/coresight-… > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next > patch link: https://lore.kernel.org/r/20230317030501.1811905-5-anshuman.khandual%40arm.… > patch subject: [PATCH 4/7] coresight: etm4x: Change etm4_platform_driver driver for MMIO devices > config: arm64-buildonly-randconfig-r002-20230312 (https://download.01.org/0day-ci/archive/20230318/202303181800.KxbuwjRT-lkp@…) > compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project 67409911353323ca5edf2049ef0df54132fa1ca7) > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # install arm64 cross compiling tool for clang build > # apt-get install binutils-aarch64-linux-gnu > # https://github.com/intel-lab-lkp/linux/commit/f02ad9e7f97ab4fc1f90c7e639900… > git remote add linux-review https://github.com/intel-lab-lkp/linux > git fetch --no-tags linux-review Anshuman-Khandual/coresight-etm4x-Allocate-and-device-assign-struct-etmv4_drvdata-earlier/20230317-110755 > git checkout f02ad9e7f97ab4fc1f90c7e6399004e9ec89ef26 > # save the config file > mkdir build_dir && cp config build_dir/.config > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 olddefconfig > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/hwtracing/coresight/ > > If you fix the issue, kindly add following tag where applicable > | Reported-by: kernel test robot <lkp(a)intel.com> > | Link: https://lore.kernel.org/oe-kbuild-all/202303181800.KxbuwjRT-lkp@intel.com/ > > All warnings (new ones prefixed by >>): > >>> drivers/hwtracing/coresight/coresight-etm4x-core.c:2336:32: warning: unused variable 'etm4_dev_pm_ops' [-Wunused-const-variable] > static const struct dev_pm_ops etm4_dev_pm_ops = { These pm_ops needs to tagged along with the platform driver. diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 3ce2b4911a49..fe10dd91183e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -2280,6 +2280,7 @@ static struct platform_driver etm4_platform_driver = { .of_match_table = etm4_match, .acpi_match_table = ACPI_PTR(etm4x_acpi_ids), .suppress_bind_attrs = true, + .pm = &etm4_dev_pm_ops, }, };

2 years, 10 months

Re: [PATCH 3/7] coresight: etm4x: Drop pid argument from etm4_probe()

by Anshuman Khandual

On 3/18/23 13:51, kernel test robot wrote: > Hi Anshuman, > > Thank you for the patch! Perhaps something to improve: > > [auto build test WARNING on robh/for-next] > [also build test WARNING on soc/for-next rafael-pm/linux-next linus/master v6.3-rc2 next-20230317] > [If your patch is applied to the wrong git tree, kindly drop us a note. > And when submitting patch, we suggest to use '--base' as documented in > https://git-scm.com/docs/git-format-patch#_base_tree_information] > > url: https://github.com/intel-lab-lkp/linux/commits/Anshuman-Khandual/coresight-… > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next > patch link: https://lore.kernel.org/r/20230317030501.1811905-4-anshuman.khandual%40arm.… > patch subject: [PATCH 3/7] coresight: etm4x: Drop pid argument from etm4_probe() > config: arm64-randconfig-r021-20230312 (https://download.01.org/0day-ci/archive/20230318/202303181632.wBUDE5wa-lkp@…) > compiler: aarch64-linux-gcc (GCC) 12.1.0 > reproduce (this is a W=1 build): > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross > chmod +x ~/bin/make.cross > # https://github.com/intel-lab-lkp/linux/commit/39e224e4248f0f7b2c59b97c12a12… > git remote add linux-review https://github.com/intel-lab-lkp/linux > git fetch --no-tags linux-review Anshuman-Khandual/coresight-etm4x-Allocate-and-device-assign-struct-etmv4_drvdata-earlier/20230317-110755 > git checkout 39e224e4248f0f7b2c59b97c12a12f8343ab900e > # save the config file > mkdir build_dir && cp config build_dir/.config > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 olddefconfig > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/hwtracing/coresight/ > > If you fix the issue, kindly add following tag where applicable > | Reported-by: kernel test robot <lkp(a)intel.com> > | Link: https://lore.kernel.org/oe-kbuild-all/202303181632.wBUDE5wa-lkp@intel.com/ > > All warnings (new ones prefixed by >>): > > drivers/hwtracing/coresight/coresight-etm4x-core.c: In function 'etm4_init_arch_data': >>> drivers/hwtracing/coresight/coresight-etm4x-core.c:1169:43: warning: passing argument 2 of 'etm4_check_arch_features' makes integer from pointer without a cast [-Wint-conversion] > 1169 | etm4_check_arch_features(drvdata, csa); > | ^~~ > | | > | struct csdev_access * > drivers/hwtracing/coresight/coresight-etm4x-core.c:389:51: note: expected 'unsigned int' but argument is of type 'struct csdev_access *' > 389 | unsigned int id) > | ~~~~~~~~~~~~~^~ Fallback stub's signature also needs an update. I will fold this change in next series. --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -388,7 +388,7 @@ static void etm4_disable_arch_specific(struct etmv4_drvdata *drvdata) } static void etm4_check_arch_features(struct etmv4_drvdata *drvdata, - unsigned int id) + struct csdev_access *csa) { } #endif /* CONFIG_ETM4X_IMPDEF_FEATURE */

2 years, 10 months

Re: [PATCH 2/3] coresight etm4x: Early clear TRCOSLAR.OSLK prior to TRCIDR1 read

by Suzuki K Poulose

Hi Steve On 06/03/2023 05:54, Steve Clevenger wrote: > An Ampere Computing design decision is MMIO reads are considered the > same as an external debug access. If TRCOSLAR.OSLK is left set, the > TRCIDR1 access results in a bus fault followed by a kernel panic. A > TRCIDR1 read should be valid regardless of TRCOSLAR.OSLK provided MMIO > access (now deprecated) is supported. > > The Ampere work around is to early clear ETM TRCOSLAR.OSLK prior to > TRCIDR1 access. Do not distinguish between manufacturers. > AC03_DEBUG_06 is described in the AmpereOne Developer Errata: > > Add Ampere ETM PID required for Coresight ETM driver support. > > https://solutions.amperecomputing.com/customer-connect/products/AmpereOne-d… > > Signed-off-by: Steve Clevenger <scclevenger(a)os.amperecomputing.com> I went back to the CoreSight ETM4x architecture and this is not an erratum at your end. This is actually a bug in the ETMv4 driver. TRCIDR1 is part of the "Trace" and not "Management" registers of ETMv4. Access to "Trace" registers without OSLK is going to cause issues. (Un)Fortunately, we never hit this on existing systems, but that doesn't mean it can stay there. So we should really fix our detection and only rely on accessing the TRCDEVARCH to detect the device to be ETMv4. I have a sent out the fix here [0], are you able to test it : [0] https://lkml.kernel.org/r/20230317115728.1358368-1-suzuki.poulose@arm.com Suzuki

2 years, 11 months

[PATCH] coresight: core: Add sysfs node to reset all sources and sinks

by Mao Jinlong

Add sysfs node to reset all the sources and sinks. When mltiple sources are enabled, write 1 to reset_source_sink node to disable all sources and sinks. Signed-off-by: Mao Jinlong <quic_jinlmao(a)quicinc.com> --- drivers/hwtracing/coresight/coresight-core.c | 106 +++++++++++++++++-- 1 file changed, 99 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c index d3bf82c0de1d..06741ed2dee7 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -458,6 +458,28 @@ static bool coresight_disable_source(struct coresight_device *csdev) return !csdev->enable; } +/** + * coresight_get_source - Get the source from the path + * + * @path: The list of devices. + * + * Returns the soruce csdev. + * + */ +static struct coresight_device *coresight_get_source(struct list_head *path) +{ + struct coresight_device *csdev; + + if (!path) + return NULL; + + csdev = list_first_entry(path, struct coresight_node, link)->csdev; + if (csdev->type != CORESIGHT_DEV_TYPE_SOURCE) + return NULL; + + return csdev; +} + /* * coresight_disable_path_from : Disable components in the given path beyond * @nd in the list. If @nd is NULL, all the components, except the SOURCE are @@ -1159,20 +1181,18 @@ int coresight_enable(struct coresight_device *csdev) } EXPORT_SYMBOL_GPL(coresight_enable); -void coresight_disable(struct coresight_device *csdev) +static void _coresight_disable(struct coresight_device *csdev) { int cpu, ret; struct list_head *path = NULL; u32 hash; - mutex_lock(&coresight_mutex); - ret = coresight_validate_source(csdev, __func__); if (ret) - goto out; + return; if (!csdev->enable || !coresight_disable_source(csdev)) - goto out; + return; switch (csdev->subtype.source_subtype) { case CORESIGHT_DEV_SUBTYPE_SOURCE_PROC: @@ -1187,7 +1207,7 @@ void coresight_disable(struct coresight_device *csdev) path = idr_find(&path_idr, hash); if (path == NULL) { pr_err("Path is not found for %s\n", dev_name(&csdev->dev)); - goto out; + return; } idr_remove(&path_idr, hash); break; @@ -1198,8 +1218,12 @@ void coresight_disable(struct coresight_device *csdev) coresight_disable_path(path); coresight_release_path(path); +} -out: +void coresight_disable(struct coresight_device *csdev) +{ + mutex_lock(&coresight_mutex); + _coresight_disable(csdev); mutex_unlock(&coresight_mutex); } EXPORT_SYMBOL_GPL(coresight_disable); @@ -1761,8 +1785,76 @@ char *coresight_alloc_device_name(struct coresight_dev_list *dict, } EXPORT_SYMBOL_GPL(coresight_alloc_device_name); +/* + * Set the sink active status to false. + */ +static int coresight_reset_sink(struct device *dev, void *data) +{ + struct coresight_device *csdev = to_coresight_device(dev); + + if ((csdev->type == CORESIGHT_DEV_TYPE_SINK || + csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) && + csdev->activated) + csdev->activated = false; + + return 0; +} + +static void coresight_reset_all_sink(void) +{ + bus_for_each_dev(&coresight_bustype, NULL, NULL, coresight_reset_sink); +} + +static ssize_t reset_source_sink_store(struct bus_type *bus, + const char *buf, size_t size) +{ + int id, cpu, ret = 0; + unsigned long val; + struct coresight_device *csdev; + struct list_head *path = NULL; + + ret = kstrtoul(buf, 10, &val); + if (ret) + return ret; + + mutex_lock(&coresight_mutex); + + /* Disable all per cpu sources */ + for_each_present_cpu(cpu) { + path = per_cpu(tracer_path, cpu); + if (path) { + csdev = coresight_get_source(path); + if (!csdev) + continue; + } + _coresight_disable(csdev); + } + + /* Disable all sources which aren't associated with CPU */ + idr_for_each_entry (&path_idr, path, id) { + csdev = coresight_get_source(path); + if (!csdev) + continue; + + _coresight_disable(csdev); + } + /* Reset all activated sinks */ + coresight_reset_all_sink(); + + mutex_unlock(&coresight_mutex); + return size; +} +static BUS_ATTR_WO(reset_source_sink); + +static struct attribute *coresight_reset_source_sink_attrs[] = { + &bus_attr_reset_source_sink.attr, + NULL, +}; +ATTRIBUTE_GROUPS(coresight_reset_source_sink); + struct bus_type coresight_bustype = { .name = "coresight", + .bus_groups = coresight_reset_source_sink_groups, }; static int __init coresight_init(void) -- 2.39.0

2 years, 11 months

[RESEND PATCH] perf cs-etm: add error logging to cs_etm_is_etmv4()

by Junhao He

On the HiSilicon platform, there is one ETM per logic core. When setting up SMT, not every process has an ETM. So the path ".../cs_etm/cpux/trcidr/trcidr0" does not exist, the function perf_pmu__scan_file() return an error. However, the command 'perf record' will returns silently and don't print. After this patch, log a error when read fails that makes it easy for users to debug. root@localhost:/# perf record -e /cs_etm/@ultra_smb0/ -C 3 uname -a cs_etm: can't read file cpu3/trcidr/trcidr0 root@localhost:/# Signed-off-by: Junhao He <hejunhao3(a)huawei.com> --- tools/perf/arch/arm/util/cs-etm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 7f71c8a237ff..19ea17430399 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -585,7 +585,6 @@ cs_etm_info_priv_size(struct auxtrace_record *itr __maybe_unused, static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu) { - bool ret = false; char path[PATH_MAX]; int scan; unsigned int val; @@ -600,9 +599,10 @@ static bool cs_etm_is_etmv4(struct auxtrace_record *itr, int cpu) /* The file was read successfully, we have a winner */ if (scan == 1) - ret = true; + return true; - return ret; + pr_err("%s: can't read file %s\n", CORESIGHT_ETM_PMU_NAME, path); + return false; } static int cs_etm_get_ro(struct perf_pmu *pmu, int cpu, const char *path) -- 2.33.0

2 years, 11 months

Re: [PATCH v1 0/3] Add support to configure Coresight Dummy subunit

by Suzuki K Poulose

On 16/03/2023 03:20, Hao Zhang wrote: > Introduction of Coresight Dummy subunit > The Coresight Dummy subunit is for Coresight Dummy component, there are some > specific Coresight devices that HLOS don't have permission to access. Such as What is HLOS ? > some TPDMs, they would be configured in NON-HLOS side, but it's necessary to What is NON-HLOS ? > build Coresight path for it to debug. So there need driver to register dummy > devices as Coresight devices. Build a path for who to debug ? If this is used by some privileged software, shouldn't that do all of the work ? Suzuki > > Commit link: > https://git.codelinaro.org/clo/linux-kernel/coresight/-/tree/coresight-dummy > > Hao Zhang (3): > Coresight: Add coresight dummy driver > dt-bindings: arm: Add Coresight Dummy Trace YAML schema > Documentation: trace: Add documentation for Coresight Dummy Trace > > .../bindings/arm/qcom,coresight-dummy.yaml | 129 +++++++++++++ > .../trace/coresight/coresight-dummy.rst | 58 ++++++ > drivers/hwtracing/coresight/Kconfig | 11 ++ > drivers/hwtracing/coresight/Makefile | 1 + > drivers/hwtracing/coresight/coresight-dummy.c | 176 ++++++++++++++++++ > 5 files changed, 375 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/qcom,coresight-dummy.yaml > create mode 100644 Documentation/trace/coresight/coresight-dummy.rst > create mode 100644 drivers/hwtracing/coresight/coresight-dummy.c >

2 years, 11 months

[PATCH 1/2] perf cs-etm: Reduce verbosity of ts_source warning

by James Clark

This is printed as a warning but it is normal behavior that users shouldn't be expected to do anything about. Reduce the warning level to debug3 so it's only seen in verbose mode to avoid confusion. Signed-off-by: James Clark <james.clark(a)arm.com> --- tools/perf/arch/arm/util/cs-etm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/perf/arch/arm/util/cs-etm.c b/tools/perf/arch/arm/util/cs-etm.c index 7f71c8a237ff..59b50dd70330 100644 --- a/tools/perf/arch/arm/util/cs-etm.c +++ b/tools/perf/arch/arm/util/cs-etm.c @@ -694,8 +694,8 @@ static void cs_etm_save_etmv4_header(__u64 data[], struct auxtrace_record *itr, data[CS_ETMV4_TS_SOURCE] = (__u64) cs_etm_get_ro_signed(cs_etm_pmu, cpu, metadata_etmv4_ro[CS_ETMV4_TS_SOURCE]); else { - pr_warning("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n", - cpu); + pr_debug3("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n", + cpu); data[CS_ETMV4_TS_SOURCE] = (__u64) -1; } } @@ -729,8 +729,8 @@ static void cs_etm_save_ete_header(__u64 data[], struct auxtrace_record *itr, in data[CS_ETE_TS_SOURCE] = (__u64) cs_etm_get_ro_signed(cs_etm_pmu, cpu, metadata_ete_ro[CS_ETE_TS_SOURCE]); else { - pr_warning("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n", - cpu); + pr_debug3("[%03d] pmu file 'ts_source' not found. Fallback to safe value (-1)\n", + cpu); data[CS_ETE_TS_SOURCE] = (__u64) -1; } } -- 2.34.1

2 years, 11 months

Re: [BUG] perf: No samples found when using kcore + coresight

by Leo Yan

On Thu, Mar 09, 2023 at 10:06:41AM -0800, Yang Shi wrote: [...] > > I reviewed your shared dump, the bad and good perf data both contain the > > dummy event with 'text_poke = 1'. Could you confirm the shared dump in > > your previous email is correct or not? > > Oops, sorry. I pasted the wrong log. The good one looks like > (generated by v5.19): > > # captured on : Wed Mar 8 18:02:58 2023 > # header version : 1 > # data offset : 408 > # data size : 22640 > # feat offset : 23048 > # hostname : fedora > # os release : 6.2.0-coresight+ > # perf version : 5.19.g3d7cb6b04c3f > # arch : aarch64 > # nrcpus online : 128 > # nrcpus avail : 128 > # cpuid : 0x00000000c00fac30 > # total memory : 2108862504 kB > # cmdline : /home/yshi/linux/tools/perf/perf record -e > cs_etm/@tmc_etf63/k --kcore --per-thread -- taskset --cpu-list 1 uname > # event : name = cs_etm/@tmc_etf63/k, , id = { 3832 }, type = 9, size > = 128, { sample_period, sample_freq } = 1, sample_type = > IP|TID|IDENTIFIER, read_format = ID, d > isabled = 1, exclude_user = 1, exclude_hv = 1, enable_on_exec = 1, > sample_id_all = 1, { bp_len, config2 } = 0x12792918 > # event : name = dummy:u, , id = { 3833 }, type = 1, size = 128, > config = 0x9, { sample_period, sample_freq } = 1, sample_type = > IP|TID|IDENTIFIER, read_format = ID, > disabled = 1, exclude_kernel = 1, exclude_hv = 1, mmap = 1, comm = 1, > enable_on_exec = 1, task = 1, sample_id_all = 1, exclude_guest = 1, > mmap2 = 1, comm_exec = 1, > context_switch = 1, ksymbol = 1, bpf_event = 1 > # CPU_TOPOLOGY info available, use -I to display > # NUMA_TOPOLOGY info available, use -I to display > # pmu mappings: armv8_pmuv3_0 = 8, software = 1, arm_cmn_0 = 10, > uprobe = 7, cs_etm = 9, breakpoint = 5, tracepoint = 2, arm_cmn_1 = > 11, kprobe = 6 > # contains AUX area data (e.g. instruction trace) > # CACHE info available, use -I to display > # time of first sample : 18446744073.709551 > # time of last sample : 18446744073.709551 > # sample duration : 0.000 ms > # MEM_TOPOLOGY info available, use -I to display > # missing features: TRACING_DATA CPUDESC BRANCH_STACK GROUP_DESC STAT > CLOCKID DIR_FORMAT COMPRESSED CPU_PMU_CAPS CLOCK_DATA HYBRID_TOPOLOGY > HYBRID_CPU_PMU_CAPS Thanks for confirmation. Just a quick summary, here we have two issues: - With command: perf record -e cs_etm/@tmc_etf63/k --kcore --per-thread \ -- taskset --cpu-list 1 uname", perf doesn't enable "text poke" attribution. - With command: perf record -e cs_etm/@tmc_etf63/k --kcore --per-thread \ -- taskset --cpu-list 1 true (in your previous email), or ... perf record --kcore -e cs_etm/@tmc_etf63/k --per-thread \ -- taskset --cpu-list 1 uname (in your shared perf data file), perf enables "text poke" attribution, in this case, perf fails to decode Arm CoreSight trace data. [...] > > Do you mind to share the bad perf.data file with James and me? > > Please check the attachment out. Thanks for looking into this problem. Thank you for sharing the data. We will look into it. Leo

2 years, 11 months

Re: [PATCH 3/3] coresight etm4x: Add 32-bit read/write option to split 64-bit words

by Leo Yan

On Thu, Mar 09, 2023 at 12:46:55PM -0800, Steve Clevenger wrote: [...] > > #include <linux/io-64-nonatomic-hi-lo.h> > > > > static inline u64 etm4x_relaxed_read64(struct csdev_access *csa, unsigned int offset) > > { > > if (csa->io_mem) { > > if (csa->no_quad_mmio) > > return hi_lo_readq_relaxed(csa->base + offset); > > else > > return readq_relaxed(csa->base + offset); > > } else { > > return read_etm4x_sysreg_offset(offset, true); > > } > > } > > > > I'm not saying to play magic on {writeq|readq}_relaxed(), would it be > > fine to directly call hi_lo_readq_relaxed()? > > I can do this, and it would work fine. Without compile protection, one > concern is the silent inclusion of io-64-nonatomic-hi-lo.h definitions > for readq_relaxed/writeq_relaxed if the include hierarchy gets changed. > The only (minor) risk I see is to performance. Yeah, we could include io.h ahead io-64-nonatomic-hi-lo.h: #include <linux/io.h> #include <linux/io-64-nonatomic-lo-hi.h> Thus we can get the definitions for {readq|writeq}_relaxed() from "io.h". > Second, it seems to me the hi_lo and lo_hi macros were intended to deal > with endianness. IMO, the implementation I offered is agnostic without a > hint to endianness or atomicity. Seems to me, kernel functions with explict endianness naming is not bad thing :) > The CoreSight maintainer audience is > limited and already aware of these issues, so I'll make the change for you. Thanks! Suzuki, Mike, I think it's good to get your opinion before Steve can proceed for updating patch. Leo

2 years, 11 months

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