CoreSight September 2025

coresight@lists.linaro.org

8 participants
42 discussions

Re: [PATCH v1] coresight: tpda: fix the logic to setup the element size

by Suzuki K Poulose

On 06/08/2025 09:09, Jie Gan wrote: > Some TPDM devices support both CMB and DSB datasets, requiring > the system to enable the port with both corresponding element sizes. > > Currently, the logic treats tpdm_read_element_size as successful if > the CMB element size is retrieved correctly, regardless of whether > the DSB element size is obtained. This behavior causes issues > when parsing data from TPDM devices that depend on both element sizes. > > To address this, the function should explicitly fail if the DSB > element size cannot be read correctly. But what is the device only has CMB ? Back when this was originally merged, we raised this question and the answer was, "Only one is supported, not both." But this sounds like that is wrong. Could we defer the "Warning" to the caller. i.e., Let the caller figure out the if the DSB size is found and predicate that on the DSB support on the TPDM. Suzuki > > Fixes: e6d7f5252f73 ("coresight-tpda: Add support to configure CMB element") > Signed-off-by: Jie Gan <jie.gan(a)oss.qualcomm.com> > --- > drivers/hwtracing/coresight/coresight-tpda.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c > index 0633f04beb24..333b3cb23685 100644 > --- a/drivers/hwtracing/coresight/coresight-tpda.c > +++ b/drivers/hwtracing/coresight/coresight-tpda.c > @@ -71,6 +71,8 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > if (tpdm_data->dsb) { > rc = fwnode_property_read_u32(dev_fwnode(csdev->dev.parent), > "qcom,dsb-element-bits", &drvdata->dsb_esize); > + if (rc) > + goto out; > } > > if (tpdm_data->cmb) { > @@ -78,6 +80,7 @@ static int tpdm_read_element_size(struct tpda_drvdata *drvdata, > "qcom,cmb-element-bits", &drvdata->cmb_esize); > } > > +out: > if (rc) > dev_warn_once(&csdev->dev, > "Failed to read TPDM Element size: %d\n", rc);

2 weeks, 5 days

Re: [PATCH v2] coresight-etm4x: Conditionally access register TRCEXTINSELR

by Suzuki K Poulose

On Tue, 12 Aug 2025 01:24:45 -0700, Yuanfang Zhang wrote: > The TRCEXTINSELR is only implemented if TRCIDR5.NUMEXTINSEL > 0. > To avoid invalid accesses, introduce a check on numextinsel > (derived from TRCIDR5[11:9]) before reading or writing to this register. > > The patch looks good to me. May be we could expose this via sysfs, like we do for the other fields. That can be a separate patch without the Fixes tag. I have applied this patch to -next, thanks! [1/1] coresight-etm4x: Conditionally access register TRCEXTINSELR https://git.kernel.org/coresight/c/fa71e9cb4cfa Best regards, -- Suzuki K Poulose <suzuki.poulose(a)arm.com>

2 weeks, 6 days

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CoreSight September 2025