All,
I am testing Volodymyr's dynamic shared memory patches, which depends on the non-sec DDR support that has been added in OP-TEE recently. I am testing this on a Juno platform which has a DDR split into 2 different regions: 0x0_80000000 2G 0x8_80000000 6G
The platform_config.h allows you to define a DRAM0 base/size which then is used in the macro: register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE);
I tried defining the second DDR region in platform_config.h and a second call to register_nsec_ddr(), but that did not work.
Has anyone succeeded in having the nsec DDR split into 2 regions?
Would Jen's patch: core: assign non-sec DDR configuration from DT
...solve this issue? Right now the Juno does not use CFG_DT, and when I turn it on OP-TEE reports that it cannot find the device tree.
Thanks, Stuart
Hi Stuart,
On Tue, Aug 15, 2017 at 4:20 PM, Stuart Yoder stuart.yoder@arm.com wrote:
All,
I am testing Volodymyr's dynamic shared memory patches, which depends on the non-sec DDR support that has been added in OP-TEE recently. I am testing this on a Juno platform which has a DDR split into 2 different regions: 0x0_80000000 2G 0x8_80000000 6G
The platform_config.h allows you to define a DRAM0 base/size which then is used in the macro: register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE);
I tried defining the second DDR region in platform_config.h and a second call to register_nsec_ddr(), but that did not work.
Has anyone succeeded in having the nsec DDR split into 2 regions?
Would Jen's patch: core: assign non-sec DDR configuration from DT
No, because as you point out the DT can't be found by OP-TEE. DT is loaded later and provided to the kernel only.
The easiest for Juno is probably to just add another register_nsec_ddr() for the other nsec DDR region.
Regards, Jens
...solve this issue? Right now the Juno does not use CFG_DT, and when I turn it on OP-TEE reports that it cannot find the device tree.
Thanks, Stuart
On 8/16/17 1:42 AM, Jens Wiklander wrote:
Hi Stuart,
On Tue, Aug 15, 2017 at 4:20 PM, Stuart Yoder stuart.yoder@arm.com wrote:
All,
I am testing Volodymyr's dynamic shared memory patches, which depends on the non-sec DDR support that has been added in OP-TEE recently. I am testing this on a Juno platform which has a DDR split into 2 different regions: 0x0_80000000 2G 0x8_80000000 6G
The platform_config.h allows you to define a DRAM0 base/size which then is used in the macro: register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE);
I tried defining the second DDR region in platform_config.h and a second call to register_nsec_ddr(), but that did not work.
Has anyone succeeded in having the nsec DDR split into 2 regions?
Would Jen's patch: core: assign non-sec DDR configuration from DT
No, because as you point out the DT can't be found by OP-TEE. DT is loaded later and provided to the kernel only.
The easiest for Juno is probably to just add another register_nsec_ddr() for the other nsec DDR region.
Ok, like I said, I did try that and it didn't work, so I there is something there that needs to be debugged. I get a data abort when running hello_world.
One thing that looks wrong is this message:
DEBUG: [0x0] TEE-CORE:verify_special_mem_areas:317: NSEC DDR memory [880000000 a00000000] DEBUG: [0x0] TEE-CORE:verify_special_mem_areas:317: NSEC DDR memory [80000000 fee00000]
The size of the 880000000 region is wrong.
I pasted my patch at the end of this email, in case anyone sees something obviously wrong.
Thanks, Stuart
--------------------------------------------------------------------------
diff --git a/core/arch/arm/plat-vexpress/main.c b/core/arch/arm/plat-vexpress/main.c index 8957266..d62bd57 100644 --- a/core/arch/arm/plat-vexpress/main.c +++ b/core/arch/arm/plat-vexpress/main.c @@ -51,6 +51,7 @@ #include <initcall.h>
register_nsec_ddr(DRAM0_BASE, DRAM0_SIZE); +register_nsec_ddr(DRAM1_BASE, DRAM1_SIZE);
static void main_fiq(void);
diff --git a/core/arch/arm/plat-vexpress/platform_config.h b/core/arch/arm/plat-vexpress/platform_config.h index 6589fd8..502fd22 100644 --- a/core/arch/arm/plat-vexpress/platform_config.h +++ b/core/arch/arm/plat-vexpress/platform_config.h @@ -145,6 +145,9 @@ #define DRAM0_BASE UINTPTR_C(0x80000000) #define DRAM0_SIZE (0x7F000000 - CFG_SHMEM_SIZE)
+#define DRAM1_BASE UINTPTR_C(0x880000000) +#define DRAM1_SIZE (0x180000000) +
-
Jens Wiklander -
Stuart Yoder