Hi Volodymyr,
On Thu, May 4, 2017 at 5:52 PM, Volodymyr Babchuk vlad.babchuk@gmail.com wrote:
Okay, so looks like there are some problem with MMU or MMU tables. You can define define DEBUG_XLAT_TABLE 1 on core_mmu_v7.c to take a look at the tables. They should be OK. But just to be sure... And one more question: are you sure that u-boot boots in Secure PL1 mode? Can you dump contents of SCR just to be sure?
Below is a log with DEBUG_XLAT_TABLE set to 1, seems to look ok to me.
I also printed the SCR register from op-tee and it is set to 0x0.
I also modified the code to set AW bit to 1 in SCR register, the SCR register read back 0x20 but still resulted in the hang.
DEBUG: TEE-CORE:add_phys_mem:325: CFG_SHMEM_START type NSEC_SHM 0x3e000000 size 0x00400000 DEBUG: TEE-CORE:add_phys_mem:325: CFG_TA_RAM_START type TA_RAM 0x3e500000 size 0x01b00000 DEBUG: TEE-CORE:add_phys_mem:325: CFG_TEE_RAM_START type TEE_RAM 0x3e400000 size 0x00100000 DEBUG: TEE-CORE:add_phys_mem:325: CONSOLE_UART_BASE type IO_NSEC 0xf8000000 size 0x00200000 DEBUG: TEE-CORE:add_va_space:364: type RES_VASPACE size 0x00a00000 DEBUG: TEE-CORE:add_va_space:364: type SHM_VASPACE size 0x00a00000 DEBUG: TEE-CORE:dump_mmap_table:478: type TEE_RAM va 0x3e400000..0x3e4fffff pa 0x3e400000..0x3e4fffff size 0x00100000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:478: type TA_RAM va 0x3e500000..0x3fffffff pa 0x3e500000..0x3fffffff size 0x01b00000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:478: type NSEC_SHM va 0x40000000..0x403fffff pa 0x3e000000..0x3e3fffff size 0x00400000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:478: type IO_NSEC va 0x40400000..0x405fffff pa 0xf8000000..0xf81fffff size 0x00200000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:478: type RES_VASPACE va 0x40600000..0x40ffffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:478: type SHM_VASPACE va 0x41000000..0x419fffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir) DEBUG: TEE-CORE: section map [3e400000 3e500000] MEM-RW-X-S DEBUG: TEE-CORE: section map [3e500000 40000000] MEM-RW-XN-S DEBUG: TEE-CORE: section map [40000000 40400000] MEM-RW-XN-NS DEBUG: TEE-CORE: section map [40400000 40600000] DEV-RW-XN-NS DEBUG: TEE-CORE: section map [40600000 41000000] not-mapped DEBUG: TEE-CORE: section map [41000000 41a00000] MEM-RW-XN-NS MESSAGE: TEE-CORE:print_scr:57: SCR: = 0x0 MESSAGE: TEE-CORE:ugly_trace:52: ugly trace MESSAGE: TEE-CORE:core_init_mmu_regs:830: TTBR0 = 0x3e45804a MESSAGE: TEE-CORE:core_init_mmu_regs:831: TTBR1 = 0x3e45804a MESSAGE: TEE-CORE:ugly_trace:52: ugly trace
Thanks for your continued feedback. Anything else I can check?