On Fri, May 5, 2017 at 3:21 PM, Volodymyr Babchuk vlad.babchuk@gmail.com wrote:
Hmm... Another obvious thing to check is CPSR.M. Apart of this I don't have any ideas.
Before the MMU is enabled it is: MESSAGE: TEE-CORE:print_scr:58: CPSR: = 0x600001d3
I just got a j-link debugger to work with the board. Here is a register dump when the board gets into the hung state. Looks like there is a abort, will try and dig deeper to narrow down the cause.
(gdb) mon halt target state: halted target halted in Thumb state due to debug-request, current mode: Abort cpsr: 0x600001f7 pc: 0x3e407538 MMU: enabled, D-Cache: enabled, I-Cache: enabled Data fault registers DFSR: 00001cc7, DFAR: 23fe6ed7 Instruction fault registers IFSR: 00001403, IFAR: 0779e1c9
(1890) r0 (/32): 0x800001D7 (dirty) (1891) r1 (/32): 0x00000000 (1892) r2 (/32): 0x00000AFF (1893) r3 (/32): 0x00000AFF (1894) r4 (/32): 0x00000000 (1895) r5 (/32): 0x00000000 (1896) r6 (/32): 0x00000000 (1897) r7 (/32): 0x00000000 (1898) r8 (/32): 0x00000000 (1899) r9 (/32): 0x3E45E450 (1900) r10 (/32): 0x000000DC (1901) r11 (/32): 0x3E000000 (1902) r12 (/32): 0xDFFD20D7 (1903) sp_usr (/32) (1904) lr_usr (/32) (1905) pc (/32): 0x3E407538 (1906) r8_fiq (/32) (1907) r9_fiq (/32) (1908) r10_fiq (/32) (1909) r11_fiq (/32) (1910) r12_fiq (/32) (1911) sp_fiq (/32) (1912) lr_fiq (/32) (1913) sp_irq (/32) (1914) lr_irq (/32) (1915) sp_svc (/32) (1916) lr_svc (/32) (1917) sp_abt (/32): 0x3E45ED90 (1918) lr_abt (/32): 0x3E41E259 (1919) sp_und (/32) (1920) lr_und (/32) (1921) cpsr (/32): 0x600001F7 (1922) spsr_fiq (/32) (1923) spsr_irq (/32) (1924) spsr_svc (/32) (1925) spsr_abt (/32) (1926) spsr_und (/32) (1927) sp (/32) (1928) lr (/32) (1929) sp_mon (/32) (1930) lr_mon (/32) (1931) spsr_mon (/32)
You also can check documentation on your SoC regarding TruztZone and security extensions. Maybe there are some special steps need to be taken.
Thanks, I will take a look at it.