Hi Volodymyr,
On Thu, May 4, 2017 at 4:41 PM, Volodymyr Babchuk vlad.babchuk@gmail.com wrote:
Just to be sure: does CFG_TEE_LOAD_ADDR corresponds to the real address where u-boot loads optee image?
CFG_TEE_LOAD_ADDR corresponds to the relocated address (real entry point) of optee.
//Build details: $ make PLATFORM=at91-sama5d2xult -j12 CFG_PAGEABLE_ADDR=0 CFG_NS_ENTRY_ADDR=0x22000000 CFG_DT_ADDR=0x21000000 CFG_DT=y DEBUG=y CFG_TEE_CORE_LOG_LEVEL=4 $ mkimage -A arm -O linux -C none -a 0x3E3fffe4 -e 0x3E400000 -d ./out/arm-plat-at91/core/tee.bin uTee Image Name: Created: Thu May 4 16:49:09 2017 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 223092 Bytes = 217.86 kB = 0.21 MB Load Address: 3e3fffe4 Entry Point: 3e400000
//u-boot load details fatload mmc 1:1 0x21000000 at91-sama5d2_xplained.dtb; fatload mmc 1:1 0x22000000 zImage; fatload mmc 1:1 0x23000000 uTee; bootm 0x23000000 - 0x21000000 reading at91-sama5d2_xplained.dtb 31619 bytes read in 7 ms (4.3 MiB/s) reading zImage 3680520 bytes read in 211 ms (16.6 MiB/s) reading uTee 223156 bytes read in 17 ms (12.5 MiB/s) ## Booting kernel from Legacy Image at 23000000 ... Image Name: Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 223092 Bytes = 217.9 KiB Load Address: 3e3fffe4 Entry Point: 3e400000 Verifying Checksum ... OK ## Flattened Device Tree blob at 21000000 Booting using the fdt blob at 0x21000000 Loading Kernel Image ... OK Loading Device Tree to 3db5c000, end 3db66b82 ... OK
Starting kernel ...
DEBUG: TEE-CORE:add_phys_mem:324: CFG_SHMEM_START type NSEC_SHM 0x3e000000 size 0x00400000 DEBUG: TEE-CORE:add_phys_mem:324: CFG_TA_RAM_START type TA_RAM 0x3e500000 size 0x01b00000 DEBUG: TEE-CORE:add_phys_mem:324: CFG_TEE_RAM_START type TEE_RAM 0x3e400000 size 0x00100000 DEBUG: TEE-CORE:add_phys_mem:324: CONSOLE_UART_BASE type IO_NSEC 0xf8000000 size 0x00200000 DEBUG: TEE-CORE:add_va_space:363: type RES_VASPACE size 0x00a00000 DEBUG: TEE-CORE:dump_mmap_table:476: type TEE_RAM va 0x3e400000..0x3e4fffff pa 0x3e400000..0x3e4fffff size 0x00100000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:476: type TA_RAM va 0x3e500000..0x3fffffff pa 0x3e500000..0x3fffffff size 0x01b00000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:476: type NSEC_SHM va 0x40000000..0x403fffff pa 0x3e000000..0x3e3fffff size 0x00400000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:476: type IO_NSEC va 0x40400000..0x405fffff pa 0xf8000000..0xf81fffff size 0x00200000 (pgdir) DEBUG: TEE-CORE:dump_mmap_table:476: type RES_VASPACE va 0x40600000..0x40ffffff pa 0x00000000..0x009fffff size 0x00a00000 (pgdir) MESSAGE: TEE-CORE:ugly_trace:52: ugly trace MESSAGE: TEE-CORE:core_init_mmu_regs:822: TTBR0 = 0x3e45804a MESSAGE: TEE-CORE:core_init_mmu_regs:823: TTBR1 = 0x3e45804a MESSAGE: TEE-CORE:ugly_trace:52: ugly trace
//Code #define DRAM0_BASE 0x20000000 #define DRAM0_SIZE (512 * 1024 * 1024) #define TZDRAM_BASE (DRAM0_BASE + DRAM0_SIZE - TZDRAM_SIZE) #define TZDRAM_SIZE (28 * 1024 * 1024) #define CFG_SHMEM_START (TZDRAM_BASE - CFG_SHMEM_SIZE) #define CFG_SHMEM_SIZE (4 * 1024 * 1024) #define CFG_TEE_RAM_START TZDRAM_BASE #define CFG_TEE_RAM_VA_SIZE (1024 * 1024) #define CFG_TEE_RAM_PH_SIZE CFG_TEE_RAM_VA_SIZE #ifndef CFG_TEE_LOAD_ADDR #define CFG_TEE_LOAD_ADDR CFG_TEE_RAM_START #endif #define CFG_TA_RAM_START ROUNDUP((TZDRAM_BASE + CFG_TEE_RAM_VA_SIZE), \ CORE_MMU_DEVICE_SIZE) #define CFG_TA_RAM_SIZE ROUNDDOWN((TZDRAM_SIZE - CFG_TEE_RAM_VA_SIZE), \ CORE_MMU_DEVICE_SIZE)
Also, I'm bothered by thread id (0x5f5ed35e in your case). It should be 0x0.
The weird thing is looking back at the console logs and looks like I have been getting different thread ids between reboots/builds!
//1st instance DEBUG: [0x525c875d] TEE-CORE: //2nd instance DEBUG: TEE-CORE: //3rd instance DEBUG: [0x5f5ed35e] TEE-CORE: //4th instance DEBUG: [0x2000] TEE-CORE:
Thanks for your quick response.