Hi,

While porting OP-TEE to Xilinx zynq-7000 ( 702 dev board ) I’ve hit a couple of issues which I’m hoping you might be able to help with.

Issue 1 :

If I have OP-TEE OS using both cores and core synchronisation at start-up, core 1 writes SEM_CPU_READY to sem_cpu_sync + 4, but core 0 reads 0 from sem_cpu_sync + 4.

Issue 2:

When OP-TEE OS for using only 1 core when it gets to the “rfefd sp!” in sm_smc_entry, it is not returning to the address specified in the mon_lr field of the sm_nsec_ctx structure for the core, which does match the address written to “lr” by the Xilinx FSBL before branching to OP-TEE for its initialisation.

Regards

Andy Bridges.

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