This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/gcc.
from b5562f1187d Daily bump. adds 73bc09fa8c6 middle-end/94216 fix another build_fold_addr_expr use adds f3280e4c0c9 ipa/94217 simplify offsetted address build adds c7e90196818 phiopt: Avoid -fcompare-debug bug in phiopt [PR94211] adds bb83e069eba libgomp/testsuite: ignore blank-line output for function-no [...] adds 02f7334ac93 c++: Fix up handling of captured vars in lambdas in OpenMP [...] adds f5389e17e4b Update include/plugin-api.h. adds c8429c2aba8 API extension for binutils (type of symbols). adds f22712bd8a2 Fix inliner ICE on alias with flatten attribute [PR92372] adds 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] adds b599bf9d6d1 c++: Reject changing active member of union during initiali [...] adds 98eb7b2ed24 d: Fix ICE in add_symbol_to_partition_1, at lto/lto-partiti [...] adds 837cece888f Darwin: Address translation comments (PR93694). adds dfb25dfe3d3 Darwin: Handle NULL DECL_SIZE_TYPE in machopic_select_secti [...] adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...]
No new revisions were added by this update.
Summary of changes: gcc/ChangeLog | 1620 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 7 + gcc/c-family/c-common.c | 11 +- gcc/c/ChangeLog | 14 + gcc/c/c-decl.c | 4 +- gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 2 +- gcc/cgraph.c | 90 +- gcc/cgraph.h | 17 +- gcc/cgraphunit.c | 8 + gcc/config/arm/arm-builtins.c | 86 + gcc/config/arm/arm.md | 8 +- gcc/config/arm/arm_mve.h | 8413 ++++++++-- gcc/config/arm/arm_mve_builtins.def | 61 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 1250 +- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 4 +- gcc/config/arm/vec-common.md | 42 +- gcc/config/arm/vfp.md | 7 +- gcc/config/darwin.c | 29 +- gcc/config/darwin.opt | 96 +- gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 9 +- gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 47 + gcc/cp/call.c | 4 + gcc/cp/constexpr.c | 69 +- gcc/cp/cp-gimplify.c | 30 +- gcc/cp/cp-tree.h | 1 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/cp/parser.c | 2 + gcc/d/ChangeLog | 31 + gcc/d/d-lang.cc | 52 +- gcc/d/d-tree.h | 5 + gcc/d/decl.cc | 10 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/dclass.c | 1 - gcc/d/dmd/expressionsem.c | 1 + gcc/d/dmd/module.h | 1 + gcc/d/typeinfo.cc | 47 +- gcc/d/types.cc | 48 + gcc/fold-const.c | 2 +- gcc/gimple-ssa-sprintf.c | 4 +- gcc/gimple-ssa-store-merging.c | 4 +- gcc/ipa-cp.c | 13 +- gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-inline.c | 3 + gcc/ipa-split.c | 2 +- gcc/lra-constraints.c | 24 +- gcc/lto-section-in.c | 1 + gcc/lto-streamer-out.c | 82 +- gcc/lto-streamer.h | 1 + gcc/params.opt | 4 + gcc/po/ChangeLog | 4 + gcc/po/gcc.pot | 15239 +++++++++++-------- gcc/symtab.c | 11 + gcc/testsuite/ChangeLog | 664 + gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/cpp1y/constexpr-union2.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union3.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union4.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union5.C | 15 + gcc/testsuite/g++.dg/cpp1y/pr94066-2.C | 19 + gcc/testsuite/g++.dg/cpp1y/pr94066-3.C | 16 + gcc/testsuite/g++.dg/cpp1y/pr94066.C | 18 + gcc/testsuite/g++.dg/cpp2a/constexpr-union1.C | 18 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 + gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/torture/pr94216.C | 45 + gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/g++.target/aarch64/pr94052.C | 174 + gcc/testsuite/gcc.c-torture/pr92372.c | 16 + gcc/testsuite/gcc.dg/attr-flatten-1.c | 18 + gcc/testsuite/gcc.dg/pr94211.c | 12 + gcc/testsuite/gcc.dg/tree-ssa/pr93435.c | 159 + gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 11 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 26 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 15 + .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 26 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 25 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 14 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 12 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 12 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 23 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 22 + .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 16 + .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 5 +- .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 23 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 16 + .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 29 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + gcc/testsuite/gdc.dg/fileimports/pr93038.txt | 1 + gcc/testsuite/gdc.dg/pr93038.d | 8 + .../gdc.test/compilable/imports/pr9471a.d | 2 + .../gdc.test/compilable/imports/pr9471b.d | 5 + .../gdc.test/compilable/imports/pr9471c.d | 18 + .../gdc.test/compilable/imports/pr9471d.d | 1 + gcc/testsuite/gdc.test/compilable/pr9471.d | 6 + gcc/testsuite/gdc.test/runnable/traits.d | 4 +- gcc/tree-sra.c | 37 +- gcc/tree-ssa-phiopt.c | 10 +- gcc/tree-vect-slp.c | 4 +- include/ChangeLog | 19 + include/lto-symtab.h | 13 + include/plugin-api.h | 32 +- libgomp/ChangeLog | 10 + libgomp/testsuite/libgomp.c++/pr93931.C | 120 + .../libgomp.c-c++-common/function-not-offloaded.c | 1 + libstdc++-v3/ChangeLog | 17 + libstdc++-v3/include/bits/fs_path.h | 11 +- libstdc++-v3/include/experimental/bits/fs_path.h | 40 +- .../filesystem/path/generic/94242.cc} | 41 +- .../filesystem/path/generic/generic_string.cc | 32 + .../filesystem/path/generic/generic_string.cc | 46 +- lto-plugin/ChangeLog | 20 + lto-plugin/lto-plugin.c | 141 +- 653 files changed, 34278 insertions(+), 7416 deletions(-) create mode 100644 gcc/testsuite/g++.dg/abi/empty30.C create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype75.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union4.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union5.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066-2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066-3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/constexpr-union1.C create mode 100644 gcc/testsuite/g++.dg/torture/pr93347.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94202.C create mode 100644 gcc/testsuite/g++.dg/torture/pr94216.C create mode 100644 gcc/testsuite/g++.dg/tree-ssa/pr94224.C create mode 100644 gcc/testsuite/g++.target/aarch64/pr94052.C create mode 100644 gcc/testsuite/gcc.c-torture/pr92372.c create mode 100644 gcc/testsuite/gcc.dg/attr-flatten-1.c create mode 100644 gcc/testsuite/gcc.dg/pr94211.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93435.c create mode 100644 gcc/testsuite/gcc.misc-tests/gcov-pr94029.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94072.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/mve_move_gpr_to_gpr.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c create mode 100644 gcc/testsuite/gdc.dg/fileimports/pr93038.txt create mode 100644 gcc/testsuite/gdc.dg/pr93038.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471a.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471b.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471c.d create mode 100644 gcc/testsuite/gdc.test/compilable/imports/pr9471d.d create mode 100644 gcc/testsuite/gdc.test/compilable/pr9471.d create mode 100644 libgomp/testsuite/libgomp.c++/pr93931.C copy libstdc++-v3/testsuite/{experimental/filesystem/path/generic/generic_string.c [...]