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from 601a412ef0f RISC-V: Remove the redundant expressions in the and<mode>3. new ad0518d97cf RISC-V: Recognized zihintntl extensions

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Summary of changes: gcc/common/config/riscv/riscv-common.cc | 4 ++++ gcc/config/riscv/riscv-opts.h | 2 ++ gcc/testsuite/gcc.target/riscv/arch-22.c | 5 +++++ .../gcc.target/riscv/{predef-10.c => predef-28.c} | 20 ++++++++++++-------- 4 files changed, 23 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/arch-22.c copy gcc/testsuite/gcc.target/riscv/{predef-10.c => predef-28.c} (53%)