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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allmodconfig in repository toolchain/ci/llvm-project.

from 5e23f428203 AMDGPU: Avoid custom predicates for stores with glue adds 3a3c58f0459 [InstCombine] Fix copy/paste mistake in the test cases I ad [...] adds 34da8dfba08 Revert r366610 and r366612: Expand pseudo-components before [...] adds 7b5a54e3690 [AMDGPU] Fixed occupancy calculation for gfx10 adds f4038e75d20 Disallow most calling convention attributes on PS4 adds 407e8375402 Revert "Fix asan infinite loop on undefined symbol" adds 05d9e6a2a3d [AMDGPU] Autogenerate register sequences in tuples adds a29002e59b5 [NFC] Remove unused variable adds f3bfb85bcea AMDGPU/GlobalISel: Legalize GEP for other 32-bit address spaces adds 578e8fa8337 Re-commit: r366610 and r366612: Expand pseudo-components be [...] adds 604f802fd30 [LTO] Always mark regular LTO units with EnableSplitLTOUnit=1 adds 5204f7611f4 [WebAssembly] Compute and export TLS block alignment adds 41affad967d [GlobalISel][AArch64] Contract trivial same-size cross-bank [...] adds 3bef014e7d7 Implement P1301R4, which allows specifying an optional mess [...] adds 1f8aa536f39 [cxx_status] Update status page for WG21 Cologne meeting motions. adds 1358af27c09 We support P1301R4 in C++2a as of r366626. adds 7017a6d3a3f Mark P1301R4 in C++2a as being SVN instead. adds 6a382050391 [c++20] P1161R3: a[b,c] is deprecated. adds fc0d766511e [CMake] Align debugserver with lldb-server on Darwin adds cbd28cd05bb Fix asan infinite loop on undefined symbol adds 0a7faa4e3d9 [Local] Zap blockaddress without users in ConstantFoldTerminator. adds 7a3d4c15a7f Revert "Fix asan infinite loop on undefined symbol" adds 12b48b16074 Fix cppcheck reduce scope variable warnings. NFCI adds adec0f22524 [X86][SSE] Use PSADBW to improve vXi8 sum reduction (PR42674) adds cd9b19484b6 [Codegen][SelectionDAG] X u% C == 0 fold: non-splat vector [...] adds a30a4a35ecb Fix asan infinite loop on undefined symbol adds e97f2f33e75 build: allow the user to specify `llvm-tblgen` adds 7f0c23576f5 [NFC][Codegen][X86][AArch64] Add "(x s% C) == 0" tests

No new revisions were added by this update.

Summary of changes: clang/include/clang/Basic/Attr.td | 3 +- clang/include/clang/Basic/AttrDocs.td | 7 + clang/include/clang/Basic/BuiltinsWebAssembly.def | 1 + clang/include/clang/Basic/DiagnosticGroups.td | 2 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 9 + clang/include/clang/Basic/TargetInfo.h | 1 + clang/lib/Basic/Targets/OSTargets.h | 4 + clang/lib/CodeGen/BackendUtil.cpp | 2 +- clang/lib/CodeGen/CGBuiltin.cpp | 5 + clang/lib/CodeGen/TargetInfo.cpp | 2 +- clang/lib/Sema/SemaDecl.cpp | 6 +- clang/lib/Sema/SemaDeclAttr.cpp | 33 +- clang/lib/Sema/SemaExpr.cpp | 9 + clang/lib/Sema/SemaStmt.cpp | 15 +- .../CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p1.cpp | 4 +- .../CXX/dcl.dcl/dcl.attr/dcl.attr.nodiscard/p2.cpp | 34 +- clang/test/CodeGen/builtins-wasm.c | 6 + clang/test/CodeGen/split-lto-unit.c | 12 + clang/test/Preprocessor/has_attribute.cpp | 2 +- clang/test/Sema/c2x-nodiscard.c | 6 +- clang/test/Sema/no_callconv.cpp | 44 + clang/test/SemaCXX/cxx11-attr-print.cpp | 8 +- clang/test/SemaCXX/deprecated.cpp | 26 + .../RecursiveASTVisitorTests/LambdaExpr.cpp | 2 + clang/www/cxx_status.html | 111 +- .../test/asan/TestCases/Linux/dlopen-mixed-c-cxx.c | 5 +- lld/test/wasm/{tls.ll => tls-align.ll} | 54 +- lld/test/wasm/tls.ll | 27 + lld/wasm/Driver.cpp | 31 +- lld/wasm/Symbols.cpp | 1 + lld/wasm/Symbols.h | 4 + lld/wasm/Writer.cpp | 3 + lldb/cmake/modules/LLDBConfig.cmake | 10 +- lldb/cmake/modules/LLDBStandalone.cmake | 50 +- lldb/test/CMakeLists.txt | 9 +- lldb/tools/CMakeLists.txt | 4 +- lldb/unittests/CMakeLists.txt | 2 +- lldb/unittests/tools/lldb-server/CMakeLists.txt | 2 +- llvm/cmake/modules/LLVM-Config.cmake | 7 +- llvm/include/llvm/IR/IntrinsicsWebAssembly.td | 5 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 167 +- .../Target/AArch64/AArch64InstructionSelector.cpp | 49 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 25 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 2 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 319 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 18 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 2 +- .../Target/WebAssembly/WebAssemblyISelDAGToDAG.cpp | 10 + .../Target/WebAssembly/WebAssemblyMCInstLower.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 45 +- llvm/lib/Transforms/Utils/Local.cpp | 6 + .../CodeGen/AArch64/GlobalISel/contract-store.mir | 89 + llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll | 40 + ...-vec-nonsplat.ll => srem-seteq-vec-nonsplat.ll} | 624 ++-- llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll | 157 + llvm/test/CodeGen/AArch64/srem-seteq.ll | 253 ++ .../CodeGen/AArch64/urem-seteq-vec-nonsplat.ll | 68 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir | 86 + .../CodeGen/AMDGPU/GlobalISel/legalize-gep.mir | 36 + .../AMDGPU/hsa-metadata-kernel-code-props-v3.ll | 5 +- llvm/test/CodeGen/AMDGPU/idot8s.ll | 8 +- llvm/test/CodeGen/AMDGPU/nsa-reassign.ll | 4 +- llvm/test/CodeGen/AMDGPU/regbank-reassign.mir | 12 + llvm/test/CodeGen/AMDGPU/wave32.ll | 2 +- .../CodeGen/WebAssembly/tls-general-dynamic.ll | 10 + llvm/test/CodeGen/X86/srem-seteq-optsize.ll | 85 + llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll | 3535 ++++++++++++++++++++ llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll | 586 ++++ llvm/test/CodeGen/X86/srem-seteq.ll | 420 +++ llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll | 720 +--- llvm/test/CodeGen/X86/vector-reduce-add-widen.ll | 192 +- llvm/test/CodeGen/X86/vector-reduce-add.ll | 192 +- llvm/test/Transforms/InstCombine/and-or-icmps.ll | 8 +- .../dce-cond-after-folding-terminator.ll | 5 +- 75 files changed, 6665 insertions(+), 1689 deletions(-) create mode 100644 clang/test/CodeGen/split-lto-unit.c create mode 100644 clang/test/Sema/no_callconv.cpp copy lld/test/wasm/{tls.ll => tls-align.ll} (50%) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/contract-store.mir create mode 100644 llvm/test/CodeGen/AArch64/srem-seteq-optsize.ll copy llvm/test/CodeGen/AArch64/{urem-seteq-vec-nonsplat.ll => srem-seteq-vec-nonsp [...] create mode 100644 llvm/test/CodeGen/AArch64/srem-seteq-vec-splat.ll create mode 100644 llvm/test/CodeGen/AArch64/srem-seteq.ll create mode 100644 llvm/test/CodeGen/X86/srem-seteq-optsize.ll create mode 100644 llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll create mode 100644 llvm/test/CodeGen/X86/srem-seteq-vec-splat.ll create mode 100644 llvm/test/CodeGen/X86/srem-seteq.ll