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from fb4ee0d83c5 Creating branches/google/stable and tags/google/stable/2018 [...] adds 3459520e803 [Hexagon] Update more testcases adds 04fcfb94ade [SymboleFilePDB] Put the test input back that my previous c [...] adds 2b8042c2ab1 [TargetLowering] Rename DAGCombinerInfo::isAfterLegalizeVec [...] adds e4e32bbd5b1 PrintStatistics() and PrintStatisticsJSON() should take StatLock adds 95e5d37d586 DA: remove uses of GEP, only ask SCEV adds cd508410db3 [TargetLowering] Add vector BITCAST support to SimplifyDema [...] adds c7343198cac Reapply "[DWARFv5] Emit file 0 to the line table." adds e2eaa5bc5ca [X86] Fix a typo in Host.cpp that causes us to misidentify [...] adds 7c9054610e3 [Transforms] Add missing header for InstructionCombining.cp [...] adds 611e8053e25 [DebugInfoPDB] Add DIA implementation for getSrcLineOnTypeDefn adds b86930c9098 Add early exit on reassociation of 0 expression. adds 71e93dfc4b9 [llvm-pdbdump] Add guard for null pointers and remove unused code adds 0ad2b2f8bfa [X86] Add IMUL scheduling info on sandybridge, fix it on >= [...] adds dbd628b4c75 [SystemZ] Improved debug dumping during post-RA scheduling. adds 1ab36774565 [SystemZ] NFC refactoring in SystemZHazardRecognizer. adds ff11c425c0a [SystemZ] Improve getCurrCycleIdx() in SystemZHazardRecognizer. adds 1344a1a25c9 [SystemZ] NFC refactoring in SystemZHazardRecognizer. adds 65019820f72 [ARM] Fix for PR36577 adds f0eff632cbd [LoadStoreVectorizer] Differentiate between <1 x T> and T adds e341fede2cc [mips] Correct the definition of m(f|t)c(0|2) adds 783bd6a2037 [X86][X87] Add X87 fp80 conversion tests adds d78a9f326e5 Teach CorrelatedValuePropagation to reduce the width of udi [...] adds 85acf6acb27 Revert rL326898: "Teach CorrelatedValuePropagation to reduc [...] adds b0846f97d65 Revert "Reapply "[DWARFv5] Emit file 0 to the line table."" adds 3cfa28f02fd [dwarfdump] Only print CU relative offset in verbose mode adds a446275ee2e [AMDGPU] Widened vector length for global/constant address space. adds f53ccf3b4f7 [SampleFDO] Extend SampleProfReader to handle demangled names. adds 7ada867e268 [PowerPC] LSR tunings for PowerPC adds 832984ded28 Revert "[AMDGPU] Widened vector length for global/constant [...] adds 78303097dbe Re-land: Teach CorrelatedValuePropagation to reduce the wid [...] adds 084dcd89dea [AMDGPU] Increased vector length for global/constant loads. adds 81c70f8f4d7 [LangRef] fix formatting in FP descriptions; NFC adds ef29b6a9cc9 [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned ones adds 92d52490c85 [Support] Stop passing StringRefs by const reference in som [...] adds 07657f23003 [X86] Make the MUL->VPMADDWD work before op legalization on [...] adds 59e31a6588b [PowerPC] Move test to correct location. adds df85654ae81 Teach identify_file_magic to identify PDB files. adds eb85033972b [Pipeliner] Fixed node order issue related to zero latency edges adds a896ada8ee6 Update a few switch statements to handle file_magic::pdb. adds 3c6344a9e29 Fix a bug regarding a mis-identified file type in pdbutil. adds 9f148e7de29 [X86][SSE] Regenerate float maxnum/minnum tests adds 44f97b98b66 [DebugInfo] Support DWARF expressions in eh_frame adds a86576d8771 Fix cmake's multi-config generators after r326738 adds b5e785a6cbe [X86] Remove unused function argument. NFC adds 96db657c27a [llvm-objcopy] Add support for large indexes adds 2bc4193b4d5 Revert "[llvm-objcopy] Add support for large indexes" adds 55371ce3e71 [AArch64] add missing pattern for insert_subvector undef adds 4d09eef8ec5 Revert r326932: [DebugInfo] Support DWARF expressions in eh_frame adds 6b4f6ae0915 [AArch64] Adjust the cost of integer vector division adds 9f44552ba56 [TTI] add explanatory comments for getArithmeticInstrCost; NFC adds 24e3626128a Use itaniumDemangle in llvm-symbolizer adds 7992ab8d2df [X86][SSE] LowerBUILD_VECTORAsVariablePermute - reorder per [...] adds 5aaa078baa9 Fix build broken by r326959 adds b71357f7d69 Delete code that is probably dead since r249303. adds b398d8e1fa5 [X86] Fix some isel patterns that used aligned vector load [...] adds 76ea6aab07b [AArch64] Fix UB about shift amount exceeds data bit-width adds ed6b821cce3 Reland "[DebugInfo] Support DWARF expressions in eh_frame" adds 17f0b881779 Revert "[LTO] Support filtering by hotness threshold" adds a385fd71f06 Add attributes and fix some keywords in llvm-mode.el adds 50adb3d4d1f Support resetting STATISTIC() values using llvm::ResetStatistics() adds f112c715e2d [WebAssembly] Add IntrNoReturn property to throw/rethrow in [...] adds df76a895331 [WebAssembly] Add except_ref as a first-class type adds 636e2230de9 [AMDGPU] Update AMDGOUUsage.rst descriptions adds 92758f37a54 [X86] Change X86::PMULDQ/PMULUDQ opcodes to take vXi64 type [...] adds b54703c0236 [MCSchedule] Always generate processor resource names. adds e5edcce9f5f [dsymutil] Embed toolchain in dSYM bundle adds 41b1ba97236 [DWARF] Don't attempt to parse line tables at invalid offsets adds 29b29cc6a94 [llvm-mca] LLVM Machine Code Analyzer. adds 017ddc27626 Add llvm-mca.rst to the table of contents in docs/CommandGuide. adds 828cfc4dba9 Use ellipsis ... to indicate omitted commands adds 1b572164989 [CMake] Add missing test dependency adds a3b56b24e78 [InstCombine, NewGVN] remove FP undef from tests adds a7c94b20187 [cmake] Append -Wl,-rpath-link conditionally to GNULD adds 65d5f36900e [llvm-mca] Emit the 'Instruction Info' table before the res [...] adds 0cb5f9bfc1a DWARFVerifier: Basic verification of .debug_names adds 772c9bccc0f [InstSimplify] add more tests for FP undef; NFC adds 2f86ce800e6 [InstCombine] regenerate checks; NFC adds ec47f70762b Fix unused function warning in StatisticTest.cpp adds 6b07e2fa926 [llvm-mca] Unify the API for the various views. NFCI adds b62dc36d6fe AMDGPU/GlobalISel: Pass subtarget + TM to LegalizerInfo adds f06452e21d6 [Power9] Add more missing instructions to the Power 9 scheduler adds 59dd021e4a5 [StructurizeCFG] auto-generate full checks; NFC adds 8019c4f0889 merge-request.sh: Update 6.0 metabug for 6.0.1 adds 8b2d6a01c0c [llvm-mca] HWEventListener is a class, not struct. adds 2115d9a8b77 [x86] regenerate checks; NFC adds ed2fadf0a73 [llvm-mca] add override keyword to method ResourcePressureV [...] adds 741541c9bf7 [StructurizeCFG] fix test to be independent of FP undef adds 3accb31f4aa [asan] Fix a false positive ODR violation due to LTO Consta [...] adds e3ff72b439e [x86] fix test to be independent of FP undef adds 796595e1732 Revert r327029 adds a6a4aed9471 [AMDGPU] fix test to survive the most basic undef constant folding adds a6c1ba47ac9 Expose must/may alias info in MemorySSA. adds 70dc9422419 [Tests] Remove empty test file that causes the test suite to fail adds eb1287597e9 [Hexagon] Ignore indexed loads when handling unaligned loads adds 5fff7aaccb2 [InstCombine] add min/max tests with not ops; NFC adds dc042ebfe54 [ThinLTO] Keep available_externally symbols live adds c1b100ad981 [MemorySSA] Split PtrIntPair as this fails on win/arm. adds 3c9a3ab78fc Fix test failure introduced in r327041 adds 8951246e13b [DebugInfo] Add verifier for DICompositeType vector adds 4b32c56fb3b Fix detection of COFF executable files. adds d7297a8595f Specify that test from r327041 requires asserts adds 97f847913bf [asan] Fix a false positive ODR violation due to LTO Consta [...] adds 138421ba53f [X86][AVX] Pull out variable permute creation from LowerBUI [...] adds dba96664aff Revert r327053. adds 955f6c3c872 [llvm-mca] Fix handling of zero-latency instructions. adds c29d246f516 [Support] Add WriteThroughMemoryBuffer. adds b70e54f12d2 [ConstantFold] fp_binop undef, undef --> undef adds 1a5231fa62e [DWARF v5] Support for verbose dumping of .debug_rnglist entries adds a5b92985863 Fix signed-unsigned comparison warning. adds 89d004c6420 [asan] Fix a false positive ODR violation due to LTO Consta [...] adds 832535f453f Fix compilation failure with MSVC. adds 2082160f33b [NFC] Factor out a helper function for checking if a block [...] adds 74ff3cc8bd5 [AMDGPU] fix test to survive more FP undef constant folding adds 767ba55eb3b [DebugInfo] Move RangeListEntries instead of copying. adds 46130075815 [TargetLowering] Remove redundant if condition in SimplifyS [...] adds c9edd422c97 [Support] Pacify -Wsign-compare in unit test. adds dc22e43bc70 [Reassociate] fix test to be independent of FP undef adds 0c6f09c16f4 [DebugInfo] Add DW_AT_byte_size to vectors adds 183b2d4615a [DWARF] Fix mixing assembler -g with DWARF .file directives. adds 0e9471b4533 For llvm-objdump and Mach-O files, update the printing of s [...] adds 51ed40093dd Propagate flags to SDValue in SplitVecOp_VECREDUCE adds 4fc3c08f880 utils: add a helper class to lit for captured substitutions adds 0434996945f Revert "[DWARF] Fix mixing assembler -g with DWARF .file di [...] adds de81a7e9826 Fix header comment on SHA1 code. adds ac41ddd33c1 LowerDbgDeclare: ignore dbg.declares for allocas with volat [...] adds 00f8cf90647 [X86] Remove SRAs from v16i8 multiply lowering on sse2 targets adds df5e1e0e8bf Revert "[ThinLTO] Keep available_externally symbols live" adds 4826b282dad Attempt to fix vecreduce-propagate-sd-flags.ll test. adds 9e6c29a2f00 Don't treat .symver as a regular alias definition. adds eb6bf931728 [X86] Remove duplicate isel pattern. NFC adds c88f3543c01 [AMDGPU] Fixed V_DIV_FIXUP_F16 selection on GFX9 adds ed70dc4de2b [AArch64] Fix use of a regex in the win-alloca.ll test. NFC. adds 01d72e5767f [Support] Move syntax highlighting into support adds 2e97c7a391e [LV] Fix vectorizer's isUniform() abuse triggers assert in SCEV adds 2cf5f8ca1d4 [DebugInfo/AccelTable] Fix inconsistency in getDIEOffset im [...] adds a2472dbf170 TableGen: add !isa operation adds e08484073d2 TableGen: More helpful error messages adds 691987fdfaf TableGen: Remove unused ParseForeachMode adds ad64c889918 TableGen: Allow arbitrary list values as ranges of foreach adds d66fa2a6706 TableGen: Add a defset statement adds 163bd8a42df [llvm-mca] Run clang-format on the source code. NFC adds 7ebbb195b1b [llvm-mca] Move the logic that prints the summary into its [...] adds f5ac31606c2 [x86][aarch64] ask the backend whether it has a vector blen [...] adds 5dd777c5de5 CMake: Make libxml2 show up in --system-libs (PR36660) adds beee6ae8b95 [dsymutil] Unify error handling and add color adds 8fca4625124 [LangRef] make it clear that FP instructions do not have si [...] adds 1e09c89fe4c Try to fix Windows bot by forcing "rm". adds 3cbc0a3be5d [X86][SSE] createVariablePermute - move index vector canoni [...] adds c8a7beb4856 Tidyup comment that was destroyed by clang-format. NFCI. adds 599fd01a39c Revert "[PowerPC] Move test to correct location." adds 6b6fa08ba70 Revert "[PowerPC] LSR tunings for PowerPC" adds 815d73b1d6e [InstSimplify] fix FP infinite hex constant values in tests; NFC adds 44818a31b75 [WebAssembly] Disallow weak undefined globals in the object format adds 21de18a5cc6 [AMDGPU] fix test to be independent of FP undef adds aecc972c199 Move generic test to the Generic directory adds 4adc4526ec1 [JumpThreading] Don't restrict cast-traversal to i1 adds bf0554faf15 [GISel]: Add helpers for easy building G_FCONSTANT along wi [...] adds 2006e6286bd [AMDGPU] Supported ds_read_b128 generation; Widened vector [...] adds 5da34644012 [LV] Adding test for r327109 adds f3ad8d561c8 [X86][SSE] createVariablePermute - move source vector canon [...] adds 9ae21b397da TableGen: Remove space at EOL in TGLexer.{h,cpp} adds c805ab08151 [X86][AVX] createVariablePermute - fix v2i64/v2f64 VPERMILP [...] adds 6f0333acc17 Delay creating an alias for @@@. adds fd10033f581 Avoid creating a Constant for each value in a ConstantDataS [...] adds 68d73644cd5 Use branch funnels for virtual calls when retpoline mitigat [...] adds 67fe7958c82 [llvm-objdump] Support disassembling by symbol name adds 493154d6d00 Make early exit hasPredecessorHelper return true. NFCI. adds 0f0ed7bf931 [DAG] Enforce stricter NodeId invariant during Instruction [...] adds 8fc6a5e5d1c Improve Dependency analysis when doing multi-node Instructi [...] adds c2d2d1a3f1a Correct load-op-store cycle detection analysis adds 658734384f5 [NFC] Consolidate six getPointerOperand() utility functions [...] adds 7902c08bca9 [Power9] Code Cleaup and adding Comments for Power 9 Scheduler adds f26984a632e [Debug] Retain both sets of debug intrinsics in HoistThenEl [...] adds 6165a776d1a Revert "[Debug] Retain both sets of debug intrinsics in Hoi [...] adds 346e47066fe [TargetLowering] Remove redundant term in two ifs in Simpli [...] adds c81ea862200 ADT: Make MapVector::value_type and MapVector::size_type pu [...] adds ac0df5fe842 [WebAssembly] Add EVT::getEVTString() for except_ref type adds 2fb0fe6cdbf [TwoAddressInstructionPass] Improve tryInstructionCommute o [...] adds 87407bd5762 Revert: r327172 "Correct load-op-store cycle detection anal [...] adds 824eedb9eb4 Go back to sometimes assuming intristics are local. adds 11ddcbc5725 Clean up a temp file on the buildbots. adds 4d617521270 [X86] Rewrite printMasking code in X86InstComments to use T [...] adds 197b6c81959 [AliasAnalysis] Shrink AliasResults; NFC adds 9c2329d170f [X86] Move the AC_EVEX_2_VEX AsmComments enum to X86InstrIn [...] adds 2e7a52adbad [WebAssembly] Object: Add accessor for wasm symbols adds 7ca2a477857 [X86] Add a missing EVEX instruction to EmitAnyX86InstComments. adds 8c9cc1f5e67 [PartialInlining] Use isInlineViable to detect constructs p [...] adds fc21165c231 [ConstantFold] fp_binop AnyConstant, undef --> NaN adds 5c56853ab70 AMDGPU: Fix crash when constant folding with physreg operand adds f8a45a4d4ab [PowerPC] fix tests to be independent of FP undef adds 00cb8ab9267 [AMDGPU] fix tests to be independent of FP undef adds 253ee8cecfe [InstSimplify] fp_binop X, undef --> NaN adds 8da142da077 [X86][XOP] createVariablePermute - use VPPERM for v32i8 var [...] adds 80f8cd5c841 [llvm-mca] Views are now independent from resource masks. NFCI adds bd2985da0d1 [llvm-mca] BackendStatistics: early exit from method printS [...] adds fae96e03f7d [X86][SSE] createVariablePermute - create index scaling hel [...] adds c28fd904800 [X86][XOP] createVariablePermute - use VPPERM for v16i16 va [...] adds d4f6324d82d [ADT] Shuffle containers before sorting to uncover non-dete [...] adds c8b2a4c11ad [AArch64] Implement native TLS for Windows adds b4b3cc544d1 [X86][XOP] createVariablePermute - use VPERMIL2 for v8i32/v [...] adds 50cc6006023 [llvm-mca] Fix use-of-uninitialized-value error reported by [...] adds 9d122e2d977 [X86] Add comments to the end of FMA3 instructions to make [...] adds ac38a557160 Revert r327199: "Clean up a temp file on the buildbots" adds a41ced4260a [TargetSchedule] Minor refactor in computeInstrLatency. NFC adds 60a5e731799 Add REQUIRES: arm-registered-target to test using an arm-ap [...] adds aa85acb15c0 Test commit - change comment slightly. adds 71d757ba1f7 [MemorySSA] Fix comment + remove redundant dyn_casts; NFC adds ccddf0fbd5f [x86][SSE] Add widenSubVector helper. NFCI. adds 7e6bfebf859 [X86][AVX512] createVariablePermute - Non-VLX targets can w [...] adds 78049a406dc [X86][AVX] createVariablePermute - use 2xVPERMIL+PCMPGT+SEL [...] adds fa5f307cd33 [X86][SSE] Generalized SplitBinaryOpsAndApply to SplitOpsAn [...] adds faa03756ee0 Fix for buildbots which didn't like makeArrayRef with initi [...] adds 8259353e43b [X86][AVX] createVariablePermute - use PSHUFB+PCMPGT+SELECT [...] adds 7f617622f31 [InstCombine] add tests for casted sign-bit cmp (PR36682); NFC adds 9139e91192d [X86][AVX] createVariablePermute - widen permutes for cases [...] adds f86876ec491 [X86][AVX] createVariablePermute - scale v16i16 variable pe [...] adds 1635c635cc5 [X86][AVX512] Added more non-VLX test cases adds 3c0783d9757 [X86][MMX] Support MMX build vectors to avoid SSE usage (PR29222) adds e6bdfcf63a0 [CGP] Fix the remove of matched phis in complex addressing mode adds 1c193f4abb7 [X86] Don't compute known bits twice for the same SDValue i [...] adds bd99a1f1df9 Back out "Re-land: Teach CorrelatedValuePropagation to redu [...] adds d7e41ba27b9 [ThinLTO] Recommit of import global variables adds 68642e9a892 Fix compilation on Darwin with expensive checks. adds 3d53cc7b752 [X86][SSE] createVariablePermute - PSHUFB requires SSSE3 no [...] adds a722fa24b2f MC intel asm parser: Allow @ at the start of function names. adds 59a0caa4c55 [mips] Split out ASEPredicate from InsnPredicates (NFC) adds 2ee3b171474 Revert r326710 "Fuzzer: remove temporary files after we're [...] adds b3834e5d6b5 AMDGPU/GlobalISel: Make some G_MERGE_VALUEs legal adds e0eff38b22d AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUES adds 7f9dbc4419d AMDGPU/GlobalISel: Legality and RegBankInfo for G_{INSERT|E [...] adds c9946711cef [Hexagon] Add more lit tests adds c9f7443e501 [Hexagon] fix 'must explicitly initialize the const member' [...] adds 78a4389abbb [DebugInfo] Replace unreachable with None adds 9e2cb4287db Updating MIR Language Reference to include new syntax for s [...] adds d2ac73c164a [llvm-readobj] Make header self-contained adds a70206a47a3 [AMDGPU][MC] Corrected GATHER4 opcodes adds eb98f9d1846 [Hexagon] Add REQUIRES: asserts to testcases that use -debug-only adds 3af14155da5 [Hexagon] Add REQUIRES: asserts to testcases that use -stats adds b2adf42c525 [X86][Btver2] Use JWriteResFpuPair wrapper for AES/CLMUL/HA [...] adds 538055ab894 [InstSimplify] add test for m_NegZero with undef elt; NFC adds 1eaf2d7b5ac [AMDGPU][MC][DOC] Updated AMD GPU assembler description adds 2744a56d797 [X86][Btver2] Extend JWriteResFpuPair to accept resource/uo [...] adds d4b84fce523 [AMDGPU] Fix lowering enqueue kernel when kernel has no name adds 47684f7cb03 [X86] Remove use of MVT class from the ShuffleDecode library. adds 850d35ab15b [X86][Btver2] Prefix all scheduler defs. NFCI. adds 0e3e44d0442 [X86] Add all of the MRM_C0-MRM_FF forms to the switch in R [...] adds db98ce74198 [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction adds 62f3cb723c6 [X86] Deleting README-MMX.txt now that all tasks have been [...] adds 7870dc6ea1a [InstCombine] [NFC] Add tests for peeking through FP casts [...] adds f865ef62e54 [Hexagon] Subtarget feature to emit one instruction per packet adds 475569518b9 [SelectionDAG] Improve handling of dangling debug info adds 78c10b0e5a8 update_mir_test_checks: Fix handling of IR input after r326284 adds 381750391ce [X86][Btver2] FSqrt/FDiv reg-reg instructions don't use the AGU. adds f4eb10a0cb9 [PatternMatch, InstSimplify] allow undef elements when matc [...] adds 8921acb5dbb [Hexagon] Counting leading/trailing bits is cheap adds a3f44daec10 [Hexagon] Fix typo in testcase adds 584d88ccc77 [NFC] PrintHelp cleanup adds 9b2441e49b7 [NFC] Replace iterators in PrintHelp with range-based for adds 5ef6ff69583 [CallSiteSplitting] Use !Instruction::use_empty instead of [...] adds c4689888d64 [InstCombine] Replace calls to getNumUses with hasNUses or [...] adds e9c83048fbc [AArch64] Fold adds with tprel_lo12_nc and secrel_lo12 into [...] adds de8d3a7d94a [PowerPC][NFC] Explicitly state types on FP SDAG patterns i [...] adds 29680d6d4f2 [llvm-readobj][ELF] Move ELF note parsing into libObject adds 6a79fbce1b4 Improve caching scheme in ProvenanceAnalysis. adds f7b39ab9dfa Remove the LoopInstSimplify pass (-loop-instsimplify) adds c91e4c196d9 [X86][Btver2] Clean up formatting/comments in scheduler mod [...] adds a71d86999e7 [InstSimplify] add fcmp tests for constant NaN vector with [...] adds 709c2af62bb ObjCARC: teach the cloner about funclets adds ff9e3f175e1 [PatternMatch] enhance m_NaN() to ignore undef elements in vectors adds 7b396b7a54b BlockExtractor: Don’t delete functions directly adds 304352277fd [llvm-readobj] Extend the output of -elf-section-groups adds d309dec2f3e [InstCombine] add test to show fmul transform creates extra [...] adds 3270ed077cb [llvm] Fix mc tests adds ddf9edb4020 ObjCARC: address review comments from majnemer adds 66a6ddceda2 [LegalizeTypes] In SplitVecOp_TruncateHelper, use GetSplitV [...] adds d737130f0f7 [ThinLTO] Add funtions in callees metadata to CallGraphEdges adds b0d20586e98 [LTO] Return proper error object rather than null LTOModule adds 97fa4365e0a Reland r327041: [ThinLTO] Keep available_externally symbols live adds 579aaf149ed [SCEV] Fix isKnownPredicate adds 8f8572aba3b Revert [SCEV] Fix isKnownPredicate adds a26a1c77ed7 bpf: Add more check directives in peephole testcase adds c543a072f89 bpf: Tighten subregister definition check adds 83008ad9412 bpf: J*_RR should check both operands adds 5e02a7311a0 bpf: Extends zero extension elimination beyond comparison i [...] adds 0f4700096fb bpf: Support subregister definition check on PHI node adds 87576cc8b8e bpf: Don't expand BSWAP on i32, promote it adds bdea56efc22 bpf: New post-RA peephole optimization pass to eliminate ba [...] adds c9274e4c03c bpf: Enhance debug information for peephole optimization passes adds cfe9a0e9053 [MergeICmps] Make sure that the comparison only has one use. adds 4f23838f561 [SCEV][NFC] Smarter implementation of isAvailableAtLoopEntry adds e7b0e8d685f [CodeGenPrepare] Respect endianness in splitMergedValStore. adds 0cfc08d8e28 [Evaluator] Evaluate load/store with bitcast adds a4c60c4ed08 [dsymutil] Introduce LinkContext. NFC. adds 3f2bd66874a [dsymutil] Unbreak non-Darwin bots. adds 6fb020e07a9 [X86][SSE41] createVariablePermute v2X64 - PCMPEQQ can test [...] adds 54fe79a5b0d [mips] Don't create nested CALLSEQ_START..CALLSEQ_END nodes. adds 641c297f4d9 [llvm-mca] Refactor event listeners to make the backend agn [...] adds 9f5a1878692 [llvm-mca] Fix unused variable warning in opt mode. adds 6ebd13d4d17 [TTI] Fix a typo in the comment adds 7411a597460 [llvm-mca] Use a const ArrayRef in a few places. NFC adds 10ee99b9adb [CodeView] Omit forward references for unnamed structs and unions adds e8dc98337bf [SROA] Take advantage of separate alignments for memcpy sou [...] adds b9365200525 [dsymutil] Perform analyzeContextInfo and CloneDIEs in parallel adds 10e112323e4 [dsymutil] Remove old error/warn functions. NFC. adds e17ca0d378c [mips] Fix the definitions of the EVA instructions adds 68ba6f10e9d [InstCombine] fix fmul reassociation to avoid creating an e [...] adds fe3b1d26874 [MC] Move the instruction latency computation from TargetSc [...] adds 201fb78eddb [X86][Btver2] Split i8/i16/i32/i64 div/idiv costs adds 8ed6693f03d [ThinLTO] Clear dllimport when setting dso_local. adds 49c5e696fd6 [mips] Guard traps for microMIPS correctly adds cc46e391a28 [dsymutil] Unify error handling outside DwarfLinker. adds 341f4b576d1 test commit: fix formatting of a comment This is a simple [...] adds a1604a6d987 Revert r327397 [CodeView] Omit forward references for unnam [...] adds 604cc1c6899 [llvm-mca] Simplify code that computes the latency of an in [...] adds 37d11b4d9bf [X86] Remove SplitBinaryOpsAndApply and use SplitOpsAndAppl [...] adds 0718cccb582 [MC] Move the reciprocal throughput computation from Target [...] adds 86dce8fdeab [SelectionDAGBuilder] Replace deprecated calls to MemoryInt [...] adds d4198762192 [lit] - Allow 1 test to report multiple micro-test results [...] adds 3ca92f8e9ed Build system changes for RISCV adds 38ac5997de8 [DAGCombine] visitREM - Don't assume that one divrem isn't [...] adds 04be4f58790 [llvm-mca] Remove the logic that computes the reciprocal th [...] adds 14d8d03fe25 Revert "[mips] Guard traps for microMIPS correctly" adds 3eda0067794 [PDB] Support dumping injected sources via the DIA reader. adds 23862c8b358 [MC] fix documentation comments; NFC adds d3a30bc6f18 Handle mixed-OS paths in DWARF reader adds 02a171a38c3 Implement pure virtual method to fix build. adds b2e9134e8c5 [LazyValueInfo] PR33357 prevent infinite recursion on Binar [...] adds 5edc5fb7cf0 [SLP] clean some formats adds 0b6e4ebf673 [x86] add test for WriteZero sched class instructions; NFC adds e4f0193bed3 Test Commit NFC. Updated comment adds 0d729fa5d6a Temporary disable debuglineinfo-path.ll to fix build adds 12d5807d036 [MIR] Allow frame-setup and frame-destroy on the same instruction adds 29c097d5441 Fix debuglineinfo-path.ll adds fc9466dd054 Update modulemap to exclude new DIA headers. adds 0d74daca01d [DAGCombiner] Allow visitEXTRACT_SUBVECTOR to combine with [...] adds 3640be3663d Remove explicit triple and data layout from the test adds b80dd9b5698 Simplify more cases of logical ops of masked icmps. adds 737a344b6fd Disable PDB injected sources test temporarily. adds 597af6522ca [X86] Rewrite LowerAVXCONCAT_VECTORS similar to how we hand [...] adds 0ae4561211a [X86] Simplify the LowerAVXCONCAT_VECTORS code a little by [...] adds 6b4846ae8fe Disable optimizations in debuglineinfo-path test adds a3a491bfb16 [LTO/gold] Support --wrap adds 39745f957e2 [GISel]: Fix incorrect type used in Pattern Match for ICst adds 583a2b4786c [X86] Re-generate test to get proper capitalization of its [...] adds 8f15c882eb7 Revert "[LTO/gold] Support --wrap" adds ef25e23f6f1 Add extra output/check to debug clang-ppc64be-linux test failure adds 6f1d6423b3a TargetMachine: Add address space to getPointerSize adds edc3de56875 grep for global functions only adds 144840375f2 Disable test debuglineinfo-path on powerpc adds a4b7c02dd57 [ORC] Add a 'lookup' convenience function for finding symbo [...] adds 50f412d3251 [ORC] Silence a compiler error. adds dda1921ef42 [ExecutionEngine] Add a getSymbolTable method to RuntimeDyld. adds 58ecc853fca [ORC] Fix a data race in the lookup function. adds e8aa86b340b [RuntimeDyld] Silence a compiler error. adds df7c2a2c93e [LLVM-C] Redo unnamed_address attribute bindings adds 5b80a6538b6 [GlobalIsel][X86] Support for G_ZEXT instruction adds 4d613a84ce2 Export LLVM_DYLIB_COMPONENTS in LLVMConfig.cmake adds 21cda30c180 [dsymutil] Print architecture in warning adds fa49d7da448 DWARF: Unify form size handling code adds 738ee045416 [AMDGPU] Fix for DAGCombiner infinite loop in OCLtst adds 231876457fe TableGen: Add !dag function for construction adds 14236ebc9ca TableGen: Allow ? in lists adds 8ed1fd468ae TableGen: Type-check BinOps adds 79175dbbae0 TableGen: Allow dag operators to be resolved late adds af0de5073c2 TableGen: Add !ne, !le, !lt, !ge, and !gt comparisons adds 3e7114a4b6f TableGen: Explicitly forbid some nestings of class, multicl [...] adds 9357220c93d Explicitly initialize dwarf::FormParams in DIEInteger::SizeOf adds 5b113a2c3b0 [GlobalISel][X86] Support G_LSHR/G_ASHR/G_SHL adds 9bb5a07f68d Fix msvc compiler error in r327498 adds 2d21c59fcf0 Fix 'not all control paths return a value' MSVC warning. NFCI. adds fd89485e3cb [AArch64] Don't produce R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC adds 7c95150df80 [X86][SSE] Use WriteFShuffleLd for MOVDDUP/MOVSHDUP/MOVSLDU [...] adds ead876539dc [LTO/gold] Support --wrap adds 64c4f712b2d [LTO/gold] Fix workaround for old plugin-api.h in --wrap support adds c2b0f90df1f [X86][Btver2] Fix YMM shuffle, permute and permutevar sched [...] adds cad9f50df38 [mips] Add support for CRC ASE adds 2a50eccea8b [llvm-mca] Move the logic that updates the register files f [...] adds ce305b30126 [llvm-mca] Remove unused variable from InstrBuilder.cpp. NFC adds a816f42e4da [CodeGen] allow printing of zero latency in sched comments adds 47473109e3c [GlobalIsel][X86] Support for G_SDIV instruction adds 1fd0177abc0 SjLjEHPrepare: Don't reg-to-mem swifterror values adds dc84b5c40c7 [WebAssembly] Identify COMDATs by index rather than string. NFC adds d1498c372ae [X86][AVX] Use WriteFShuffleLd for broadcast reg-mem instructions adds c2f88d9b7ef [WebAssembly] Add DenseMap traits and operator== for Wasm t [...] adds 3a48b7c274c [X86] Teach X86TargetLowering::targetShrinkDemandedConstant [...] adds b34a8c964f3 [AArch64] Keep track of MIFlags in the LoadStoreOptimizer adds db67ae0928a [InstCombine] [NFC] Add tests for peeking through unsigned [...] adds f446c68a19a [InstSimplify] [NFC] Add tests for peeking through unsigned [...] adds 9c2e5e4f785 Fix LLVM IR check lines in utils/update_cc_test_checks.py adds 2671f80b2d1 [X86] Add back fast-isel code for handling i8 shifts. adds 6f801c6c330 [InstSimplify] [NFC] cast-unsigned-icmp-cmp-0.ll - don't ru [...] adds 862ea57eb62 [LLVM-C] [bindings/go] Add C and Golang bindings for COMDAT adds a38a41d83f7 [InstSimplify] regenerate checks; NFC adds 0f6b1bf2e5e [InstSimplify] add tests to show missing/broken fadd folds [...] adds 9232972575c [MC] Always emit relocations for same-section function references adds b18de8bdc3c [UpdateTestChecks] Handle IR variables with a '-' in the name adds 96ae7f89109 [ORC] Switch from shared_ptr to unique_ptr for addModule methods. adds d31cc5d410e [AArch64] Emit CSR loads in the same order as stores adds 8f10645fe18 [X86] Add haswell testing for PR35635 as well. adds 2a44ab0eda7 [InstSimplify] fix folds for (0.0 - X) + X --> 0 (PR27151) adds d1e7e3c8a89 Revert "[ORC] Switch from shared_ptr to unique_ptr for addM [...] adds ea8353074c9 [EarlyCSE] Exploit open ended invariant.start scopes adds 0d758f3663c [CodeGen] Use MIR syntax for MachineMemOperand printing adds 4d4a317f80f [FastISel] Sink local value materializations to first use adds 91c8f6f87b8 [X86][Btver2] Add ResourceCycles and NumMicroOps overrides [...] adds b30a83dec38 [AMDGPU] Waitcnt pass: Modify the waitcnt pass to propagate [...] adds e4c28b17afd [InstSimplify] add tests for frem and vectors with undef; NFC adds d31d6f8a4da [X86][Btver2] Add support for multiple pipelines stages for [...] adds 54cff77be9a [CleanUp] Remove NumInstructions field from LoopVectorizer' [...] adds 6531c3164cb [ORC] Re-apply r327566 with a fix for test-global-ctors.ll. adds 1b59d4be44b Remove unused variable; NFC adds f1067c00662 [PowerPC][NFC] formatting-only fix adds fd5ed2e166f [DebugInfo] Add a new method IPDBSession::findLineNumbersBy [...] adds 31970347f11 [X86] Use MVT in a couple places where we know the type is legal. adds fb970f28250 [X86] Remove old TODO. We have coverage for this now. adds cc5be0160c9 [X86] Add support for matching FMSUBADD from build_vector. adds a2e859907e1 [X86] Add test cases for 512-bit addsub from build_vector. adds cfb3cd346a7 [SCEV][NFC] Remove TBB, FBB parameters from exit limit comp [...] adds 0e27effab39 [LoopUnroll] Ignore ephemeral values when checking full unr [...] adds 116f1ad7f69 [New PM][IRCE] port of Inductive Range Check Elimination pa [...] adds bb3e2694e91 [CodeView] Initial support for emitting S_BLOCK32 symbols f [...] adds 170747ec42d [Debug] Retain both copies of debug intrinsics in HoistThen [...] adds 94b082e3cc6 [AArch64] Codegen tests for the Armv8.2-A FP16 intrinsics adds 175ecc97981 [InstSimplify] remove 'nsz' requirement for frem 0, X adds e2ee2c948f5 [PatternMatch, InstSimplify] allow undef elements when matc [...] adds dc55b3ba688 [X86] Regenerate schedule tests with zero latency comments adds e7dd436d902 [X86][SSE] Introduce Float/Vector WriteMove, WriteLoad and [...] adds 353be84b744 [InstSimplify] add tests with NaN operand for fp binops; NFC adds 258a13c8f29 [X86][Btver2] Remove JAny resource, and map system/microcod [...] adds ffb3337b41a [PowerPC] Optimize TLS initial-exec sequence to use X-Form [...] adds 828ff3b7ed5 [ConstantFolding, InstSimplify] Handle more vector GEPs adds 8b845d3c43b [llvm-mca] Simplify code. NFC. adds d2827a5a712 [InstSimplify][NFC] simplifyICmpWithConstant(): refactor Ge [...] adds 73e0892707f [InstSimplify] peek through unsigned FP casts for sign-bit [...] adds 457b8b54363 [EarlyCSE] Reuse invariant scopes for invariant load adds 1ae46a07efa Refactor the PDB HashTable class. adds d8d0bbd266f [X86] Fix 80 column violations. adds e9d01827a3b [X86] Simplify the type legality checking for (FM)ADDSUB/SU [...] adds a2c49110903 [X86][Btver2] Attach AES/CLMUL instructions to a scheduler pipe adds 03d35ec16ac [PPC] Avoid non-simple MVT in STBRX optimization adds 0d2e162af58 Add missing #includes. adds a60f94fa6bd Move some function declarations higher so they can be found. adds 74711af0968 [EarlyCSE] Don't hide earler invariant.scopes adds ed3ec2499c1 [LV] Test commit. Removing white space. adds 319ecd75bd3 Revert r327620 "[CodeView] Initial support for emitting S_B [...] adds de41255531c Remove empty file adds f2188eee623 [X86] Add test case showing bad fmsubadd creation due to ba [...] adds a3e0d356f4d [X86] Make sure we use FSUB instruction as the reference fo [...] adds 315ff22c81e [AArch64] Adjust the cost model for Exynos M3 adds 41bcd469df0 [AArch64] Adjust the cost model for Exynos M3 adds 911ca90266c [AArch64] Adjust the cost model for Exynos M3 adds 7a956b6e4d7 [LICM] Ignore exits provably not taken on first iteration w [...] adds 44bbb4a2f37 [codeview] Delete FunctionInfo copy ctor and move out of DenseMap adds 585f63458fb Fix structure alignment issue. adds 80c83143318 [codeview] Fix sense of the assertion about hashtable insertion adds 58e2c599eb3 Re-land r327620 "[CodeView] Initial support for emitting S_ [...] adds 648727d7b98 [LoopUnroll] Peel off iterations if it makes conditions tru [...] adds 6a06998de9c [NVPTX] TblGen-ized lowering of WMMA intrinsics. adds 1695e783fb4 [WebAssembly] Add DebugLoc information to WebAssembly block [...] adds 9ebec54ea6a [PDB] Fix a bug where we were serializing hash tables incorrectly. adds b914af4b4d4 [X86][Btver2] Add test to show timeline of fpu instructions [...] adds 3db0d5dc227 Fix PDB injected sources test. adds 0cd1080fe62 [InstCombine] add tests for fcmp+select -> fabs; NFC adds fd345c1c18a Use standard `print(dbgs())` pattern to implement DebugLoc::dump adds ff9bcaa73fb [X86][Btver2] Fix ymm div/sqrt to use fmul unit adds fdfe3c24c80 [SelectionDAG][ARM][X86] Teach PromoteIntRes_SETCC to do a [...] adds 92adf334440 [X86][Btver2] Tweak pipes test to remove register dependencies adds d25830eab24 [X86][Btver2] Add support for multiple pipelines stages for [...] adds d157ba2f807 [InstCombine] add more tests for fcmp+select -> fabs; NFC adds 2a1dc77e0b0 [NFC] Void variables used for asserts only adds 547e2f8dcc1 [ARM] FP16 codegen support for VSEL adds 107433d6ada [TTI, AArch64] Allow the cost model analysis to test vector [...] adds c5ad26d89b9 DWARFVerifier: Enhance validation of .debug_names hash tables adds 7f805ae9a22 HashTableTest: squelch some "comparison of integers of diff [...] adds a7fd2c3c2ac [AArch64] Implement getArithmeticReductionCost adds c96f2d40f91 [ARM] Fix a check in vmov/vmvn immediate parsing adds d957afd022c [X86][Btver2] Add correct lzcnt/tzcnt/popcnt schedule costs adds 9d52551911e [X86][Btver2] Add correct mul/imul schedule costs adds 91d396d6ecf [ARM] Convert more invalid NEON immediate loads adds 4dee5498348 [Hexagon] Fix zero-extending non-HVX bool vectors adds cd83f2d5e3c [JumpThreading] Track unreachable BBs to avoid processing adds 5dee7735ac4 [GISel]: Remove unused header include in MachineIRBuilder.h adds 2d27b2a32c7 [SystemZ] Make AnyRegBitRegClass unallocatable. adds b8633051f00 [InstCombine] add nnan requirement to potential fabs folds [...] adds 835a08c7cce [AMDGPU][MC] Corrected default values for unused SDWA operands adds 11f5adb29bf This patch fixes the invalid usage of OptSize in Machine Co [...] adds 884dc869a4f [LICM/mustexec] Extend first iteration must execute logic to fcmps adds a5e8c708f7f [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix [...] adds c1b9fa26d9c [X86] Post process the DAG after isel to remove vector move [...] adds 7c98e88dc90 [AMDGPU] Supported ds_write_b128 generation. adds c00d3a3cf5a [CorrelatedValuePropagation] Use SelectInst::getCondition/g [...] adds e983329c584 [X86] Merge ADDSUB/SUBADD detection into single methods tha [...] adds f6f2e196818 Revert r327721 "This patch fixes the invalid usage of OptSi [...] adds 025ee4f9cce [IR] Avoid the need to prefix MS C++ symbols with '\01' adds 962b1b6c197 [Hexagon] Add lit testcases for atomic intrinsics adds 62100bd95ab [Hexagon] Avoid bank conflicts in post-RA scheduler adds b1c52c6fcec [InstSimplify] add NaN constant diversity; NFC adds f38d29c48f5 [X86] Pass SelectionDAG into X86ISelAddressMode::dump and o [...] adds 447a9343fcb Quiet unused variable warnings. NFC. adds 277e3b2aec6 [llvm-mca] Remove unused methods from Backend. NFC adds 115a8a95afb [llvm-mca] Remove method getSchedModel() from the Backend. adds af5b99318de [MachineOutliner] Make KILLs invisible adds 2755819705e [GlobalsAA] Fix a pretty terrible bug that has been in Glob [...] adds eb9d4e05e65 [SelectionDAG] Handle big endian target BITCAST in compute [...] adds 42bc90e1724 [SystemZ] computeKnownBitsForTargetNode() / ComputeNumSign [...] adds 0c44305d76d [SystemZ] Add 'REQUIRES: asserts' to test case using debug [...] adds 10c992c085d [X86] Added support for nocf_check attribute for indirect B [...] adds 2901b0fdfca [bindings/go] Add a missing `,` in the test code to fix a g [...] adds 177d1142dd7 AMDGPU/GlobalISel: Basic legality for load/store adds 417485b734f AMDGPU/GlobalISel: Basic G_GEP legality adds 65181f7b753 AMDGPU/GlobalISel: Cleanup constant legality adds b3fc341d672 Fix some user facing typos adds f79c73681d8 [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172" adds f35e82f91d4 Revert "[DAG, X86] Revert r327197 "Revert r327170, r327171, [...] adds f1cadb5079b [AArch64] Skip an unnecessary getCopyToReg in DYNAMIC_STACKALLOC adds 8b968a4e3c3 [X86] Remove MMX_MASKMOVQ64 and VMASKMOVDQU from scheduler models. adds 65c850f5813 [TableGen] Move some variables into for loop declaration. NFC adds 6ef6701c93c [TableGen] Remove unnecessary uses of make_range. adds a6a110ed9ab [X86] Fix a couple typos in the Zen scheduler model. adds 270a3a483f2 [X86] Fix a bunch of overlapping regular expressions in the [...] adds a97a360d7ef [X86][Btver2] Add llvm-mca tests to show pipe resource usag [...] adds aec737a3d39 [X86][Btver2] Merge equivalent VBLENDVY + VPERMILY schedule groups adds a8b19e082c5 [dsymutil] Rename llvm-dsymutil -> dsymutil adds 118b26f0034 [X86][Btver2] Correctly distinguish between scheduling pipe [...] adds e3995b77d62 [dsymutil] Fix add_llvm_tool_symlink adds 3f5267c305c [X86][Btver2] Modelled float bitwise instructions as being [...] adds 0d3d0f5f299 [X86][Btver2] SSE4A EXTRQ/INSERTQ instructions are performe [...] adds d33d1f5f75d [X86][Btver2] Strip default latency/resource values. NFCI. adds d65aba275a9 [InstSimplify] loosen FMF for sqrt(X) * sqrt(X) --> X adds e989b120444 [InstCombine] add nnan requirement for sqrt(x) * sqrt(y) -> [...] adds 3cfd596c21d [llvm-mca] Allow the definition of multiple register files. adds 0fdbc4caef4 [InstCombine] peek through unsigned FP casts for zero-equal [...] adds 867827c0f39 [LICM] Salvage DI from dying Instructions adds 4d1a7f6f3f3 [X86][Btver2] F16C instructions are performed on the JSTC f [...] adds 8a3c14bd567 [X86][Btver2] Float bitwise ymm instructions are double pum [...] adds bc428f382a2 [X86][Btver2] FADD/FHADD ymm instructions are double pumped [...] adds f4acc066335 [X86][Btver2] Add crc32 resource tests adds 03fbd137fa2 [X86][Btver2] Fix crc32 schedule costs adds 27bdb27dad7 [TableGen] When trying to reuse a scheduler class for instr [...] adds c8f23a2d217 [SelectionDAG] Don't default the SelectionDAG* parameter to [...] adds 2c4e9afb584 [AArch64] Fix a few InstRWs in the A53 scheduler model and [...] adds 258e9b19646 [Mips] Remove duplicate lines from MipsScheduleP5600.td and [...] adds f0c8edc1fce [AVR] Lower i128 divisions to runtime library calls adds 60a8b5946af [X86] Merge 8-bit instructions into instregex with 16/32/64 [...] adds e932818cf9c [X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single r [...] adds 3e980654e85 [X86] Use IIC_CMOV64_RR/RM on 64-bit cmov instructions. adds f5ae8467a0a [X6] Remove two unused InstrItinClass adds c479e3d3f29 [X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the sch [...] adds be522c69dea [X86] Merge XADD8rr regular expression with XADD16rr/XADD32 [...] adds 4cf108a0bbb [SCEV] Re-land: Fix isKnownPredicate adds 51dcaa3a7b6 [SCEV] Factor out isKnownViaInduction. NFC. adds 9958e72cf3f [ARM] Fix warnings about missing parentheses in ARMAsmParser adds 1a2e5023b72 [MSan] Introduce insertWarningFn(). NFC adds f96dc7a4f12 [MSan] Don't create zero offsets in getShadowPtrForArgument(). NFC adds 6e6caa02ecc [MSan] fix the types of RegSaveAreaPtrPtr and OverflowArgAr [...] adds abb819e1e57 [RISCV] Peephole optimisation for load/store of global valu [...] adds 837541c2f18 HexagonISelLowering.cpp: fix 'enum in bool context' warning adds ea7c1d4e4e1 [SystemZ] Bugfix of CC liveness in emitMemMemWrapper (CLC). adds dc9a7c0c43b build_llvm_package.bat: Drop LLDB from the package. adds 2448ce21221 [llvm-mca] Add pipeline stall events. adds 5a0249de088 Stylish change. NFC adds e9c814d4ae5 [ARM] Support for v4f16 and v8f16 vectors adds cae812cc14b [MergeICmps] Re-land 324317 "Enable the MergeICmps Pass by [...] adds 1df3767b190 [NFC] Fix minor typos in comments adds fe576409831 AMDGPU: Don't leave dead illegal VGPR->SGPR copies adds 41fae9f61aa AMDGPU/GlobalISel: RegBankSelect for basic int ops adds ce04a4a4e7a TableGen: Remove the cast-from-string-to-variable-reference [...] adds b50f5594c5c TableGen: Move GenStrConcat to a helper function in BinOpInit adds a1c1c2357cf TableGen: Remove OpInit::Fold adds e0e26550486 TableGen: Only fold when some operand made resolve progress adds 0715b9ec565 TableGen: Explicitly test some cases of self-references and [...] adds c9cc57b52dc TableGen: Check the dynamic type of !cast<Rec>(string) adds 6bd41dfa71d TableGen: Explicitly forbid self-references to field members adds c27b35793b1 Changed createTemporaryFile without FD to actually create a file. adds 3cf01d23dd1 [x86] put nops into the WriteNop class and customize for Jaguar adds e9aabdfb389 [X86] Generalize schedule classes to support multiple stages adds 6502ebe7a52 [MachineLICM] Add functions to MachineLICM to hoist invaria [...] adds bf1689531ad [InstCombine] canonicalize fcmp+select to fabs adds d767d0a7b45 [demangler] Recopy the demangler from libcxxabi. adds db1b5f0c0f9 [CodeGen] Avoid handling DBG_VALUE in the LivePhysRegs (add [...] adds f01789ae309 Revert [MachineLICM] This reverts commit rL327856 adds 34035f0c288 [X86] Make the multiply and divide itineraries more consistent. adds 33cd6b5b1c4 [X86] Remove sse41 specific code from lowering v16i8 multiply adds 85724b02b40 [X86] Add MOV16ri*/MOV32ri*/MOV64ri* to scheduler models to [...] adds 8bb77ddd946 [X86] Add the rest of the TEST with immediate instructions [...] adds f20165913ca [PowerPC] Make AddrSpaceCast noop adds 328e67adb1e [PowerPC][Power9]Legalize and emit code for quad-precision [...] adds 10888ceb0ed [X86] Correct the SchedRW on (V)MOVAPSrr_REV and similar to [...] adds 369474116d7 [X86] Correct regular expression in Zen scheduler model tha [...] adds e7f0446eb91 [X86] Add JCXZ/JECXZ to Sandybridge/Haswell/Broadwell/Skyla [...] adds 0dec787211a [X86] Remove OUT32rr/OUT8rr/OUT32ri/OUT8ri from Sandybridge [...] adds 3c8e8f0115a [X86] Add JMP16r and JMP32r to Sandybridge scheduler model. adds 2518feb69d6 [Hexagon] Add a few more lit tests adds de37af54bdb [llvm-mca] Simplify code. NFC adds 8804752576c [llvm-mca] Remove unused method from ResourceManager. NFC adds 187f0849794 [Power9]Legalize and emit code for quad-precision copySign/ [...] adds 8a350b553d9 [AMDGPU] adjust tests to be nan-free adds 0245f1cd627 [AMDGPU] change test to avoid NaN math adds e8989cc97b9 Make ConstantDataArray::get constructor templated. Will sup [...] adds c010893e584 Support embedding natvis files in PDBs. adds c12cb2ce2d5 Add cast to Type*, fix failure from r327894. adds dbc74cb8729 [ARM, AArch64] Check the no-stack-arg-probe attribute for d [...] adds 3dd52e62ea3 [DAG, X86] Revert r327197 "Revert r327170, r327171, r327172" adds 468ff8a9b83 [X86] Replace a couple calls to getExtendInVec with getNode [...] adds e2a3256f7ce Remove an unused private variable. adds c643a82421d Revert "Support embedding natvis files in PDBs." adds 5fbee8fcb1f [Hexagon] Add REQUIRES: asserts to test/CodeGen/Hexagon/v6v [...] adds bbb189326d1 [PDB] Add exclusive methods to derived symbol class adds f19689a8da2 [PDB] Add a method to get the full path of the source file [...] adds c1a9456cbdd Accept any filepath in llvm_check_source_file_list adds b76a2f8b81f [X86] Simplify the AVX512 code in LowerTruncate a little. adds a1b5897aa30 [DAGCombiner] Fix type in comment. NFC adds aa9b406e17a [MachineOutliner] AArch64: Emit CFI instructions when outli [...] adds 88275016ddb [SelectionDAG] Transfer DbgValues when integer operations a [...] adds 32c22cbba9b Object: Move attribute calculation into RecordStreamer. NFC adds 488250e1efe Object: Fix handling of @@@ in .symver directive adds 95d1ad8f2dc [DebugInfoPDB] Add backward support flags to PDB_NameSearchFlags adds 47ac688332f Run dos2unix on a test. NFC. adds 18df4f09ff7 [X86] Fix the SNB scheduler for BLENDVB. adds 6a9321130f4 [RISCV] Preserve stack space for outgoing arguments when th [...] adds 12ea4642637 Fix layering between llvm-c and Support by factoring out so [...] adds c83d754ae2b [ShrinkWrap] Take into account landing pad adds 001a48c5f66 [X86] Add ROR/ROL/SHR/SAR by 1 instructions to the Sandy Br [...] adds ea05d68efb0 [X86] Add TEST16mi/TEST32mi/TEST64mi32 to the Sandybridge/H [...] adds 507d7742b96 [ORC] Rename SymbolSource to MaterializationUnit, and make [...] adds 95aa4b0a44a [X86] Fix the SchedRW for memory forms of CMP and TEST. adds d1339006229 [X86] Rename MOVSX32_NOREXrr8 to MOVSX32rr8_NOREX so that t [...] adds 0dadf10b4a7 [ORC] Don't fully qualify explicit destructor call -- it co [...] adds 29475f1bf8e [X86] Properly implement the calling convention for f80 for [...] adds 1c3cdea2f18 [SystemZ] Add "REQUIRES: asserts" to test case to fix build bots. adds afd766bf9c0 [LV] Let recordVectorLoopValueForInductionCast to check if [...] adds fb0d0c9b6d3 [CGP] Avoid segmentation fault when doing PHI node simplifications adds 9d81521985c [Release Notes] Add release note for llvm-mca. adds 2cfa233311b [AVR] Add a regression test for struct return lowering adds c9a5416c8fc Revert "Fix layering between llvm-c and Support by factorin [...] adds 7724d6bcafa [llvm-opt-fuzzer] Add irce to the fuzzing options adds d89cc9594c8 [MergeICmp] Fix a bug in entry block shuffled to middle of [...] adds 8e6d19ebe4a [MergeICmps] Break eargerly out of loop adds bce5921b79c [llvm-mca] Move the routine that computes processor resourc [...] adds f659c36f7f5 [X86][SandyBridge] Merge multiple InstrRW entries that map [...] adds 38b58f1b4f4 [Hexagon] Improve scheduling based on register pressure adds a07f460d529 [RISCV] Add codegen for RV32F arithmetic and conversion operations adds 0d055e19c37 [llvm-mca] Use llvm::make_unique in a few places. NFC adds 8ce26eb802f [RISCV] Add codegen for RV32F floating point load/store adds 45cd8b347fb [Hexagon] Fix division by zero in machine scheduler adds 41c8825da4f [AArch64][Falkor] Correct load/store increment scheduling details adds 4519ac37911 [Hexagon] Improve scheduling heuristic for large basic blocks adds 3f8e03ebb0c [Kaleidoscope] doc fix adds 3f86364e40e [X86][Haswell][Znver1] Fix typo in fldl instregexs adds bb8af2f3334 [DEBUGINFO] Add flag -no-dwarf-pub-sections to disable pub [...] adds 90166272c16 [AArch64] add fabs tests for PR36600; NFC adds 2215590bd6d [Hexagon] Check weak dependences when only 1 instruction is [...] adds a61bf37968d [LangRef] describe the default FP environment adds 5926c6d6fe8 [XRay] Lazily compute MachineLoopInfo instead of requiring it. adds b3bc29ae35c [Hexagon] Correct the computation of TopReadyCycle and BotR [...] adds f60cf82ca0e [LangRef] fix link formatting adds 119b4ed31aa Resubmit "Support embedding natvis files in PDBs." adds 645255bd306 MC: fix layering violation introduced in r325139. adds 4961d4cd766 Add an analysis printer for must execute reasoning adds 9a1bbfc77b1 [NVPTX] Make tensor load/store intrinsics overloaded. adds 5c0bc7c6357 [llvm-mca] Move the logic that computes the scheduler's que [...] adds e89563694fe [llvm-objcopy] Implement support for section groups adds b2ac93315d7 Revert "Resubmit "Support embedding natvis files in PDBs."" adds 284e7ac42de [MustExecute] Use the annotation style printer adds 58749583a19 [X86] Add phony registers for high halves of regs with low halves adds d8c4b815911 [PowerPC][LegalizeFloatTypes] Move the PPC hacks for (i32 f [...] adds 0183d4fd608 [llvm-mca] Remove const from a bunch of ArrayRef. NFC adds a4bf3b724ba [MC,X86] Cleanup some X86 parser functions to use MCParser [...] adds 0e29bc7c071 [Hexagon] Fix fall-through warnings in HexagonMCDuplexInfo.cpp adds 4bc8dde04b4 [Hexagon] Add heuristic to exclude critical path cost for s [...] adds 14bde67afca [Hexagon] Add a few more lit tests, NFC adds 823e8522943 [llvm-objcopy] Revert r328012 adds 81d5a0d35d9 [llvm-objcopy] Revert the tests from r328012 adds 6265550ceb2 [AArch64] Adjust the cost model for Exynos M3 adds a17749935c9 [WebAssembly] Added initial AsmParser implementation. adds c0f4846c2b6 [llvm-mca] add keyword override to a couple of methods in B [...] adds bed0b6132a6 [DEBUGINFO] Add -no-dwarf-debug-ranges option. adds 17ab24c8db8 [TableGen] Pass result of std::unique to vector::erase inst [...] adds 24e5cd2399b [TableGen] Use llvm::transform to simplify some loops. NFCI adds 36fc59c4769 [TableGen] Use vector::append instead of looping and callin [...] adds 0cd071c82ef [TableGen] Use range based for loop. NFC adds a08b9a16814 [AArch64] Add vmulxh_lane fp16 vector intrinsic adds a17a5fa0b67 For llvm-objdump and Mach-O files, fix the printing of modu [...] adds 13041108baf [X86] Don't use the MSVC stack protector names on mingw adds 287b901befd [ObjCARC] Add funclet token to ARC marker adds 9ec8f37d286 [ReachingDefAnalysis] Fix what I assume to be a typo Reachi [...] adds 6bfc13d2f5f [X86] Drop unnecessary InstRW overrides for WriteFMA adds c3f6be53504 [WebAssembly] Strip threadlocal attribute from globals in s [...] adds 10d5949495f [SchedModel] Simplify InstRegexOp::apply. NFCI. adds 16a143ef903 [MustExecute] Move isGuaranteedToExecute and related rourti [...] adds eec69847b25 [MustExecute] Add simplest possible test for LoopSafetyOnfo adds cce5a27f7d0 [WebAssembly] Update torture compile test expectations adds 16193ef0b37 [MustExecute] Shwo the effect of using full loop info variant adds 2c3cc29d17a [X86] Change PMULLD to 10 cycles on Skylake per Agner's tab [...] adds 18c08d4a366 Move DataTypes.h from Support to llvm-c to fix layering. adds b6f73f8f0be [TableGen] Use SmallMapVector to simplify some code that wa [...] adds 7be19caff20 [X86] Fix the SchedRW for XOP vpcom register form instructi [...] adds ab9186d500b Move Compiler.h from Support to Demangler to fix layering. adds 90d475a11fe Fix the actual user of DataTypes.h in llvm-c to avoid the c [...] adds 6eda329d34e [TableGen] Move a function from llvm namespace and make it [...] adds dbb224560c4 [TableGen] Remove a defaulted function argument that is nev [...] adds 36dd4b43610 [X86][Broadwell] Merge multiple InstrRW entries that map to [...] adds a48ab92bca4 [llvm-readobj] - Teach llvm-readobj to dump .note.gnu.prope [...] adds c8ecb9de6dc Fix build bot after r328078 "llvm-readobj] - Teach llvm-rea [...] adds 53107870962 [SelectionDAG] Support multiple dangling debug info for one value adds 74473fc50b9 Revert layering changes adds 8abcf8e6eff [dwarf] Unify unknown dwarf enum formatting code adds 88eab22187a Fix build broken by r328090 adds 32ad6ff3721 [llvm-mca] Clean up some code. NFC adds 2f0ad89dc48 Revert "Move DataTypes.h from Support to llvm-c to fix layering." adds 0be6cf599c9 Re-re-land: Teach CorrelatedValuePropagation to reduce the [...] adds 8bf245f39a7 [MemCpyOpt] Update to new API for memory intrinsic alignment adds 16e9a290212 [LangRef] more hyphens: always write "floating-point" adds e132439ab25 Change DT_* value definitions to macros in a separate file adds 30a32a618ed [RISCV] Add tests missed from r327979 adds 94f16be2380 [RISCV] Codegen support for RV32F floating point comparison [...] adds f169e120a7f [LangRef] add note about format of FP types adds f633bc35164 [InstCombine] move/add tests for xor-of-icmps (PR36682); NFC adds c414c7259c0 [X86][SandyBridge] Merge more VEX/non-VEX instregex pattern [...] adds dc89989167e [X86][Haswell] Merge multiple InstrRW entries that map to t [...] adds fec64ebeba4 [WebAssembly] Suppress unused function warning for register [...] adds 31d44fceb15 [Hexagon] Eliminate subregisters from PHI nodes before pipelining adds e9a0122a40d [Documentation] Fix markup problem in AMDGPUUsage.rst. adds 02dea26d56a TableGen: Streamline how defs are instantiated adds 9fe53b205cb TableGen: Remove redundant loop in ListInit::resolveReferences adds 96157b8553c [InstCombine] add folds for xor-of-icmp signbit tests (PR36682) adds 73e73c044e5 [Hexagon] Generalize DAG mutation for function calls adds 8dce0ebcdac [Documentation] Fix markup problems in X86Usage.rst adds 8b9a0b319aa Add missing #includes to Analysis/MustExecute.h adds 1c62040a5cf Reapply Support layering fixes. adds de69937494c [Docs] Remove some WIP X86 documentation I accidentally lea [...] adds 6ee668d4cbd [SchedModel] Use CodeGenSchedClass::isKeyEqual instead of d [...] adds 4a705d1b606 [SchedModel] Use CodeGenSchedClass::getSchedClassIdx helper [...] adds 2ff763c8ed2 [llvm-mca] Move the logic that computes the register file u [...] adds 6d18d80e29a Ensure that DataTypes.h is installed now that it's moved to llvm-c adds 66677152d05 [InstrProf] Support for external functions in text format. adds 63f2cc2aa90 [SLP] Add test case for a gather sequence with multiple uses adds d7ca916c7c7 Sink Analysis/ObjectUtil(canBeOmittedFromSymbolTable) into [...] adds bbe1a9edde0 [X86] Rewrite getOperandBias in X86BaseInfo.h to be a littl [...] adds 788fc6f75e6 [TableGen] Use count_if instead of a manual loop. NFC adds e2cd723d4e9 [TableGen] Use range-based for loops. NFC adds cbb421beaa9 [TableGen] Remove unnecessary map lookup and shadowing of a [...] adds 3e65cc15a0e [InstSimplify] fp_binop X, NaN --> NaN adds dbce663d7fc typo adds 6790638696e [TableGen] Hoist the code for copying InstRWs from an old s [...] adds 36cdb40ffa9 [llvm-objcopy] Implement support for section groups adds 74173207d10 Revert r328119 "[InstCombine] add folds for xor-of-icmp sig [...] adds d03537f6d36 [POWER9][NFC] update testcase check statements adds efc6b72c7c5 [InstCombine] move/add tests for fmul distribution; NFC adds d227a3b47ef Handle abbr_offset with relocations. adds 94fa4665a6c [WebAssembly] Really disable wasm register name matcher adds 2d2cbcb32d9 [PDB] Remove unused private variable, re-applying r327900 a [...] adds 143902e14cd [llvm-profdata] Use "-o /dev/null" in invalid-profdata.test adds bc1c5eddf29 [NVPTX] Make tensor shape part of WMMA intrinsic's name. adds 1cc14d86af7 [test] Add tests for llc passes pipelines. adds 05d039d2025 [test] Add tests for opt passes pipelines for O0, O2, O3, and Os. adds 1ea77ad5866 [PDB] Don't ignore bucket 0 when writing the PDB string table. adds 06b0783db13 [InstrProf] Encapsulates access to AddrToMD5Map. adds 283527b3900 Fix a couple of layering violations in Transforms adds 35ba77daa3b [test] Try to unbreak hexagon bots after r328160. adds 164c112ac4a vim: add `dso_local` and `dso_preemptable` keywords adds fcd7af40529 [PDB] Get more DIA table enumerators adds b360e566cfd [DIA] Add IPDBSectionContrib interfaces and DIA implementation adds b0f0b5ebce3 [X86][Skylake] Merge multiple InstrRW entries that map to t [...] adds dc3f0cc9d71 [X86] Remove unused SchedWriteRes classes. NFC adds d74de62f37c [TableGen] Add a non-default constructor to CodeGenSchedCla [...] adds b0f8e696aae [TableGen] Use empty emplace_back to add defaulted construc [...] adds 280f00a153c [llvm-mca] Simplify code. NFC adds 7abb456200f Revert "[test] Add tests for llc passes pipelines." adds 3f00e08460f [CloneFunction] Preserve DT in DuplicateInstructionsInSplit [...] adds efac2a80464 [llvm-mca] Simplify (and better standardize) the Instructio [...] adds 213a51db0a6 Add vendor specific calling convention to DWARF adds 4a0d8d3b03f [X86] Use the default AES scheduler classes directly. NFCI. adds 20bfacfd59f [X86][CLMUL] Fix/add missing itinerary tags to (V)PCLMULQDQ [...] adds c6005c0d9ac [X86][CLMUL] Use the default CLMUL scheduler classes direct [...] adds 92198f30146 [InstCombine] add folds for xor-of-icmp signbit tests (PR36682) adds d7398385c01 [llvm-mca] Minor refactoring. NFCI adds 3d2595ce36e DWARFVerifier: verify debug_names abbreviation table adds 047303ecc62 [X86][SSE42] Use the default PCMPEST/PCMPIST scheduler clas [...] adds f973ed2782d [MC] fix documentation comments; NFC adds 5185879973d [CallSiteSplitting] Preserve DominatorTreeAnalysis. adds 364eb09576a Revert "[InstrProf] Support for external functions in text [...] adds d3997f9e4ea [DWARF] Fix mixing assembler -g with DWARF .file directives. adds 769052bf89c Move MetaRenamer from Transforms/UTils to Transforms/IPO si [...] adds ded959f9f42 [LoopPredication] Add profitability check based on BPI adds d6947e36d89 vim: rename `singlethread` to `syncscope` adds 7fdf2c28149 [DWARF] Add EmitDwarfOffset function, NFC. adds 7d085b607df [SimplifyCFG] Create attribute for fuzzing-specific optimizations. adds 8804d5ef4a8 [ARM] Enable the full InstRW overlap check for ARMScheduleR52.td adds 1ab12510bbb [X86][Btver2] FMUL ymm instructions are double pumped on th [...] adds 258782adb21 [GISel]: Fix incorrect IRTranslation while translating null [...] adds 5a43e12ccb5 [Codeview/PDB] Rename some methods for clarity. adds 304948c9f7e [X86][Btver2] FCMP (inc FMAX/FMIN) instructions use the JFP [...] adds 2d0d47ceb8b [X86][Btver2] Conversion, MaskedLoad/MaskedStore and NTStor [...] adds 8c2147125a6 [InstCombineCalls] Update deprecated API usage (NFC) adds a95f2c4f47b [X86] Correct the scheduling data for some of the 32 and 64 [...] adds bd3649ff6d6 [DAG, X86] Fix ISel-time node insertion ids adds 30a7db5e5fa Move the initialization of the Meta Renamer pass over to IP [...] adds adec4ee33d6 [DWARF] Replace assert with diagnostic. PR36868. adds 590f2e2f2eb Document optforfuzzing attribute created in r328214. adds af566830199 [CodeGen] Add a new pass for PostRA sink adds d8ad3cf8c91 [MachineOutliner][NFC] Refactoring + comments in runOnModule adds d2172848309 [X86][SkylakeClient] Fix a bunch of instructions that were [...] adds 21d9c7a33c5 Revert "Revert "[InstrProf] Support for external functions [...] adds 238a3389d05 [MIR] Making MIR Printing, opt -dot-cfg, and -debug printin [...] adds 7afebf73492 Fix layering between SCCP and IPO SCCP adds 423eb96060c [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst [...] adds c4f4f54c9df [X86] Rename VROUNDYPS* and VROUNDYPD* instructions to VROU [...] adds b31382197fd Add test for demangling GNU ABI tags. adds ca64890b851 Revert r325687 (workaround for PR36032). adds f181976a674 Finish moving the IPSCCP pass from Scalar to IPO - moving t [...] adds 0db608b20c6 [X86] Correct the VROUND regular expressions in Znver1 sche [...] adds d140aea2312 Move SampleProfile.h into IPO along with the rest of the IP [...] adds ac2f2dee4b7 Reapply "[test] Add tests for llc passes pipelines." with a [...] adds 61fb9e7a944 [Support/Parallel] Use lock_guard which has less overhead t [...] adds b9182a2b32b State that CFG is preserved in 'Falkor HW Prefetch Fix Late [...] adds 6394fed3dc8 For llvm-nm and Mach-O files also use function starts info [...] adds 729e2bc549a [TableGen] Don't capture returned std::vectors by const reference. adds aea03035b9c [DAG] Fix node id invalidation in Instruction Selection. adds 555ee3a0e12 [X86] Fix the itinerary for vextractps to match extractps. adds 7b045fcd1fe [X86] Add VEXTRB/W/D/Q to Zen scheduler model. adds 23b385dc5a4 [X86] Merge VMOVMSKBrr and MOVMSKBrr in the SNB sheduler model. adds 3a512b02aca [X86] Give VLDDQUrm and LDDQUrm the same itinerary. adds 1a5a81ce0e0 [X86] Change VPSADBW itinerary to SSE_INTALU_ITINS_P to mat [...] adds 727b684e151 [X86] Match vpblendvb/vblendvps/vblendvpd itineraries to th [...] adds daf2cf12902 [X86] Correct the latencies of SNB integer vector multiplie [...] adds 3475594d1e1 [X86] Give VPCMPEQQ the same itinerary as its SSE counterpart. adds c5f9aedb728 Revert "[DAGCombiner] Fold (zext (and/or/xor (shl/shr (load [...] adds 20ec3b01c72 [ARM] Error out on .arm assembler directives on windows adds 5277548f84a [ORC] Join materialization thread in unit test adds bf6a9a9d8c3 [LoopUnroll] Simplify induction variables after peeling too. adds ebbdedf2b3d [AArch64] Clean-up a few over-eager regexps in models. adds 32a98598833 [X86][Btver2] Vector move/load/store instructions use a JFP [...] adds 10ba818f3b2 [llvm-mca] Add flag -resource-pressure to enable/disable pr [...] adds 8a63941a9ff [llvm-mca] Pass the InstrBuilder to the constructor of Backend. adds a1633c3b32c [IPSCCP] Use constant range information for comparisons of [...] adds ad4f5a90486 [X86][SandyBridge] Fix missing comma that was causing strin [...] adds f89d0f29475 [X86][Znver1] Fix instregex entries that don't match any in [...] adds 639d24925ea [test] Allow for optional No-Op Barrier Pass in O0 pipeline adds 844cfa056c8 [GlobalISel] Fix legalizer combine to not use illegal input [...] adds 02f8ef30638 Revert r328307: [IPSCCP] Use constant range information for [...] adds a0e24a5d9f3 [ARM] Support float literals under XO adds 37d8f03a367 [DEBUGINFO] Add flag for DWARF2 to use sections as references. adds 7e21e42ddaa Remove deprecated MemIntrinsic methods (NFC) adds 27f212d583a [SLP] Stop counting cost of gather sequences with multiple uses adds 4a4cde36b5f Remove the deprecated single-alignment IRBuilder API for me [...] adds 35ac3518056 [X86][Btver2] Cleanup SSE42 PCMPISTR/PCMPESTR string instru [...] adds 9023810566b [X86][Btver2] Fix MicroOps counts for DPPS/YMM memory folde [...] adds a5f02879283 [AArch64] Don't reduce the width of loads if it prevents co [...] adds 02dc2b96487 [InstCombine] improve variable name; NFC adds 9e58a322ef6 [InstCombine] reduce code duplication; NFC adds 8ec7dc027c8 [X86][Btver2] Cleanup DPPS/DPPD instructions to use JFPA/JF [...] adds 9dd8ea36b2b [InstCombine] regenerate test checks; NFC adds 4561f7dac87 Re-commit: [MachineLICM] Add functions to MachineLICM to ho [...] adds ff51e420754 [InstSimplify] regenerate checks, move tests; NFC adds 1234988eb62 [X86][Btver2] Vector store instructions use a JFPU1 schedul [...] adds 20274bee14b [InstCombine] auto-generate checks; NFC adds aa42861b09e [X86][Btver2] Vector permutes use a JFPU01 scheduler pipe a [...] adds c1ba2003d30 [Hexagon] Copy subregisters in HexagonStoreWiden adds b14d2e8797b [ADT] Simplify getMemory. NFC adds c643add02d8 [llvm-mca] Make the resource cost a double. adds 1224e3b5b37 Fix a block copying problem in LICM adds 03d3921f6ef [X86][Btver2] Cleanup MOVMSK instructions to use JFPA funct [...] adds 75d94b0a1b4 [Hexagon] Two fixes in early if-conversion adds f536a15c84b [llvm-mca] update the ResourcePressureView after r328335. NFC. adds 2aafc7ac030 [ARM] Fix "Constant pool entry out of range!" in Thumb1 mode adds 49cb85b13af [HWASan] Port HWASan to Linux x86-64 (LLVM) adds fc595472281 [X86][Btver2] Cleanup TEST instructions to use JFPA (+JFPX [...] adds ab5fa751830 [Hexagon] Avoid early if-conversion for one sided branches adds c2422b8ca68 Delete the copy constructor for llvm::yaml::Node adds 287a3ef3c92 [Hexagon] Always generate mux out of predicated transfers i [...] adds 0995a92322b [PDB] Make our PDBs look more like MS PDBs. adds 2b4b7fe3620 [AMDGPU] Remove use of OpenCL triple environment and replac [...] adds 9272c8addcb [AMDGPU] Update OpenCL to use 48 bytes of implicit argument [...] adds 668c5c9a6ac [X86] Add itineraries to ADD.*_DB instructions to match the [...] adds 5c164ff75ee [X86] Add itinerary to RCPSS*_Int and similar instructions. adds 9c29185b4fe [Hexagon] Fold offset in base+immediate loads/stores adds fcf36ad098b [Hexagon] Silence unused variable warning in Release builds adds 6ee63824e6b [Hexagon] Incorrectly removing dead flag and adding kill flag adds 3b9d2408db6 [llvm-mca] Split the InstructionInfoView from the SummaryView. adds b5af7692c5d [Hexagon] Assume all extendable branches to be of size 8 in [...] adds 40a7eed5094 [PDB] Resubmit "Support embedding natvis files in PDBs." adds 285ec603522 [Hexagon] Boost profit for word-mask immediates, reduce for others adds b0f83298593 [Hexagon] Correct update of instruction offet in HW loop fixup adds a9607de4ae4 [Hexagon] Make findLoopInstr member of HexagonInstrInfo adds e3edd4831b3 [InstCombine] increase test coverage for intrinsic shrinking; NFC adds 8a304166110 [InstCombine] simplify code for FP intrinsic shrinking; NFCI adds ae29a3a8040 [PM][FunctionAttrs] add NoUnwind attribute inference to Pos [...] adds a10309cedda Fix Layering, move instrumentation transform headers into I [...] adds e8b9e310f66 [X86] Fix Windows `i1 zeroext` conventions to use i8 instea [...] adds 4dcdb906955 [GuardWidening] Group code by class [NFC] adds fe42bd50da4 Move TargetLoweringObjectFile from CodeGen to Target to fix [...] adds cb6b3afcb25 Fix layering by moving X86DisassemblerDecoderCommon to Support adds dae3bbe6a3f Fix layering by moving Support/CodeGenCWrappers.h to Target adds 9d9a46a465e Fix layering of MachineValueType.h by moving it from CodeGe [...] adds b9334112fc4 Fix layering of CodeGen/TargetOpcodes.def by moving it to Support adds b91d9a71287 Fix layering by moving ValueTypes.h from CodeGen to IR adds fbb1ffb01cd [X86] Correct the value AdSizeX in X86II enum. NFC adds 679790c5c04 Remove unused header from EntryExitInstrumenter adds 39974018fc6 Allow FDE references outside the +/-2GB range supported by [...] adds b97c8e64c6e [X86] Add a DAG combine to simplify PMULDQ/PMULUDQ nodes adds 0a0437fc09e Add REQUIRES lines for the targets being checked in this test. adds f0c0da8ab25 [X86] Merge the Has3DNow0F0FOpcode TSFlag into the OpMap en [...] adds 4f709f6290d [X86] Remove an unnecessary switch around two other switches. NFC adds ce08cb32ab5 [X86] Use X86_INSTR_MRM_MAPPING macro instead of listing al [...] adds 2280dbe191a [X86] Use unique_ptr to simplify memory management. NFC adds 7cff4112905 [X86] Add a new disassembler opcode map for 3DNow. Stop tre [...] adds f5891a03e15 [X86][AVX2] Ensure we don't use later instruction sets in A [...] adds 02ccc542f04 [X86][AVX1] Ensure we don't use later instruction sets in A [...] adds 905503826cb [InstCombine] add multi-use/vector tests for intrinsic shri [...] adds b5d6a0f78a2 [X86][SSE] Ensure we're testing both non-VEX/VEX variants o [...] adds b747538097f [X86][AES] Ensure we're testing both non-VEX/VEX variants o [...] adds 97758c96a5e [InstCombine] fix formatting; NFC adds 51bf1123ff2 [InstCombine] peek through FP casts for sign-bit compares ( [...] adds 7525290f96d [llvm-mca] Remove unused field in InstrBuilder. NFC adds add7b3e24ef [llvm-mca] run clang-format on all files. adds a71df880dd0 [AMDGPU] Change std::sort to llvm::sort in response to r327219 adds 7780649d412 [Hexagon] Change std::sort to llvm::sort in response to r327219 adds 43a750729a7 [X86][SandyBridge] Merge xmm/ymm instructions instregex ent [...] adds 329aaa6a3b9 [X86][Haswell] Merge xmm/ymm instructions instregex entries [...] adds df931524ae5 [RISCV] Use init_array instead of ctors for RISCV target, b [...] adds c6d3a5eaa07 [X86][Broadwell] Merge xmm/ymm instructions instregex entri [...] adds 9a7f9fe9d61 [X86][SkylakeClient] Merge xmm/ymm instructions instregex e [...] adds 79483b2bf49 [SchedModel] Avoid std::string creation for instregex patte [...] adds ded7cc40dad [SchedModel] Record::getName() returns StringRef - avoid st [...] adds 92016652c4b [SchedModel] Remove std::vectors that were created with 1 e [...] adds a078148144e Fix module.modulemap after r328395 adds af807a64a6b [SchedModel] Use std::move to replace a vector instead of v [...] adds 284e1ff26d2 [SchedModel] Use std::move in a couple places to reduce copying adds 419fa240023 [SchedModel] Remove an unneeded temporary vector. adds 6c053b7e51e [X86] Update a partially stale comment, since SVN r328386. NFC. adds 04dad85394b [X86] Consistently prefix all defs in X86ScheduleSLM.td wit [...] adds 7a1a91f7369 [X86] Add the ability to override memory folding latency to [...] adds aef1b112e12 [InstCombine] peek through more icmp of FP cast + bitcast adds eb6f6afe62a [InstCombine] consolidate casted icmp vector tests adds 9c0bd4b3bc9 [InstCombine] adjust test comments; NFC adds e192eb0ee6d [X86] Update cost model for Goldmont. Add fsqrt costs for S [...] adds 96cdb99aa1b [X86][SkylakeServer] Merge multiple instregex. NFCI adds feb39051265 [X86][MMX] MOVQ2DQ/MOVDQ2Q are better described as WriteVec [...] adds d40afef4915 [X86][SkylakeClient] Fix a set of regular expressions that [...] adds 1241873ba4d [InstSimplify, InstCombine] add/update tests with FP +0.0 v [...] adds 0989cb2c430 [X86] Add missing full stop to comment. NFCI. adds cfec5dcf63e [ARM] Remove sched model instregex entries that don't match [...] adds 9c2d3ad18e3 [X86][SkylakeClient] Fix missing comma adds fb87505f61a [SchedModel] Remove instregex entries that don't match any [...] adds 636b39a97c8 [X86] Use WriteResPair for WriteIDiv to cleanup sched defs. NFCI. adds 10176786777 [PatternMatch] allow undef elements when matching vector FP +0.0 adds e7042cfa9c9 [demangler] Support for clang's enable_if attribute. adds 49908590729 [demangler] Tweak how parameter pack sizes are determined. adds 21f282660df [demangler] Use a back-patching scheme to resolve forward r [...] adds f4156906fc4 [X86] Move (v)movss to port 5 only for Skylake. Move (v)mov [...] adds 629da0d3f5f [X86] Give vpmsadbw the same itinerary as the SSE version s [...] adds 12144401352 [X86] Give VMOVSX/ZX the same itinerary as the SSE version [...] adds 8816046c767 [X86] Swap the itineraries on the memory and register forms [...] adds 1f70ff89ce8 [X86] Use the same itinerary for VCVTDQ2PD as the SSE versi [...] adds c2d0f67793c [X86] Correct the itineraries for the dot production instructions. adds a514d327d80 [X86] Add itinerary to intrinsic version of sqrtss, rcpss, [...] adds 0738cbc4142 [X86] Merge the SSE and AVX versions of fp divs and sqrts i [...] adds 640ccb5e8cc [X86] Fix the SchedRW for intrinsic register form of SQRT/R [...] adds 2c3af0c1d2c [ARM] Simplify constructing the ARMArchFeature string. NFC. adds 714416332b3 [IRCE] Enable increasing loops of variable bounds adds 120cf639c0a [DeadArgElim] Strip allocsize attributes when deleting an a [...] adds 7b0d0302dff Revert r328386 "[X86] Fix Windows `i1 zeroext` conventions [...] adds edec8af2251 [LoopUnroll] Fix dangling pointers in SCEV adds df730ad235f Test commit - adding a new line. adds 181ce9f6092 [llvm-mca] Add flag -instruction-tables to print the theore [...] adds 48972e6c8f9 [LSR] Allow giving priority to post-incrementing addressing modes adds d1449c97e57 [X86][Btver2] Double the AGU and schedule pipe resources for YMM adds 33dfb9de6c4 [llvm-mca] Update the commandline docs after r328305. adds fafdf4a29ce [llvm-mca] Add a flag -instruction-info to enable/disable t [...] adds 6e532c9bf01 AMDGPU: Introduce common SOP_Pseudo and VOP_Pseudo TableGen [...] adds 74c171f5c08 [X86][Btver2] Add (V)SQRTPD/(V)SQRTSD costs adds 4432622fbc8 [InstCombine] check uses before creating instructions for f [...] adds 7fa3ae5ae3e [llvm-mca] Fix how views are added to the InstructionTables. adds da4fb16364d [X86][Btver2] Fix YMM BLENDPD/BLENDPS + UNPCKPD/UNPCKP inst [...] adds 3e5c120fbac [InstCombine] distribute fmul over fadd/fsub adds 474404b22b0 Migrate dockerfiles to use multi-stage builds. adds c6c033fb73a [X86][Btver2] Add CVTSD2SI/CVTSS2SI scheduler costs adds eb1ea2f1c81 [Hexagon] Give priority to post-incremementing memory acces [...] adds a76b7566a84 [demangler] Fix a bug in r328464 found by oss-fuzz. adds b2c894024b5 [Pipeliner] Correctly update memoperands in the epilog adds a13b439b133 [Pipeliner] Pipeliner should mark physical registers as used adds d5ceb00b90e [Pipeliner] Fix in the pipeliner phi reuse code adds 2fc30a3dc44 [Pipeliner] Fix check for order dependences when finalizing [...] adds f0568a860ce [X86][Btver2] Account for the "+i" integer pipe transfer co [...] adds 1e6d98ea5e1 [Pipeliner] Fix calculation when reusing phis adds 42f8f944d97 [Pipeliner] Enable more base+offset dependence changes in p [...] adds 0c137c56602 [InstCombine] reassociate loop invariant GEP chains to enable LICM adds 6023f6ca35a [Pipeliner] Fix assert caused by pipeliner serialization adds b483db269fb [X86][Btver2] Add CVTSD2SS/CVTSS2SD scheduler costs adds 5f51cb0ad85 [Pipeliner] Use latency to compute RecMII adds 2d4c98fec96 [Pipeliner] Fix number of phis to generate in the epilog adds 276ad3cf6cc [Pipeliner] Fix renaming in pipeliner when eliminating phis adds b9e7253e391 [SLP] Add a test case. NFC. adds b709662b9c2 [Pipeliner] Add missing loop carried dependences adds fecaf52c6b1 Remove unneeded (& mislayered) include from TargetMachine.c [...] adds 42e9b96ddfd Remove an unneeded (& mislayered) include from Target/Targe [...] adds b22cddf04e5 [Pipeliner] Check for affine expression in isLoopCarriedOrder adds 92d40b0a3d4 [X86][Btver2] Add CVTSI2SD/CVTSI2SS scheduler costs adds 476b2588b14 [AMDGPU] Improve disassembler error handling adds e67cab7ed99 [Pipeliner] Several node-ordering fixes adds 10fe375630c Disable [MachineLICM] Add functions to MachineLICM to hoist [...] adds ba5863e984a [PowerPC] Infrastructure work. Implement getting the opcode [...] adds ae98859fc1d [Power9]Legalize and emit code for quad-precision convert f [...] adds 99cf6a153e3 [InstCombine] improve code comment; NFC adds 03a0661f606 [Hexagon] Add more lit tests adds 01931073eb2 Delete pdbutil diff mode. adds d15fdc63fa8 [lit] Implement 'cat' command for internal shell adds 61e5f25ff11 [XCore] Change std::sort to llvm::sort in response to r327219 adds a9c6c33abc5 Remove unused file, ExecutionEngine/MCJIT/ObjectBuffer.h adds 33b38a21e8e [X86] Add WriteBitScan/WriteLZCNT/WriteTZCNT/WritePOPCNT sc [...] adds ff1d4d27d78 [X86] Fix Windows `i1 zeroext` conventions to use i8 instea [...] adds 648a6091ecc [SLP] Add more checks to a test case. NFC. adds ac9701c363f [X86][Btver2] Add (U)COMISD/(U)COMISD scheduler costs adds cc9e41f605b [Hexagon] Assertion failure in HexagonSubtarget.cpp adds b972acbf78d [MemorySSA] Fix exponential compile-time updating MemorySSA. adds c7df4e42afc Use correct format specifier. Review comment on r328235 by [...] adds 13e4ac01113 Fix go bindings test when using goma distributed build tool adds f9941d3c0d3 Use local symbols for creating .stack-size. adds b72ac7e9e83 [X86] Add WriteCRC32 scheduler class adds aa18302e4fe Fix newlines. NFCI. adds af0c1412d95 [DebugInfoPDB] Add DIA implementation of addressForVA and a [...] adds f975bab62fb [DebugInfoPDB] Add DIA implementation of findLineNumbersByRVA adds 28ec98c907a [DebugInfoPDB] Add methods to get the compiland and line nu [...] adds ca7fdbb9743 [lit] Generalized /dev/null support on Windows. adds 2b889957ee0 [DebugInfoPDB] Print the method name along with the variant value adds 8fd84ebcf37 [x86] add tests for ftrunc; NFC adds 1d4a167c65d Move CVDebugRecord from CodeView to Object to fix layering adds 22f6baa132a Add a build dependency from libMC to libDebugInfoCodeView t [...] adds 35e080b5365 Revert "[lit] Generalized /dev/null support on Windows." adds 771829b640a [lit] Temporarily disable shtest-timeout.py on darwin adds 678a72e7482 [x86] add RUN for target before roundss; NFC adds 7348dc2750a Revert "Revert "[lit] Generalized /dev/null support on Windows."" adds fa067e8cb8e [MachineScheduler] Add itinerary to schedcover.py. Make def [...] adds 10568deedda [SCEV] Add one more case in computeConstantDifference adds 8f8f2fa4dd8 [SCEV] Make exact taken count calculation more optimistic adds 0048092b9c8 [NFC] Fix comments in getExact() adds 0ba1cd85f0f [IRCE] Enable decreasing loops of non-const bound adds 56b15eb6ebd [LoopUnroll][NFC] Remove redundant canPeel check adds e0a5279318f [MIPS] Add static_assert that all Fixups are handled in get [...] adds 4ec907cc28e [PowerPC] Secure PLT support adds ff39c611114 [X86][Btver2] Add MMX_PMOVMSKBrr to MOVMSK scheduler class adds 7395f4fb58c [llvm-mca] pass the correct set of used registers in checkRAT. adds 4153b00c216 [LV] Add TTI::shouldMaximizeVectorBandwidth to allow enabli [...] adds 9273bb3570e Use .set instead of = when printing assignment in assembly output adds 558f76fb1dd [NFC] OptPassGate extracted from OptBisect adds 1560bf03438 [AArch64] Decorate AArch64 instrs with OPERAND_PCREL adds 24feab89192 [Hexagon] Rudimentary support for auto-vectorization for HVX adds 22c5f7cb54b Fix a reoccuring typo in load-combine tests adds 104b1294749 Remap values in PromotedFloats adds 9470442c907 [Power9] Fix the resource list for the COPY instruction. adds a9d6d4cb72b [Hexagon] Implement TTI::shouldMaximizeVectorBandwidth adds aaf71562321 AMDGPU: Fix FP restore from being reordered with stack ops adds a833b4252d0 AMDGPU: Fix register name format in tests adds bf82806c2ee AMDGPU: Fix crash when MachinePointerInfo invalid adds 25956d8d3c8 [PGO] Fix branch probability remarks assert adds 117b6717070 [DWARF] Simplify DWARFAddressRange::contains adds afaac4ad30d AMDGPU: Set natural stack alignment in DataLayout adds a2f8776c07e AMDGPU: Fix not preserving CSR VGPR if used for SGPR spills adds 10b8d1571ca 80-line wrap. NFC adds 86d0c61b6fb [YAML] Escape non-printable multibyte UTF8 in Output::scala [...] adds 3c8a7c30ccf [DWARF][DWARF v5]: Adding support for dumping DW_RLE_offset [...] adds 1b35c9a0d86 [X86] Add WriteFMOVMSK/WriteVecMOVMSK/WriteMMXMOVMSK schedu [...] adds 531edfd3b91 [YAML] Remove unit test of multibyte non-printable escaping [...] adds 10478ee1f32 Initialize variable added in r328617. adds fccceddef3c [CodeGen] Fixed unreachable with -print-machineinstrs and c [...] adds d31305af4f0 [AMDGPU] Define code object identification string used in A [...] adds 730f4c7d716 [DWARF] Suppress split line tables more carefully. adds 0daf86291d3 [AMDGPU] For OS type AMDPAL, fixed scratch on compute shader adds 49dbb6edd82 [MachineOutliner] AArch64: Don't outline ADRPs with un-outl [...] adds 973d7ed6e9c Reapply "[DWARFv5] Emit file 0 to the line table." adds ee25d6c0ce3 AMDGPU: Really implement getFrameRegister adds ceb2de9399c [WebAssembly] Add exception and selector intrinsics adds 21bae12a9e4 [PowerPC] add ftrunc vector tests; NFC adds abcc316cb54 [AArch64] add ftrunc tests; NFC adds de6ad3a31fb [ORC] Fix ORC on platforms without indirection support. adds 1effa108aef [RegisterCoalescing] Don't move COPY if it would interfere [...] adds fd7cc69a64d [ARM] Support float literals under XO adds 1ca736e56f6 [MSan] Add an isStore argument to getShadowOriginPtr(). NFC adds bece5f87091 [X86][BtVer2] Fix the number of micro opcodes for a bunch o [...] adds 9f475f3a912 Revert "[AMDGPU] For OS type AMDPAL, fixed scratch on compu [...] adds ebc5027eb82 [MSan] Introduce ActualFnStart. NFC adds ed2243b21bc [X86][BtVer2] Fix the number of micro opcodes for AES[ENC|D [...] adds 7323a7bf809 Revert "Reapply "[DWARFv5] Emit file 0 to the line table."" adds b42dc3192fa [X86][Btver2] Moved JWriteFCmp/JWriteFCmpY classes next to [...] adds 3a421b791d4 [lit] Remove a timing senstive part of `shtest-timeout.py` adds 0822ac42c4d Revert "[lit] Temporarily disable shtest-timeout.py on darwin" adds 1a79b714666 [AMDGPU][MC][GFX9] Added s_scratch* instructions adds c584e9e80eb [ORC] Re-add the Windows check that was dropped in r328687. adds 19a26aafdb3 [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x adds 03d46f12abf [PatternMatch] Add matchers for vector operations adds 4288e700e05 [AMDGPU][MC] Added PCK variants of image load/store instructions adds 9e19b76c0bb [ORC] Restore the narrower check from before r328687. adds 3bce2685f17 [AMDGPU][MC] Added ds_add_src2_f32 adds 240b840e702 [X86][AVX2] Add shuffle test case from PR36933 adds 59aa4501cc4 [llvm-ar] Support multiple dashed options adds 49ca55e3813 Transforms: Introduce Transforms/Utils.h rather than spread [...] adds 2b13c66b9ff [MachineOutliner] Simplify call outlining + require valid c [...] adds a5fb5aaf81f Oops - moved slightly too many things from Scalar to Utils. [...] adds 1b2b18b4a8e [Hexagon] Add support for "new" circular buffer intrinsics adds e6597a2a88f [PostRAMachineSink] preserve CFG adds 7c7f19c5827 [X86][SkylakeServer] Remove checks for 'k', 'z', '_Int' and [...] adds ebb5c411453 Plumb useAA through TargetTransformInfo to remove Transform [...] adds 9f7a1218718 Add missing dependency (headers are included from MC, so a [...] adds 8fa57f4788a Split Disassembler.h in two to fix dependencies adds 21251db1b49 Remove some unused includes to fix layering. adds 2fceac297fb [MemorySSA] Consider callsite args for hashing and equality. adds dad68b7bf78 [MemorySSA] Turn an assert into a condition adds a947197ad9b [X86] Cleanup inheritance of the X86InstrFormats.td classes. NFC adds 8221cef0d7e [X86] Rename RIi64_NOREX tblgen class to just Ii64. Make RI [...] adds e9c4ebc285a [LLVM-C] Finish exception instruction bindings adds 7ff39f36382 [X86] Don't pass getRegisterName from the InstPrinters into [...] adds 5c990415df8 [NFC] Fix meaningless assert in SCEV adds 157cb63b8b9 [Transforms] Make sure to include the c binding header when [...] adds 14d04397ce7 [LoopRotate] Restructuring LoopRotation.cpp to create Loop [...] adds 7693b32badc [Mips] Remove dead code adds 2a6cf858285 Rename llvm library from libLLVM-X.Y to libLLVM-X adds 6fbc9985d1b [X86][SSE] Don't bother re-adding combined target shuffles [...] adds 5e6fce16935 [Kaleidoscope] Tiny typo fixes adds 57cb15b7590 .debug_names: Parse DW_IDX_die_offset as a reference adds 934bf243bc8 [Hexagon] Add support to handle bit-reverse load intrinsics adds 8ff27dbe39e [llvm-mca] Correctly set the ReadAdvance information for re [...] adds 1aa8147054e .debug_names: Correctly align the AugmentationStringSize field adds 9c598cb7f28 [JumpThreading] Don't select an edge that we know we can't thread adds 0ebcf2f5d75 [PDB] Add an explain subcommand. adds 5be04161513 Remove unused function. adds cc1c5db7cf7 [ADT] NFC: Fix bogus StringSwitch rule-of-five boilerplate adds 5551cf2225c [PDB] Fix a bug in the explain subcommand. adds 274009662fb Reapply "[DWARFv5] Emit file 0 to the line table." adds f137ed238db [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp [...] adds 103f6b63ebd [PDB] Print some more details when explaining MSF fields. adds 289a2f5b392 [MSF] Default to FPM2, and always mark FPM pages allocated. adds 09493fff69e [SLPVectorizer] Add tests related to PR30787, NFCI. adds 1bfbe34701e Try to fix a couple tests for Windows. adds 8a009df969f [Mips] Change std::sort to llvm::sort in response to r327219 adds 1c3e6b6d3c6 Fix an accidental circular dependence adds 3ca9749f0a3 AMDGPU: Fix selection error on constant loads with < 4 byte [...] adds 157fe6044fd For llvm-nm and Mach-O files that are fully stripped, speci [...] adds ad41f941dcf AMDGPU: Increase default stack alignment adds 46f914f5a71 [NFC][LICM] Rearrange checks to have the cheap bail out first adds 1b2c29aafbb [X86] Correct the placement of ReadAfterLd in BEXTR and BZH [...] adds f039f6ab7c6 Try to fix sanitizer-x86_64-linux-fast bot due to change in [...] adds ddcdf84fb2f [X86] Remove ReadAfterLd from BMI and TBM instructions that [...] adds f8f47e0a142 Add msan custom mapping options. adds b18554c1076 AMDGPU: Support realigning stack adds 13e18b3d4bc AMDGPU: Fix build warning in release adds a15b3af3d34 Typo fix: epilouge->epilogue. NFC. adds 84f16940770 [X86] Add ReadAfterLds to some 3 src instructions adds ef267dc8eeb Remove some unneeded #includes to fix layering adds 2dd4f35c7fc llvm-c: Split Utils out of Scalar.h adds 96dbd9b711e Remove unused headers to fix layering adds ede0ca94768 Remove unused header to fix layering. adds 980826ee1c9 Fix some layering in StripNonLineTableDebugInfo, moving its [...] adds 9f3889b501c Style update. NFC. adds ae117790607 [IR] Fix some Clang-tidy modernize-use-auto warnings; other [...] adds 033a78e4eb4 [MachineCopyPropagation] Handle COPY with overlapping source/dest. adds 51feea5bc38 peel loops with runtime small trip counts adds 805514b4e0b [Hexagon] add missing lit config file adds 5488d68d0be [AMDGPU] Fix the SDWA Peephole phase to handle src for dst: [...] adds 4e45b963bcd Revert "[LLVM-C] Finish exception instruction bindings" adds f3407b73c4f [X86] Add tests to verify the presence of "ReadAfterLd" aft [...] adds 39bfbf12ad9 [X86] Add llvm-mca tests for r328834. adds 8b950daaebc [Hexagon] Pass pointer to SelectionDAG to dump functions adds 06b4b9b61ad [X86][BtVer2] Add tests that show how ReadAfterLd is missin [...] adds 70a047dc8d1 [Hexagon] Remove unused scheduling classes adds ec8cdb046d7 [X86][BtVer2] Add missing ReadAfterLd to RM variants of AVX [...] adds 849eeab8996 [Hexagon] Fix flags for store-related intrinsics adds ce765af4ed3 [Hexagon] Fix printing :mem_noshuf on compiler-generated packets adds 208f6d8a9ad [Hexagon] Recognize and handle :endloop01 adds efe1695d460 [SelectionDAG] Removing FABS folding from DAGCombiner adds 936a756969e [AMDGPU] Fixed some instructions latencies adds fa05c349cf5 Revert "peel loops with runtime small trip counts" adds 97f19f4b513 [WebAssembly] Refactor tablegen for store instructions (NFC) adds 21ff13f9ffa [llvm-pdbutil] Dig deeper into the PDB and DBI streams when [...] adds b145b4e996b Fix some signed / unsigned conversion problems. adds fea7778384a [LLVM-C] Finish exception instruction bindings - Round 2 adds e1a4b1753a1 [BlockPlacement] Disable block placement tail duplciation i [...] adds 788c75b81c8 [NVPTX] Enable StructuredCFG for NVPTX adds 292151b43c7 [X86][BtVer2] Fix the number of uOps for horizontal operations. adds eed988e3e72 [MIR] Adding support for Named Virtual Registers in MIR. adds 9541cc2882d DataFlowSanitizer: wrappers of functions with local linkage [...] adds f4abfed4f8d [X86][BtVer2] Fixed the number of micro opcodes for AVX vec [...] adds 5a53d2f60d4 [Hexagon] Avoid creating invalid offsets in packetizer adds f3e8da15323 [Hexagon] Reduce excessive indentation in .s output adds f9ed6325647 [Hexagon] Fix testcase adds 95561668f06 [WebAssembly] Register wasm passes with the PassRegistry adds 8ee6d989408 Prevent data races in concurrent ThinLTO processes. adds 73d8dbf8062 Fix a bunch of typoes. NFC adds cc2d730bc49 [ThinLTO] Add an option to force summary call edges cold fo [...] adds c60b3d1b11d [X86] Add SchedRW for PMULLD adds a96b9330a2d [MIR-Canon] Adding support for local idempotent instruction [...] adds 1ab1a1257f0 Unbreak the build of the go bindings after r328839. adds ab70130534e Fix trailing whitespace. NFCI. adds c941c47314a [X86][Btver2] Add MMX_PSHUFB to the JWritePSHUFB InstRW entries adds 6906b1fc5de [llvm-rtdyld] Fix the InputFileList cl::opt description: it [...] adds 319a3359618 [DAGCombine] (float)((int) f) --> ftrunc (PR36617) adds ccca812fc34 [Analysis] Change std::sort to llvm::sort in response to r327219 adds 1116feb011f [X86] Remove unneeded temporary variable. NFC adds c41c603aa83 [X86] Add test case to show failure to promote i16 subtract [...] adds 355d9dd2ee3 [X86] Allow i16 subtracts to be promoted if the load is on [...] adds ac43954a9b3 [X86] Add test case to show failure to promote i16 subtract [...] adds 05eb96d0371 [X86] Check if the load and store are to the same pointer b [...] adds 879ec9492f6 [X86] Don't check for folding into a store when deciding if [...] adds a9bfe02006d [LoopRotate] Rotate loops with loop exiting latches adds b1a5bd8ba95 [ThinLTO] Add an import cutoff for debugging/triaging adds 962cbb5d4c7 [DebugInfo] Change std::sort to llvm::sort in response to r327219 adds ae174bc48dc TableGen: More helpful error messages adds 7bf0a7f9621 TableGen: Support Intrinsic values in SearchableTable adds e821893513f AMDGPU: Make getTgtMemIntrinsic table-driven for resource-b [...] adds 2360e2aafa0 AMDGPU: Make isIntrinsicSourceOfDivergence table-driven adds b8bd144ca17 [include] Change std::sort to llvm::sort in response to r327219 adds 4ead3eb1715 [tools] Change std::sort to llvm::sort in response to r327219 adds 4804b201844 [x86] Expose more of the condition conversion routines in t [...] adds 2af5683048c [x86] Correct the operand structure of the ADOX instruction. adds 37e281f4902 [X86] Give ADC8/16/32/64mi the same scheduling information [...] adds ed7a017b99e [LegacyPassManager] Make 'print-module-scope' cl::Hidden li [...] adds 83a5c73d5ad [DebugCounter] Make -debug-counter cl::Hidden. adds daca222ef11 [AArch64] Reserve x18 register on Fuchsia adds 6ce22ba1dea [X86] Cleanup ADCX/ADOX instruction definitions. adds 80548aa3fb9 Add C API bindings for DIBuilder 'Type' APIs adds b8e9a739330 [X86] Give VINSERTPS the same intinerary as INSERTPS. adds 19ed08a00dd [X86] Make sure all the classes declare in the Haswell sche [...] adds 8b17c46f759 [X86] Add an itinerary to BTR64rr. adds d8156bdb482 Remove a few unreferenced config.h defines. adds aa66dbe530b [X86] Give the AVX512 VEXTRACT instructions the same SchedR [...] adds 0036663aecd [X86] Fix the SchedRW for AVX512 shift instructions. adds d9e6efc2fb5 [X86] Correct the throughput for divide instructions in San [...] adds 1936d3b892e [X86][SkylakeServer] Correct throughput for 512-bit sqrt an [...] adds 1ad5730bb97 [X86][Silvermont] Use correct latency and throughput inform [...] adds 504cea34c9d Wdocumentation fixes. NFCI. adds 7da9d9fc7ea Wdocumentation fix. NFCI. adds 67eb8fdbb03 [dsymutil] Upstream emitting of papertrail warnings. adds 0a9e4fe67e2 [PowerPC] fix assertion failure due to missing instruction [...] adds 62905805b19 Assume existence of inttypes.h and stdint.h in DataTypes.h. adds 7d1af99a866 Attempt to fix papertrail-warnings.test on Windows bots. adds e509ab0cbdd [llvm-mca] Do not assume that implicit reads cannot be asso [...] adds 3c03a2ac26c [X86] Reduce Store Forward Block issues in HW - Recommit af [...] adds bf59921ab63 Attempt to heal bots after r328970. adds ddc3770228a [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* i [...] adds b5959d3df99 More fixes after r328970. adds 2c8ee39b1ab Remove HAVE_WRITEV that's unused after r255837. adds 58ab7f7e03d Revert r328975, it makes TableGen assert on the bots. adds f38a3ac0efe Remove stro(u?)ll() config checks. Those were needed pre-MS [...] adds 66167879599 [SLP] Fix PR36481: vectorize reassociated instructions. adds e019cdef75c [Hexagon] Clean up some code in HexagonAsmPrinter, NFC adds eb4d4bc552c [AMDGPU][MC][GFX9] Added s_atomic_* and s_buffer_atomic_* i [...] adds 78cbb42d451 [coroutines] Add support for llvm.coro.noop intrinsics adds 6c25c75a694 [AMDGPU][MC][GFX9] Added instructions v_cvt_norm_*16_f16, v [...] adds b96411e4290 Remove HAVE_DIRENT_H. adds 282ca2a3b13 [DeadArgumentElim] Clone function level metadatas adds bdcaabb3284 Remove HAVE_LIBPSAPI, HAVE_SHELL32. adds 8b6b6cca6f8 Remove more feature test macros that became unused after r328989. adds 46dda154fc4 Remove some unused cmake standard library includes. adds 6eda33795aa Remove unused PACKAGE_TARNAME; looks like a remnant of the [...] adds 55ff94d9d70 [llvm-pdbutil] Add an export subcommand. adds a21e8162163 Fix header mismatch in DIBuilder Type APIs adds 9b666b71a3d Another attempt to fix papertrail-warnings.test on Windows [...] adds 4e5dad45d62 [InstCombine] add tests for icmp (sub x, y), x (PR36969); NFC adds 01621ff0d61 [InstCombine] add folds for icmp + sub (PR36969) adds dd9d04ad20e [lit] Fix problem in how Python versions open files with di [...] adds 73bcd8b27c5 [ORC] Create a new SymbolStringPool by default in Execution [...] adds 543b638e890 Treat inlining a notail call as a regular, non-tail call adds edd8b7e9b44 Revert r329012 "[lit] Fix problem in how Python versions op [...] adds 9b17e6e1c49 [ORC] Fix a think-o: ExecutionSession should create a Symbo [...] adds eee57fe80c7 [ORC] Add a debugging check to catch dangling references to [...] adds fc78d747e49 [lit] Use io.open to compare two files since it supports di [...] adds 755a2196409 Fix Go IR test for changes in DIBuilder API adds 9bfeee1032d [lit] Fix problem in how Python versions open files with di [...] adds 8ba111aa98d [lit] Attempt to fix builtin diff code for Python 2 adds 4c227240471 [lit] One more try at fixing TestRunner.py for D43165 adds bc963136e0c [InstCombine] Don't strip function type casts from musttail calls adds 8456cd08ba6 Remove llvm-mcmarkup. adds aa2d256782e Align stubs for external and common global variables to poi [...] adds 64543f4027f [Coroutines] Avoid assert splitting hidden coros adds 2784c35c0ff [SLP] Distinguish "demanded and shrinkable" from "demanded [...] adds ad2e39fd2ef [lit] Prefer opening files with open (Python 2) rather than [...] adds bab9d7badc3 [x86] Tidy up test case, generate check lines with script. NFC. adds b6d2b999776 Remove utils/makellvm; it doesn't look like it works with c [...] adds 746a5dcae63 peel loops with runtime small trip counts adds 86ab905c1d5 bpf: fix incorrect SELECT_CC lowering adds 9c72aec7a1c [TableGen] Use llvm::cast instead of static_cast so that th [...] adds 8b74007e1a3 [SLP] Fix issues with debug output in the SLP vectorizer. adds 023c8be9098 [SCEV] Make computeExitLimit more simple and more powerful adds e02284bdf8f [X86][TableGen] Add a missing error check to make sure EVEX [...] adds 16fa9066bac [X86] Reduce number of OpPrefix bits in TSFlags to 2. NFCI adds e6866b5e186 Add a wrapper around llvm-objdump to look for indirect call [...] adds 0bbc0393d89 [SCEV] Fix PR36974. adds a05cf8130c4 MSan: introduce the conservative assembly handling mode. adds 6f46178ea56 [x86] Extend my goofy SP offset scrubbing for llc test case [...] adds 18ceb931fd6 [x86] Clean up and enhance a test around eflags copying. adds 7e78daafdd2 [x86] Fix a pretty obvious think-o with my asm scrubbing. Y [...] adds 68fe43ca75e [PowerPC] reorder entries in P9InstrResources.td in alphabe [...] adds 84dd0b3fad1 [LangRef] fix description and examples of fptrunc adds ce79db62546 [MC][Tablegen] Allow the definition of processor register f [...] adds 46750809c86 [MC] Fix -Wmissing-field-initializer warning after r329067. adds 4832f865cf8 Revert "[SLP] Fix PR36481: vectorize reassociated instructions." adds 3274d703cee [llvm-mca] Remove redundant include from BackendStatistics.h. NFC adds 521c4d76e14 Adding optional Name parameter to createVirtualRegister and [...] adds 22950265a56 [Hexagon] Remove unneeded attributes from lit test adds 8d244e6d301 [Hexagon] Remove -mhvx-double and the corresponding subtarg [...] adds 0b1a72a7a60 [SLP] Added tests for checks of reordering of the repeated [...] adds f67d85620bf [LoopInterchange] Update tests so DA can handle access afte [...] adds b09f726df5f Recommit "[SLP] Fix issues with debug output in the SLP vec [...] adds 6ea791d917a [llvm-mca] Move the logic that prints register file statist [...] adds d54820bbe6e Remove a stale comment cut and pasted from another file. adds 91811bc4887 [SLP] Fix PR36481: vectorize reassociated instructions. adds 36d6cce30a6 [InstCombine] Fold compare of int constant against a splatt [...] adds d88368c7999 [DEBUGINFO] Add option that allows to disable emission of f [...] adds 4785e67b24a [SLP] Fixed formatting, NFC. adds 2f039a02f36 [dsymutil] Apply recursion workaround for threading adds c23bb98c0a8 [CodeGen]Add NoVRegs property on PostRASink and ShrinkWrap adds e1216df7bc5 Disable a test using environment variables that requires a [...] adds 8c6709f8ef0 [x86] add tests for convert-FP-to-integer with constants; NFC adds 1ad09de0932 [DebugInfoPDB] Add a few missing definitions to PDBTypes.h adds 126346798cf [DebugInfoPDB] Add methods used to read function flags adds 45013b2e671 Add the ShadowCallStack attribute adds e37502533bc [LoopInterchange] Add remark for calls preventing interchanging. adds d36a0f0f415 [coroutines] Respect alloca alignment requirements when bui [...] adds 9a0ce889d1c MSG adds 4831763daab [MachineOutliner][NFC] Make outlined functions have interna [...] adds fa13e5dd1db Fix bad copy-and-paste in r329108 adds d82ffe5dae5 Revert "MSG" adds 5d2f4dba66d [MachineOutliner] Keep track of fns that use a redzone in A [...] adds e0ab896a84b [InstCombine] allow more fmul folds with 'reassoc' adds b9d814c061f 'cat' command for internal shell - Support Python 3 adds 7c6b96497bb [Hexagon] peel loops with runtime small trip counts adds e5e59983504 [AArch64] Adjust the cost model for Exynos M3 adds a59291c1f6b [AMDGPU] performMinMaxCombine should not optimize patterns [...] adds 719cff5ce74 [RuntimeDyld][AArch64] Add some error pluming / generation [...] adds ddbccbd6f67 [MachineOutliner] Test for X86FI->getUsesRedZone() as well [...] adds 69ec7d5667e Revert r329133 "[RuntimeDyld][AArch64] Add some error plumi [...] adds 415892df80a Reapply r329133 with fix. adds ee9345b6593 Minor no-op cmake file style fix. adds 484fd96051f Add the ShadowCallStack pass adds d42d9e83aeb Fix bad #include path in r329139 adds bc032eba1ea [SimplifyCFG] Teach merge conditional stores to handle case [...] adds e22b899f649 [X86] Remove some code that was only needed when i1 was a l [...] adds 14b82ee56b4 [X86] Remove dead code for handling i8/i16 UMUL_LOHI/SMUL_L [...] adds 30f73251629 [SCEV] Prove implications for SCEVUnknown Phis adds 74ed70f44d1 [X86] Remove more dead code left over from the handling of [...] adds 9b44f71fb55 [X86] Use loadi16/loadi32 predicates in multiply patterns adds 0376d42275e [X86] Use the same predicate for the load for PMOVSXBQ and [...] adds 780c045964b Add llvm-exegesis tool. adds fb12c072df6 Revert r329156 "Add llvm-exegesis tool." adds 4634fe0cb4b [ARM] Do not convert some vmov instructions adds 9b4235c03c5 [DAGCombine] Improve ReduceLoadWidth for SRL adds 107f6100d79 [AArch64] Add patterns matching (fabs (fsub x y)) to (fabd x y) adds 126cd7e831c AMDGPU: Fix copying i1 value out of loop with non-uniform exit adds 036d645a4c8 StructurizeCFG: Test for branch divergence correctly adds 83bfebdaca8 AMDGPU: Dimension-aware image intrinsics adds 1fbc6fa39c7 [X86][CostModel] Use generic SSE levels instead of particul [...] adds fd68be2418c Re-land r329156 "Add llvm-exegesis tool." adds ab9704d95e1 Make helpers static. NFC. adds d14f88d9ca0 [llvm-exegesis] Fix compilation on some clang versions. adds 215782466af [llvm-exegesis] Fix build when libpfm is not available. adds 375e65967de [Tablegen] Slightly refactor method SubtargetEmitter::EmitE [...] adds 527bfb075c7 [llvm-exegesis][NFC] Fix a few warnings. adds 9434ee2f2ef [llvm-exegesis][NFC] Fix compilation warning. adds c07488664c0 [llvm-exegesis] Fix compilation on lld-x86_64-darwin13 adds fdbb56de7e5 [llvm-exegesis] Do not initialize FileDescriptor when libpf [...] adds a3a182263ca Remove duplicate tablegen lines from AVR target. adds 7e97238dd7a [CodeGen] Generate DWARF v5 Accelerator Tables adds 2141b4692fc Sort targetgen calls in lib/Target/*/CMakeLists. adds f1dc3c2a1f6 Attempt to fix bots after r329179. adds 5f42950f9ab [llvm-exegesis] Add missing link libraries. adds 5f1314ce9f6 Attempt to fix bots more after r329179. adds 112f4caf3f4 [AMDGPU][MC] Added support of 3-element addresses for MIMG [...] adds c5e0b13c3b6 Add AMDPAL Code Conventions section to AMD docs adds f72ca59cae2 Revert r329179 (and follow-up unsuccessful fix attempts 329 [...] adds 36c8c500bd4 Remove llvm-build's --write-make-fragment which looks like [...] adds 4d0328dce33 [X86][Btver2] Strip unnecessary check prefixes from resourc [...] adds 5b50e479b0a [llvm-exegesis] Only run unit tests on x86_64 hosts. adds 4171cb34e0f [llvm-exegesis] Temporarily disable some tests. adds 54d7a0223b4 [SLPVectorizer][X86] Regenerate some tests. NFCI adds 1669069e0ac [AMDGPU][MC] Enabled instruction TBUFFER_LOAD_FORMAT_XYZ for SI/CI adds 84f5a1e93ea [InstCombine] [NFC] Add tests for getting rid of select of [...] adds f73cdf9fe26 [llvm-exegesis] Temporarily disable a few tests. adds 3fb0112ac22 Re-commit r329179 after fixing build&test issues adds 0e5d6b26409 Fix build breakage from r329201 adds 200eeca319d [Power9]Legalize and emit code for quad-precision fma instructions adds 06e4df3aff4 [llvm-pdbutil] Add the ability to explain binary files. adds a2c231364c6 Fix a compilation failure with non MSVC compilers. adds 84038c4e882 [X86] Separate BSWAP32r and BSWAP64r scheduling data in San [...] adds 5c458ee2a90 [MachineOutliner] Fix typo; NFC adds bee3bbd9bdd [Analysis] Support aligned new/delete functions. adds 7a9e40f0e9d [AArch64] Change std::sort to llvm::sort in response to r327219 adds b9f31323a69 Revert "[Analysis] Support aligned new/delete functions." adds 75627b1a254 [Analysis] Support aligned new/delete functions. adds 7d72684477e [MachineOutliner] Add `useMachineOutliner` target hook adds b7b2c0a7bb3 hwasan: add -hwasan-match-all-tag flag adds cc96568d892 [MemorySSA] Fix spelling errors in MemorySSA.cpp. NFC adds e9567627a27 Don't inline @llvm.icall.branch.funnel adds 70bca66be3b AArch64: Implement support for the shadowcallstack attribute. adds 5539442a8f8 [WebAssembly] Only write 32-bits for WebAssembly::OPERAND_OFFSET32 adds 29bc6472deb [MIR-Canon] Adding support for multi-def -> user distance r [...] adds a7f9b6aaade [MIR-Canon] Improving performance by switching to named vregs. adds 7d9ae75740d [IR] Upgrade comment token in objc retain release marker adds 65834ee9b57 [gold] Add debug-pass-manager option, and use it to test ne [...] adds 68c702b4eeb [CallSiteSplitting] Do not perform callsite splitting insid [...] adds 224b7027524 [X86] Auto-generate complete checks. NFC adds d4b8b33a93d [X86] Remove some InstRWs for plain store instructions on S [...] adds 8e06c705058 [X86] Use WriteFShuffle256 for VEXTRACTF128 to be consisten [...] adds 67c388f5a13 [X86] Synchronize the SchedRW on some EVEX instructions wit [...] adds 19636dfbd89 [X86] Revert r329251-329254 adds c1c024f375f [llvm-exegesis] Suppress a warning. adds 1fb4289a132 [MIR-Canon] Fixing warnings in Non-assert builds. adds 88fe9bccd85 [llvm-exegesis] Check for libpfm headers. adds 8caab7da3f8 [UpdateTestChecks] Remove unnecessary return from add_ir_checks adds 49d9dfff54d [LoopInterchange] Preserve LoopInfo after interchanging. adds a9e09241ca0 [UpdateTestChecks] Make add_asm_checks more like add_ir_checks adds 90e863357da [UpdateTestChecks] Split core functionality of add_ir_check [...] adds 46d5e2b4515 allow custom OptBisect classes set to LLVMContext adds 60da41d8b56 [mips] Regenerate test before posting patch for constant mu [...] adds af1e56959c2 [LoopInterchange] Add stats counter for number of interchan [...] adds 93c47434af5 [UpdateTestChecks] Moved core functionality of add_asm_chec [...] adds ff02230cf50 [Plugins] Add a slim plugin API to work together with the new PM adds 370e64a807e [llvm-mca] Remove flag -max-retire-per-cycle, and update the docs. adds a4419a604ed Revert "[Plugins] Add a slim plugin API to work together wi [...] adds 3338e445922 Minor fix in docs. adds 716261ba052 [LoopInterchange] Require asserts for test using -stats (NFC) adds 00a96df3a57 [SchedModel] Complete models shouldn't match against itiner [...] adds 7d31ac84157 [InstCombine] cleanup; NFC adds b326c6e97a3 [DAGCombine] Revert r329160 adds 166f95ee2b0 [MC] Fix spaces between values printed by EmitRegisterFileInfo. adds dce7fb08a0d [Lexicon] Add "ICE", internal compiler error adds 1cdf10abfa3 [Hexagon] Remove default values from lambda parameters adds 1444c19a6b8 ARM: Do not spill CSR to stack on entry to noreturn functions adds 9042a61f9ba [Testing/Support]: Better matching of Error failure states adds 530167710b9 Re-land r329273: [Plugins] Add a slim plugin API to work to [...] adds 92c0e782b00 [InstCombine] add vector and vector undef tests for FP folds; NFC adds b3b089c2c5c [PowerPC] fix assertion failure due to missing instruction [...] adds 02f3e0be784 [PatternMatch] define m_FNeg using m_FSub adds 8c6c51699f8 [MC][Tablegen] Allow models to describe the retire control [...] adds 39903ab821b Fix the buildbots after r329304. adds f7c52db82e9 Fix r329293: Add a missing CMake dependency adds 0122eda6e97 [X86] Use WriteFShuffle256 for VEXTRACTF128 to be consisten [...] adds 14cfc65a1c5 [documentation][llvm-mca] Update the documentation. adds 6fbc0600513 [InstCombine] add tests for fsub --> fadd; NFC adds 13c09234d66 [WebAssembly] Allow for the creation of user-defined custom [...] adds 4736168ad53 [InstCombine] use pattern matchers for fsub --> fadd folds adds b67bfb9b9eb Another fix for r329293: Unbreak the windows bots adds 34841016c30 [X86][SSE] Add integer min/max vector.reduce tests adds f096c30c1e1 [X86][SSE] Add integer and/or/xor vector.reduce tests adds f614f36c690 [X86][SSE] Add integer add/mul vector.reduce tests adds 13f8aabe0de [InstCombine] add test for fneg+fsub with nsz; NFC adds 8947d93c99b llvm-exegesis: Fix unittests include dirs when llvm is a pa [...] adds 5ea14cb969e [llvm-pdbutil] Display types from MSVC precompiled header o [...] adds b3ec9a18424 [X86] Disassembler support for having an ADSIZE prefix affe [...] adds 205cff10183 [ARM] Change std::sort to llvm::sort in response to r327219 adds 8f85f224b95 [X86] Synchronize the SchedRW on some EVEX instructions wit [...] adds ef973e5f0a5 [InstCombine] Properly change GEP type when reassociating l [...] adds b6697c1e8f6 [Bitcode] Change std::sort to llvm::sort in response to r327219 adds 433eb70569e [RuntimeDyld][PowerPC] Use global entry points for calls be [...] adds 2cb4aedc1e1 [llvm-cov] Prevent llvm-cov from hanging when a symblink do [...] adds b49f64bf05e [X86] Remove some InstRWs for plain store instructions on S [...] adds ae3b2037b4a AMDGPU/Metadata: Always report a fixed number of hidden arguments adds 23bf3d86bae [X86][SSE] Add floating point min/max vector.reduce tests adds 62cc26416dc [X86][SSE] Add floating point add/mul fast-math vector.redu [...] adds 57bcc004a15 [DWARF v5][NFC]: Refactor DebugRnglists to prepare for the [...] adds f828e9316d4 [X86] Add LEAVE instruction to the scheduler models using t [...] adds 3e2bf90543f [InstCombine] [NFC] Add more tests for getting rid of selec [...] adds c6db24a1e00 [InstCombine][NFC] Regenerate select-of-bittest.ll with ins [...] adds bd62cc1c783 [InstCombine] nsz: -(X - Y) --> Y - X adds d5783cbc203 [X86] Add MOVZPQILo2PQIrr to the Sandy Bridge scheduler model adds 6a7cae6e89c [IR] Change std::sort to llvm::sort in response to r327219 adds efb0b0966de [X86] Separate CDQ and CDQE in the scheduler model. adds 396d590dbf7 [RuntimeDyld][PowerPC] Add a test case for r329335. adds 32d2ff0d0ff X86 Tests: Add a case for combining sdiv by a splatted pow2 [...] adds 55b03d26691 Attempt to fix Mips breakages. adds 797d5a92c6f [InstCombine] add FP tests for Z - (X - Y); NFC adds 06426a9f213 [InstCombine] FP: Z - (X - Y) --> Z + (Y - X) adds eb98fdedc02 Fix lld-x86_64-darwin13 build fails. adds ca7fd00a115 Update method names in documentation. adds e563ac372a6 [LLVM-C] Audit Inline Assembly APIs for Consistency adds 905f35003d0 [LLVM-C] Fill Out LLVMCallConv adds bbe1d513213 [PowerPC] allow D-form VSX load/store when accessing FrameI [...] adds ce9e75e4f29 [NFC] Loosen restriction on preheader to fix buildbot adds 5d5541e6df5 [debug_loc] Fix typo in DWARFExpression constructor adds 995c80d5116 [MIR] Add support for MachineFrameInfo::LocalFrameSize adds deaebefed8d [NFC] Add missing end of line symbols adds 5f10dae16e0 EntryExitInstrumenter: Handle musttail calls adds fe282cd3978 [X86][SkylakeServer] Merge 2 InstRW entries to the same sch [...] adds 2d9c75def2d Tweak an assert message in the verifier adds 770176590e3 [X86][SandyBridge] SBWriteResPair +5cy Memory Folds adds ef254f546ca [X86][SandyBridge] Add (V)DPPS memory fold latencies adds d79c539c3b0 [UpdateTestChecks] Add update_analyze_test_checks.py for co [...] adds 2f81443ddba DWARFVerifier: validate information in name index entries adds 535a822315a Followup for r329293: Temporarily disable the breaking test [...] adds 15b5be3513a [LoopUnroll] Make LoopPeeling respect the AllowPeeling preference. adds bf596a2e06d [AMDGPU][MC][GFX9] Added s_dcache_discard* instructions adds 13f7056389c [CostModel][X86] Regenerate int<->fp cost tests with update [...] adds 873c2f82eb1 [CostModel][X86] Regenerate vector shift cost tests with up [...] adds 46037d2543c [CostModel][X86] Regenerate integer division/remainder test [...] adds 8e98b842553 [CostModel][X86] Regenerate integer extension/truncation co [...] adds 05de7ec01ba [llvm-mca] Do not separate iterations with a newline in the [...] adds 029b9c23255 [ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}. adds 5f3a8825937 [CostModel][X86] Regenerate bswap/bitreverse cost tests wit [...] adds 730ed467c72 [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions adds 85b0c0c8f0c [GlobalOpt] Fix support for casts in ctors. adds 2f648b3d190 [CostModel][X86] Regenerate vector shuffle cost tests with [...] adds 1c1630d37c4 [InstCombine] add potential calloc tests and regenerate che [...] adds b41985cc636 [CostModel][X86] Regenerate bit count cost tests with updat [...] adds b4cde9307b5 [X86] Merge itineraries for CLC, CMC, and STC. adds 5a864681b87 [X86] Add an extra store address cycle to WriteRMW in the S [...] adds 11ac674b8a2 [X86] Attempt to model basic arithmetic instructions in the [...] adds 7261c3dd260 [X86] Remove InstRWs for basic arithmetic instructions from [...] adds 3a4f359302b [InstCombine] add test for fsub+fneg with extra use; NFC adds 04f5112d699 [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* [...] adds 4f4a276183f Strip trailing whitespace. NFCI. adds ab046bb4b58 [X686] Add appropriate ReadAfterLd for the register input t [...] adds 2c234f45f37 Add additional tests from D45366 adds c9b7ea3e571 Add additional tests from D45336 adds d637812084f [InstCombine] limit nsz: -(X - Y) --> Y - X to hasOneUse() adds a708d8da8f7 [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done adds 40c42b960ff Cleanup Reduction helpers by using ArrayRef(NoneType) const [...] adds 65256d7e66b [Hexagon] Handle subregisters when calculating iteration co [...] adds 8ba42a9352f [CodeGen] Change std::sort to llvm::sort in response to r327219 adds 4cfd5377662 [Hexagon] Remove duplicated code, NFC adds 5a211dfa548 [Hexagon] Prevent a stall across zero-latency instructions [...] adds 79debc50372 [Hexagon] Fix assert with packetizing IMPLICIT_DEF instructions adds 7ba710792a7 [AMDGPU][MC][GFX9] Added s_call_b64 adds 54a02055fc7 [RISCV] Update MC compression tests adds 0f09c5e66ad [EarlyCSE] Add debug counter for debugging mis-optimizations. NFC. adds 41a887af5a8 [StackProtector] Ignore certain intrinsics when calculating [...] adds 351641203ef [TableGen] Change std::sort to llvm::sort in response to r327219 adds 839cd7ff05c [RISCV] Tablegen-driven Instruction Compression. adds 05471bb6215 [NVPTX] Fixed vectorized LDG for f16. adds e37ea5686ed [Release Notes] Add release note for "-fmerge-all-constants" adds 7edf726dc36 Revert r324557, "gold-plugin: Do not set codegen opt level [...] adds b67d0963889 Runtime flag to control branch funnel threshold adds af98dad7c6c Fix warning by cl::opt<int> -> cl::opt<unsigned> adds 08846e25c57 [NVPTX] add support for initializing fp16 arrays. adds 1a2fa8de07d [lit] Fix several Python 2/3 compatibility issues and tests adds d1d162f3a76 Windows needs the current codepage instead of utf8 sometimes adds 141766acc5e [Support] Make line-number cache robust against access patterns. adds 77a1dcd15bc [unittests] Change std::sort to llvm::sort in response to r327219 adds 9387b390483 Remove trailing space in build file. adds 23bbcacac9f Convert line endings of lib/WindowsManifest/CMakeLists.txt [...] adds 38738ec786e Revert "ARM: Do not spill CSR to stack on entry to noreturn [...] adds bc866fee81d [LLVM-C] Move DIBuilder Bindings For Block Scopes adds 6df5bfeecd3 Fix stack-use-after-scope in test previously hidden by -fme [...] adds 6bc5d6199da [unittests] ADT: silence -Wself-assign diagnostics adds 93f67358758 [InstCombine] Get rid of select of bittest (PR36950 / PR17564) adds f6621a4e4b9 Reapply ARM: Do not spill CSR to stack on entry to noreturn [...] adds 55e0cda310e [llvm-exegesis] Fix unused return value warning and add a u [...] adds d5e5cebeaec [CostModel][X86] Regenerate vector comparison cost tests wi [...] adds 5eeb34e4eee [CostModel][X86] Fix v32i16/v64i8 SETCC costs on AVX512BW targets adds 8ba0797e367 [CostModel][X86] Regenerate silvermont (and added goldmont) [...] adds 43dba22c379 [CostModel][X86] Regenerate vector integer truncation cost [...] adds 4bf25ba9bb5 [InstCombine] add/move tests for fsub folds; NFC adds cc6d45b9728 [CostModel][X86] Regenerate vector select cost tests with u [...] adds a42e034bfcb [InstCombine] simplify code that propagates FMF; NFC adds 9c4e19d1272 [CostModel][X86] Regenerate vector reduction cost tests wit [...] adds 5c87b2ea7b2 [llgo] Move SetSubprogram adds ae102799e0a [DAGCombiner] Add a combine to turn a build vector of zero [...] adds 2ec9dcb2637 [X86] Combine vXi64 multiplies to MULDQ/MULUDQ during DAG c [...] adds 6569c392c84 [X86] Regenerate atom pshufb test adds 54c04412a70 Revert "Followup for r329293: Temporarily disable the break [...] adds 5c6d787053e [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst [...] adds 0edb3bf17db [LLVMTestingSupport] Add explicit linkage to LLVMSupport adds 16f832e007b [ADT] Fix MapVector when 'Map::mapped_type != unsigned'. adds 69744893588 [X86][Btver2] Add vector extract costs adds 7ac44f2885a DAGCombiner: Combine SDIV with non-splat vector pow2 divisor adds f83084d53dd NFC: delete ValueMap move ctor adds ca8890ba4c0 [X86][SSE3] Regenerate mwait/monitor intrinsic tests adds 7c5fd26a5fd [X86][PKU] Regenerate rdpkru/wrpkru intrinsic tests adds a1ad6f1ea48 [X86] Regenerate and + immediate mask tests adds c2cdd67e91b [LIR] Reorder header. NFC adds 9b484d4e23d Mark invariant.group as experimental adds 2785576ecbe [llvm-mca] Simplify code. NFC adds 3ffb0582ad5 NFC: Update NewGVN invariant.group test adds 2d13e7fa3ff [X86] Change std::sort to llvm::sort in response to r327219 adds c8f37728d59 [PowerPC] Change std::sort to llvm::sort in response to r327219 adds f717140303d [Support] Change std::sort to llvm::sort in response to r327219 adds 760af163b42 [dsymutil] Don't crash on empty CU adds d5640e4a253 [X86][Znver1] Remove InstRWs for BLENDVPS/PD adds 50cdfb85b9a [X86] Add SchedWrites for CMOV and SETCC. Use them to remov [...] adds e599ceafb83 [TargetSchedule] shrink interface for init(); NFCI adds f65fa6681f4 Remove MachineLoopInfo dependency from AsmPrinter. adds 0379e104e9f [XRay][llvm+clang] Consolidate attribute list files adds de3224bc864 [NFC] fix trivial typos in comments and error message adds 00a6e7d4883 [IRCE] Relax restriction on collected range checks adds 6221e95d979 [X86] Merge some of the autoupgrade handling for masked int [...] adds 3757f28f1d5 [DAGCombine] Improve ReduceLoad for SRL adds 099f934b4f0 [CodeGen/AccelTable]: Don't emit accelerator entries for fu [...] adds d0a066beeef [dsymutil] Don't try to load Swift ASTs as objects. adds fa428dc35d9 [dsymutil] Remove trailing colon. NFC adds a06addf4593 Make the test case from r329552 more portable adds b273503311a [X86][SSE] Fix f32 mul/div itinerary groups typo adds 9b45c7b72d5 [X86][MMX] Fix flipped reg/mem typo in MMX_MISC_FUNC_ITINS adds 4f1ff651c89 [AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl* [...] adds efcfc6694b0 [MergeICmp] Split blocks that do other work. adds fe02712e79f [X86][MMX] Fix missing itinerary for CVTPI2PS adds 44fdd91af04 [X86][MMX] Fix missing itinerary for MOVQ2DQ instruction format adds ce98d4e11bd [X86][MMX] Fix missing itinerary for PALIGNR adds b7158900353 Revert r329403 "[llvm-mca] Do not separate iterations with [...] adds 3c11d1113dc [MergeICmp] Update debug msg.NFC adds eec140da52d [RuntimeDyld][PowerPC] Fix a newly added test in r329355 adds 62bde38843a [CodeGen/AccelTable] Don't emit zero-CU name indexes adds dbec9f78b1a [MachineLICM] Re-enable hoisting of constant stores adds 06fa683388a [llvm-cov] Implement -ignore-filename-regex= option for exc [...] adds 767f692c451 Support generic expansion of ordered vector reduction (PR36732) adds a4c5186fc50 [X86][SSE] Add floating point add/mul strict (ordered) vect [...] adds 70b72706587 AMDGPU: Initialize GlobalISel passes adds aae4cd3ca11 [llvm-mca] Add the ability to mark regions of code for anal [...] adds ad396b6a172 AMDGPU: enable 128-bit for local addr space under an option adds b5f3ce829b8 [llvm-mca] Fix MCACommentConsumer adds 225c6a9d5c1 [X86] Revert the SLM part of r328914. adds b9f22e8394f [GISel] Refactor MachineIRBuilder to allow transformations [...] adds 526e92a9cfb [demangler] Support for partially substituted sizeof.... adds 6b669f18f09 [demangler] Support for <data-member-prefix>. adds 650fe38f580 [demangler] Support for fold expressions. adds 0e32281b0cd Fix type mismatch between MachineMemOperand constructor and [...] adds e6a456223bd [SLP] Additional tests for reorder reuse vectorization, NFC. adds 8c4df1d68dd [X86] Remove GCCBuiltin name from pmuldq/pmuludq intrinsics [...] adds 52da6c57039 [WebAssembly] Change std::sort to llvm::sort in response to [...] adds 83f2acb64b4 Revert "AMDGPU: enable 128-bit for local addr space under a [...] adds c878642f35f AArch64: Allow offsets to be folded into addresses with ELF. adds 2031cf6be1b [Debuginfo][COFF] Minimal serialization support for precomp [...] adds e38ed4d5340 [X86] Don't use Lower512IntUnary to split bitcasts with v32 [...] adds 419eb8a73e9 AMDGPU: Remove max_scratch_backing_memory_byte_size from ke [...] adds b26999a62d6 [MemorySSAUpdater] Mark Phi users of a node being moved as [...] adds 4668d9f5c17 Fix printing of stack id in MachineFrameInfo adds 0b943e2bc42 [globalisel][legalizerinfo] Add support for the Lower actio [...] adds 3a182ea95b1 [X86] Added missing AAD/AAM immediate schedule tests adds e18a176c283 [MemorySSA] Remove redundant assert; NFC adds afd259b0aad [MemorySSA] remove cruft; NFC. adds 8496a2c80f7 [PR16756] Add SSAUpdaterBulk. adds 79081b466d7 [PR16756] Use SSAUpdaterBulk in JumpThreading. adds e29ad6ee1fd [NFC][LV] Move InterleaveInfo from Legal to CostModel adds bc755e2a9cd Fix line endings (CR/LF -> LF) introduced by rL329613 adds ea731cf94c0 [CachePruning] Fix comment about ext4 per-directory file li [...] adds 536a2042513 Fix for the buildbot failure. Now-unused private field TTI [...] adds af04f87166d Revert "[PR16756] Use SSAUpdaterBulk in JumpThreading." adds b6a38e08578 Object: Don't mark alias unconditionally defined adds a379fe24fee ShadowCallStack/x86_64: Ignore pseudo-machine instructions adds 21a0c181743 [x86] Introduce a pass to begin more systematically fixing [...] adds 48f37040ad8 [llvm-ar] Fix lib.exe detection when running within MSVC toolchain adds 789d4d24fe4 [DebugInfo][COFF] Fix reading variable-length encoded records adds 52d8639d489 [SSAUpdaterBulk] Handle CFG with unreachable from entry blocks. adds 134d36e085d Revert "Revert "[PR16756] Use SSAUpdaterBulk in JumpThreading."" adds 4be25bd837d Revert "[PR16756] Use SSAUpdaterBulk in JumpThreading." one [...] adds 307dae5bd1d [X86] Prevent folding loads with 64-bit ANDs with immediate [...] adds 9f8f7c5e8ab [x86] Model the direction flag (DF) separately from the res [...] adds e9d0354ef42 [AArch64][SVE] Asm: Add support for SVE INDEX instructions. adds c486bdf550a [MC][TableGen] Add optional libpfm counter names for ProcResUnits. adds ca9d84f34a6 [MC][TableGen] Fix r329675. adds 76013a8ce6a Reapply "[llvm-mca] Do not separate iterations with a newli [...] adds e2cfc670afe [AArch64][SVE] Asm: Add support for unpredicated LSL/LSR (s [...] adds a95f58008cb [llvm-ar] Temporarily make the tool case detection test Win [...] adds 68f6118901a [X86][Broadwell] HWPort5 should not be added to BroadwellMo [...] adds 5de788a975a AArch64: diagnose unpredictable store-exclusive instructions adds 22c1a157580 [AMDGPU] For OS type AMDPAL, fixed scratch on compute shader adds d3ff090d699 [AArch64] Use FP to access the emergency spill slot adds f660a02ee0b [DA] Improve alias checking in dependence analysis adds 259800c8fc5 [llvm-mca] Increase the default number of iterations to 100. adds 821afa7980b [X86] Disable SGX for Skylake Server adds 67bff146fa3 [Testing/Support] Make Failed() matcher work with abstract [...] adds a678687fabe Fix whitespace indentation. NFCI. adds e6ac37f218f [CodeGen/Dwarf] Rename the "sizetype" synthetic type and ad [...] adds d9438b8809f [pdbutil] Print the checksum hex string when using the '-li [...] adds 955aba4f3b9 [llvm-mca] Move the logic that prints dispatch unit statist [...] adds 22ca1d44c56 Fix spelling. NFC. adds c30400d9d0f [llvm-mca] Simplify code. NFC adds a1f077d97a4 [PDB] Remove dead code and run clang format; NFC adds 9dd59d34c58 AMDGPU/MC: Allow disassembling without symbol info adds 08119504de3 Add missing nullptr check to AArch64MachObjectWriter::recor [...] adds e72f8b8080e Revert r329611, "AArch64: Allow offsets to be folded into a [...] adds b8924a00e7e [CodeGen] Fix printing bundles in MIR output adds 572de6a9d2c Fix test failure in arm64-no-section.ll adds 2e1ebd91ea5 [DebugInfoPDB] Add DIA implementations of findSymbolByRVA a [...] adds 272dbbe783e [llvm-mca] add example workflow for source code adds 538b65888c7 Revert 329716 "Add missing nullptr check before getSection( [...] adds 6592e3d4b59 [llvm-mca] fix formatting adds 15a9f5b86ce [LLVM-C] Add Missing 'break's in InlineAsm bindings adds 30c344c9458 [llvm-mca] reorder text adds 9970be81763 [DebugInfoPDB] Add missing test for findSymbolByRVA and fin [...] adds b8b9efdf7ea [X86] Change the name string for the newly add DF flag regi [...] adds 8eacad4a415 [InstSimplify] fix formatting; NFC adds 681f78964fa [X86] Split up -march=icelake to -client & -server adds 74ef222da21 [AArch64] Fix isel failure when BUILD_PAIR nodes are left over. adds 7b079330a5e [IR] Refactor memtransfer inst classes (NFC) adds 5d7825df151 Recommit r329716 "Add missing nullptr check before getSecti [...] adds e000e64fd84 [IR] Refactor memset inst classes (NFC) adds bba7686b467 [MachO] Emit Weak ReadOnlyWithRel to ConstDataSection adds 368f16bd674 [Verifier] Refactor duplicate code for atomic mem intrinsic [...] adds 2732c9eec9c [CVP] simplify phi with constant incoming values that match [...] adds 71bc0dbf8a7 [AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass. adds 62859f3482b Disable flaky tests till they get fixed. adds 0a5f9fa9c25 AMDGPU: enable 128-bit for local addr space under an option adds 032a6bb59f9 GOTPCREL references must always use RIP. adds 58dfbf03a0f Use contains_lower() instead of find_lower() != StringRef:: [...] adds e9fac8c037c Simplification of libcall like printf->puts must check for [...] adds 4016f71c2db [X86] Switch a test from grep to FileCheck. NFC adds 1c5a9ad72a4 [X86] In X86FlagsCopyLowering, when rewriting a memory setc [...] adds 49b10db743c [X86] Remove 128/256-bit masked pmaddubsw and pmaddwd intri [...] adds 84029d7c96e [CMake][runtimes] Process common options in runtimes build adds a59739cda10 [llvm-exegesis] Add a flag to disable libpfm even if present. adds 9cdaca853be [AArch64][AsmParser] Unify code for parsing Neon/SVE vectors. adds e7bb73e01b1 [Build][NFC] Split off libpfm detection to a separate module. adds 30552b9602d [ARM] FP16 VSEL codegen adds 3227db0643e Eliminate a bitwise 'not' op of 'not' min/max by inverting [...] adds 2d438c016c3 [llvm-mca] Move the logic that prints scheduler statistics [...] adds 900cf755f0a [llvm-mca] Renamed BackendStatistics to RetireControlUnitSt [...] adds ee869a82380 [llvm-mca] Minor code cleanup. NFC adds 3abaf8b1ba6 [AArch64] Fix regression after r329691 adds 7cb386167d6 [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32 adds 4044cf54ae3 [X86][SSE] Tweak cmpps schedule test so that it works prope [...] adds 1a1503b5d3f [AArch64] Add test case for r329797 adds d1e5672c364 [X86] Add variable shuffle schedule classes adds 91c3fd2dd62 [llvm-mca][CMake] Remove unused libraries from set LLVM_LIN [...] adds 4f9dd686235 [AMDGPU] Ensure there are enough registers for wave dispatch adds 3796ce17257 [AArch64][AsmParser] Split index parsing from vector list. adds b7cfdd3ca04 Revert "[AMDGPU] Ensure there are enough registers for wave [...] adds d248c5b3252 Revert "[llvm-mca][CMake] Remove unused libraries from set [...] adds 7a843434af3 [AMDGPU] Fix lowering enqueue_kernel adds 05d18d68a3f [SLP] update a test case. NFC. adds 92ffece4993 [MIPS GlobalISel] Select add i32, i32 adds 0bd082b444c [DWARFv5] Fuss with asm syntax for conveying MD5 checksum. adds eab1e54c67d [InstCombine] limit X - (cast(-Y) --> X + cast(Y) with hasOneUse() adds 1a785071aa5 [FastISel] Disable local value sinking by default adds ebae4b687e9 [DSE] Regenerate tests with update_test_checks.py (NFC) adds 91ebcebf134 [AMDGPU] Ensure there are enough registers for wave dispatch adds d80a410d30d [NVPTX, CUDA] Improved feature constraints on NVPTX target [...] adds 3b79cbb5742 [NVPTX] Removed 'satom' feature which is no longer used. adds f5eabce2716 [X86] Generalize X86PadShortFunction to work with TargetSchedModel adds db8b1f306e8 [llvm-mca] Let the Scheduler notify dispatch stall events c [...] adds 145d22dacc4 [X86][Atom] Convert Atom scheduler model to SchedRW (PR32431) adds 2b8ec282c2f CodeGen: Don't try to canonicalize Unix-style paths in Code [...] adds 29df540b8ea [DSE] Regenerate tests with update_test_checks.py (NFC) adds 461bf527e51 Rename *CommandFlags.def to *CommandFlags.inc adds d6c8a466876 [DSE] Add tests for atomic memory intrinsics (NFC) adds 8822a56047f [X86] Describe wbnoinvd instruction adds 98a5765c03b bpf: signal error instead of silent drop for certain invali [...] adds d85c559bc5b Attempting to work around a non-determinism issue. adds 4cd717c5133 [PowerPC] Fix condition for 64-bit rotate when replacing r+ [...] adds e03c814e571 Don't repeatedly evaluate size() in the for loop. NFCI. adds c7568e5debf [LLVM-C] Add LLVMGetHostCPU{Name,Features}. adds 125b8deb816 X86FoldTableEntry - avoid unnecessary std::string creation. NFCI. adds 66258c98881 Add missing vtable anchors adds ce2202885aa [X86] Remove unused itinerary argument from FMA3/FMA4/XOP i [...] adds 6450f7fb015 [llvm-objcopy] Switch over to using TableGen for parsing arguments adds df0745b92eb [SSAUpdaterBulk] Fix linux bootstrap/sanitizer failures: ex [...] adds b33a02496a4 Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." on [...] adds b1f2b2d1cec Revert "[llvm-objcopy] Switch over to using TableGen for pa [...] adds 6583ea328f5 [DeadArgElim] Remove allocsize attributes on callsites adds 183a800059f Test commit access adds 633653d6d5f [RISCV] Codegen support for RV32D floating point load/store [...] adds 0cc09b82a37 [RISCV] Add tests missed in r329871 adds 3664487a634 [RISCV] Add codegen support for RV32D floating point arithm [...] adds bbb41d83129 [RISCV] Codegen support for RV32D floating point conversion [...] adds 14efaa1e8e7 [RISCV] Codegen support for RV32D floating point comparison [...] adds ef1bc2d3ca7 [NFC] fix trivial typos in documents and comments adds 47d409e1ca6 [LegalizeTypes] Remove unnecessary type action check on the [...] adds a83aa7ca2e2 [MachineScheduler] NFC refactoring adds 273601eded5 [HexagonMachineScheduler] Remove local (copied) getWeakLeft(). adds 19d0394c5ae [SystemZ] Remove FullInstRWOverlapCheck from SchedMachineModels. adds 63fe16971b6 [SystemZ] Use ResourceCycles=30 for FPd unit (NFC). adds 85cae613608 [MIPS GlobalISel] minor update to MIR tests added in r329819 adds d9053c2840f [X86] Remove X87 schedule itineraries (PR37093) adds ca9b26eb14c [llvm-mca] Removed unused argument from cycleEvent. NFC adds d0c7e9cab51 [X86] Remove MMX/3DNow schedule itineraries (PR37093) adds a560b3014f3 [X86] Remove CMOV/SETCC schedule itineraries (PR37093) adds d22316e15b7 [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVC adds c2ed7d8f40a [AArch64][AsmParser] Make parse function for VectorLists ge [...] adds c4f7ab0675f [InstCombine][NFC]: Add tests: foldSelectICmpAndAnd(): and [...] adds a1c77854446 [X86] Remove system/control schedule itineraries (PR37093) adds e671fc896b1 [mips] Correct the predicates for special nops, tlb ctrl in [...] adds d9666f85485 [X86] Remove remaining system/special schedule itineraries [...] adds f09f1560b17 [IRCE] isKnownNonNegative helper function adds 224d0820890 [CodeGen] Allow printing MachineMemOperands with less conte [...] adds 8f825845f3f [AArch64][AsmParser] Unify 'addVectorListOperands' functions. adds 9ef860a3981 Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThread [...] adds 45655ba7823 [X86] Remove AES/CLMUL/CRC32/LDDQU/MOVNT/POPCNT/SHA schedul [...] adds 293041f6905 [mips] Correct the predicates of the load/store (double)wor [...] adds f0086dd6e31 [Pipeliner] Use std::stable_sort when ordering NodeSets adds b7ab0ed2197 revert r328921 - [DAGCombine] (float)((int) f) --> ftrunc ( [...] adds fd7ac552112 [AArch64] Move AFI->setRedZone(false) to top of emitPrologue adds 91e3c3b9cc5 [MIPS GlobalISel] remove superfluous #includes (NFC) adds 6724658f850 [MCJIT] Remove the anchor from mcjit. adds d018c5d7470 [Power9]Legalize and emit code for converting (Un)Signed DW [...] adds 7fa9c2f937d [X86] Remove gpr shift/extension schedule itineraries (PR37093) adds 741d7afdf12 [ORC] Plumb error notifications through the VSO interface. adds e2da0553ce0 Fix a typo in a comment; NFC adds 2d0d5db8e32 [X86] Introduce LLVM wbinvd intrinsic adds 5ae5e878035 [X86] Remove remaining gpr schedule itineraries (PR37093) adds b5070227476 [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0 adds 9da2acfea0c [X86] Remove explicit SSE/AVX schedule itineraries from def [...] adds 54ee51b2fb8 Simplify; NFCI adds 4eb94074a00 [ORC] Use insert rather than emplace. adds b5878be24a0 [X86] Remove InstrItinClass entries from SSE/AVX instructio [...] adds b068ce98cd5 [WebAssembly] libObject: Don't include the name the size of [...] adds 87bdde82ce5 [demangler] NFC: Some refactoring to support partial demangling. adds d0381b68b85 [demangler] Add a partial demangling API for LLDB. adds 1e4cb86baca [X86] Remove InstrItinClass entries from all x86 instructio [...] adds a8d61ae2cdb [ProfileSummary] Move a vector we're about to destroy anyway; NFC adds 85af7e11586 [DebugInfo] Create merged locations for instructions other [...] adds 2ee1645a3ea AArch64: Introduce a DAG combine for folding offsets into a [...] adds 90aa47d144a Let llvm-diff correctly deal with Undef/ConstantAggregateZe [...] adds 83fdf54cf32 [ProfileSummary] Remove repeated cutoffs; NFCI adds 0352abc588c Don't call skipModule for CFI lowering passes. adds a42d068725d [PowerPC] add fsub-fneg test; NFC adds c2943f0710c [DAGCombiner] simplify code; NFC adds 2d3e15f509f [CachePruning] Clarify the per-directory entry limit on Lin [...] adds beaf255480e [X86] Remove x86 InstrItinClass entries (PR37093) adds a51cdcd3c82 Free a pointer, fix a bot. adds 09ca2d92af4 [X86] Remove unused MoveLoadStoreItins/ShiftOpndItins sched [...] adds bc9d7d361f9 [lit] Remove duplicate to_string method adds f0a27cc4ccf [AMDGPU] Update relocation record description adds ed0af08f685 Fix another bot failure from r329951. adds bed2fc33e05 [CallSiteSplit] Fix comment. NFC adds edd00e40e68 Enable debug fission for thinLTO linked via gold-plugin adds 754a558235b [X86] Remove the pmuldq/pmuldq intrinsics and replace with [...] adds 4f9163a74d9 [Support] Fix building for Windows on ARM adds 31add1057f7 [X86] Introduce cldemote instruction adds 15535accd9e [AArch64][SVE] Asm: Add support for parsing and printing SV [...] adds 9f6d594268d [InstCombine]: foldSelectICmpAndAnd(): and is commutative adds 175ae4de8ec [InstCombine][NFC] Add tests for masked merge folding. adds 7dc3d5f99ac [NFC] fix trivial typos in comments adds 47df3d352ba [InstCombine][NFC] Add last few tests with constant mask fo [...] adds 982445c2a2a [llvm-exegesis] Run unit tests on more platforms. adds 7f6ed303605 Partially revert r330008. adds 5ad3e91517e [NEON] Support intrinsic for scalar and vector versions of [...] adds 3615c167adb [X86] Remove OpndItins/SizeItins from all sse instruction d [...] adds 7d9ab967e98 [AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) [...] adds a0c1588192c [llvm-exegesis] Create test files in temporary directory. adds b86299ad280 [InstCombine][NFC] Regenerate logical-select.ll test adds 13bac7c13d6 [PostRASink]Add register dependency check for implicit operands adds 2ebff131899 Remove out of data comment. NFCI. adds 89eb2f73415 [llvm-exegesis][NFC] Add more logging in case target creati [...] adds 43c4e4a682b Remove comment references to itineraries. NFCI. adds faa78cf0541 [X86] Remove remaining OpndItins/SizeItins from all instruc [...] adds 9a2e6e5e410 [X86][AVX512] UNPCKL/H PS and PD should be scheduled with W [...] adds bb755986cfa [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+imm) [...] adds 6d335d78426 Remove comment reference to itineraries. NFCI. adds 5031ac2c1dc [llvm-exegesis] Fix use after free. adds c70bdbc4bec [llvm-exegesis] re-enable failing tests after r330026. adds 68526467977 [profile] Fix binary format reader error propagation. adds 18b893f077b [X86] Generalize X86FixupLEAs to work with TargetSchedModel adds 8b2b901a7e1 [ARC] Add LImm support for J/JL adds a2ce47d27d2 [llvm-mca] Ensure that instructions with a schedule read-ad [...] adds 6bda3ad7207 Revert r330027: "[llvm-exegesis] re-enable failing tests af [...] adds b69d7e5c93a [ARM] FP16 vmaxnm/vminnm scalar instructions adds cef8ffa7205 [X86] Remove remaining itinerary support from instructions [...] adds 4467b4ce957 [mips] Materialize constants for multiplication adds 24b0700a49f Add PPC64_GLINK dynamic tag. adds c83336053fb [InstCombine][NFC] masked-merge: commutativity tests: ensur [...] adds 275d90b83cc hwasan: add -fsanitize=kernel-hwaddress flag adds 0b9d56a30ed Define InitLLVM to do common initialization all at once. adds 8a10d1ef106 [CostModel][X86] Regenerate masked intrinsic cost tests adds 7a7d602cc95 [CostModel][X86] Regenerate cast conversion cost tests adds 069de1ba377 [CostModel][X86] Regenerate latency/codesize cost tests adds bfe1c281d2c [LTO] Change std::sort to llvm::sort in response to r327219 adds 4cba8e9e908 [CostModel][X86] Split fma arith costs tests from other fp tests adds 58f4dfd1782 [CostModel][X86] Add some specific cpu targets to the cost models adds 74fc0f2259d [ProfileData] Change std::sort to llvm::sort in response to [...] adds 648f7eaefcf [MC] Change std::sort to llvm::sort in response to r327219 adds 15ff8cad10e [Transforms] Change std::sort to llvm::sort in response to r327219 adds 2782d619561 [Power9] Add the TLS store instructions to the Power 9 model adds a1a50c559e5 [DebugInfo] Change std::sort to llvm::sort in response to r327219 adds c6388fd9c7e [LV] Introduce TTI::getMinimumVF adds f5fe7853a06 Revert r329956, "AArch64: Introduce a DAG combine for foldi [...] adds 129fc8ca3cb [Hexagon] Initial instruction cost model for auto-vectorization adds 883750c46eb [DebugInfo][OPT] Fixing a couple of DI duplication bugs of [...] adds 9899cf0e8fb [DebugInfo][OPT] NFC follow-up on "Fixing a couple of DI du [...] adds a68402c36cc [InstCombine][NFC] masked-merge: add 'and' tests, too. adds 3352f5142d6 MachO: trap unreachable instructions adds c4082cf631e [X86] Add the bizarro movsww and movzww mnemonics for the d [...] adds 1076c8db457 [WebAssembly] Fix a bug in MachineBasicBlock::findDebugLoc() call adds efcdcc2677d [AMDGPU] Add gfx902 product names adds c4c17fac464 [NFC] fix trivial typos in document and comments adds 5974c34c37b [X86][MMX] Set PAVG/PHADD/PMIN/PMAX/PSIGN instructions to u [...] adds b5e9b6fb66a [InstCombine] add shift+logic tests (PR37098); NFC adds 932516862f3 [X86] Tests for unsigned saturation downconvert detection. adds cfa414cb849 [InstCombine] Enable Add/Sub simplifications with only 'rea [...] adds 851a7606e92 [X86] Tests for unsigned saturation downconvert detection. adds 5baab4c85c3 [Support] Add convenience functions to WithColor. NFC. adds 0c191c5e264 [DebugInfo] Use WithColor to print errors/warnings adds 68232226c47 NFC: Move ObjectMemoryBuffer to support adds 5365e8b4189 [Support] Extend WithColor helpers adds 7ee1ff5090a [InstCombine] simplify code for distributive property; NFCI adds 42ded2d64e0 [InstCombine] simplify more code for distributive property; NFCI adds 8a7e3a43d62 [DAGCombiner, PowerPC] allow X - (fpext(-Y) --> X + fpext(Y [...] adds b5e23d13a51 [MC] Moved all the remaining logic that computed instructio [...] adds 65f2d885f07 [NFC] ConstantOffsetExtractor::CanTraceInto(): add FIXME: no tests adds 6c24dd34f85 [InstCombine] Simplify 'add' to 'or' if no common bits are set. adds 6b8ddb45965 [SelectionDAG][NFC] haveNoCommonBitsSet(): add FIXME notes adds 7f9e67ce37e [InstCombine] Simplify 'xor' to 'or' if no common bits are set. adds dc50512231e [X86] Use uint32_t instead of unsigned in GetLo32XForm for [...] adds 445c7b1daf7 [X86] Use APInt::isSubsetof instead of APInt::intersects to [...] adds 0692f37fd08 [BasicAA] Return MayAlias for the pointer plus variable off [...] adds d7523760563 Rename ObjectMemoryBuffer to SmallVectorMemoryBuffer; NFCI adds 7088d03292e [AArch64][SVE] Asm: Support for structured LD2 (scalar+imm) [...] adds 0792ef7d6e6 [X86] Introduce archs: goldmont-plus & tremont adds 388ad3d2f7c [NFC][MIR-Canon] clang-format cleanup of Mir Canonicalizer Pass. adds f1f8a6d5369 [MIR-Canon] Adding ISA-Agnostic COPY Folding. adds 73e5c16fba6 [mips] Restrict certain trap instructions for micromipsr6 adds 10fa4a104d6 [MIR-Canon] Fixing a test failure caused by COPY Folding. adds 4a9f0dd8d7d [AArch64][SVE] Asm: Support for structured LD3 (scalar+imm) [...] adds 254172572c9 [LatencyPriorityQueue] The LatencyPriorityQueue class is mi [...] adds b5c81aba2f9 [LatencyPriorityQueue] Fix build: missing override adds a6f285a0ceb [AArch64][SVE] Asm: Support for structured LD4 (scalar+imm) [...] adds 368802e5eb3 [test] Avoid spurious failure in debug-names-find.s. NFC. adds 3210e64b499 [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32 adds 7d7f34a40df [InstCombine] fix formatting; NFC adds 72fc210036d [InstCombine] simplify fneg+fadd folds; NFC adds a97e9991f07 SmallVectorMemoryBuffer: Fix some comments adds 2be99d04c02 [InstCombine] simplify getBinOpsForFactorization(); NFC adds b1bd1633f1a Fix some incorrect fields in our generated PDBs. adds 8af1bad853e [CodeView] Initial support for emitting S_THUNK32 symbols f [...] adds 84d38622bdf Revert "Fix some incorrect fields in our generated PDBs." adds a14fac4e51e Remove faulty assertion in llvm-pdbutil adds a71a379fe7f [Attributes] Fix a bug in AttributeList::get so it can hand [...] adds 1a43e1e1bb7 [InstCombine] simplify code in SimplifyAssociativeOrCommuta [...] adds 2ad02e3f0c6 [NFC] Move verificaiton check for f128 conversion into Lowe [...] adds d7addc5a025 [Hexagon] Turn off flag enabling auto-vectorization adds 3963b7d5e4e [ORC] Merge VSO notifyResolutionFailed and notifyFinalizati [...] adds 08893d364d3 [ORC] Add a MaterializationResponsibility class to track re [...] adds 39a435f255d [SLP] Use getExtractWithExtendCost() to compute the scalar [...] adds 891d17ec5ef [X86] Remove unnecessary -mattr to enable avx512bw when the [...] adds 9a56b66b35c Resubmit "Fix some incorrect fields in our generated PDBs." adds 9d2fcc2bf4a [RISCV] Fix assert message operator adds e9f782a21be [PDB] Correctly use the target machine when writing DBI stream. adds 152533c3236 build: reserve `--color-diagnostics` for lld adds 603f108077e Revert "build: reserve `--color-diagnostics` for lld" adds 622b1d62efb [DebugInfo] Follow-up bug fix on "Fixing a couple of DI dup [...] adds fddfe33105e CODE_OWNERS: Take ownership of C API. adds a306456cafb COFF: Make SectionChunk::Relocs field an ArrayRef. NFCI. adds 753b745329a [IR] Upgrade comment token in objc retain release marker fo [...] adds 11001a689df Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." again. adds 3e304f567cd [SSAUpdaterBulk] Add debug logging. adds 81d982a4add [DAGCombiner] Fix for oss-fuzz bug adds 91a2d6cb9bc [X86] Add FP comparison scheduler classes adds f7a516d335c Revert "Reapply "[PR16756] Use SSAUpdaterBulk in JumpThread [...] adds afb8c1fed21 Fix incorrect choice of callee-saved registers save/restore points adds dc9a6a7dba4 [PowerPC] Mark the BDNZ intrinsic as NoDuplicate adds b397ebf86a2 [LLVM-C] [PR34633] Avoid calling ->dump() methods from LLVMDump*. adds 545ac87e761 [Hexagon] Do not merge initializers for stack and non-stack [...] adds 5e739badeb0 Fix incorrect choice of callee-saved registers save/restore [...] adds ce4966c8335 Revert "Fix incorrect choice of callee-saved registers save [...] adds 872612007fc [X86] Remove -mcpu=skx/knl from some tests and use -mattr instead. adds bc0f0706faf [X86] Remove unnecessary InstRW overrides. Add somes FIXMEs/TODOs. adds de9490f767f [X86] Add separate scheduling class for PSADBW instruction. adds 8995c860d67 [llvm-pdbutil] Dump first section contribution for each module. adds 7f57949cd0d [WebAssembly] Teach fast-isel to gracefully recover from il [...] adds 3e79068e735 Rename sys::Process::GetArgumentVector -> sys::windows::Get [...] adds 51d5ef9dba4 [WebAssembly] Add an assertion for an invalid CFG adds e103a56c469 [XRay] Typed event logging intrinsic adds 832cf6b7961 LoadStoreVectorizer crashes due to unsized type adds d1f8152166b llvm-pdbutil: Fix an off-by-one error. adds 6b11f688f95 [RISCV] implement li pseudo instruction adds 57045499a5e [Mem2Reg] Make RenamePassData a struct, NFC adds 7860aaa87bd [Mem2Reg] Create merged debug locations for inserted phis adds eca9ecf8f9d [AMDGPU] Enabled v2.16 literals for VOP3P adds 91cfb1b3cd2 Fix lock order inversion between ManagedStatic and Statistic adds b8a6d70c623 [InstCombine] peek through bitcasted vector/array pointer G [...] adds 8c9881027c5 [X86] Don't crash on bad operand modifiers in inline assembly adds fa0387cdcb3 [X86] Give CMOV 2 cycle latency on SLM. adds 31a2e832033 [X86][Broadwell] Remove some unnecessary InstRW overrides a [...] adds d5f157e2f57 [NFC] Remove doxygen brief tag from BasicBlock.h adds f31b39d494d [DebugInfo] Sink related dbg users when sinking in InstCombine adds 31d0ca3473f [UpdateTestChecks] Add update_mca_test_checks.py script adds 6a0f0b3810a [CodeGen/Dwarf] Make debug_names compatible with split-dwarf adds c108ab6989b [LoopUnroll] Only peel if a predicate becomes known in the [...] adds 646d5bb4d19 [cmake] Improve pthread_[gs]etname_np detection code adds 48ba6668256 [gold] Add support for optimization remarks adds 32e164b60b0 Add tests for shrink wrapping and VLAs adds 7fd3d3499a0 [llvm-exegesis] Pull out LLVMTargetMachine to simplify debu [...] adds 2acef23b4c3 [IRCE] Only check for NSW on equality predicates adds 793b714ddcf [AMDGPU] Fix issues for backend divergence tracking adds fbb6a60b6dc [llvm-exegesis] Put a newline at the end of each error report. adds aacb846c039 [SimplifyLibcalls] Realloc(null, N) -> Malloc(N) adds e734fe7e7b9 [llvm-exegesis] Use LLVMTargetMachine pointer everywhere. NFCI. adds 22942f7d6c2 [llvm-link] Use WithColor for printing errors adds 331449e7a89 [llvm-profdata] Use WithColor for printing errors adds c5db21b2665 [llvm-exegesis] Early out if the scheduler models have no e [...] adds 4c208ab0d79 [x86] Fix PR37100 by teaching the EFLAGS copy lowering to r [...] adds 85b1d18f0d0 Fix macosx build broken by r330249 adds a1ce0364e1c [support] Revert the changes made to Path.inc for the defau [...] adds ef2e5c92da3 [llvm-mca] Use WithColor for printing errors adds bb1ae438ca5 [x86] Switch EFLAGS copy lowering to use reg-reg form of te [...] adds f44d5a8b288 [DEBUG] Initial adaptation of NVPTX target for debug info e [...] adds ad6944ff337 [Power9]Legalize and emit code for converting (Un)Signed Wo [...] adds c947c65d49f [RISCV] Add specific tests for materialising imm32hi20 constants adds 70c796521ab [AArch64] Add isel pattern for v8i8->v2f32 NVCASTs. adds bd37d91039d [Power9]Legalize and emit code for converting Unsigned HWor [...] adds eea8107fac8 Revert "[RISCV] implement li pseudo instruction" adds 2383cbfa441 [X86] Fix the Uses/Defs,mayLoad,mayStore,hasSideEffects fla [...] adds 6663e67a21f [RISCV] Expand codegen -> compression sanity checks and mov [...] adds 3c8a2d808d0 [NFC] test case clean up adds 54ecebc52f7 [RISCV] Add imm-cse.ll test case adds e50f5775ba4 [RISCV] Introduce pattern for materialising immediates with [...] adds 4b5e6386220 [RISCV] Add test changes missed from rL330293 adds e6a7df8ac46 [llvm-mca][X86] Add mmx versions of SSSE3 instructions adds cbae883886b [NVPTX, CUDA] Added support for m8n32k16 and m32n8k16 varia [...] adds 3519a73c740 [X86] Correct the Defs, Uses, hasSideEffects, mayLoad, mayS [...] adds 01e03762a43 Fix data race in X86FloatingPoint.cpp ASSERT_SORTED adds b7fe96d5508 [X86] Scrub scheduling information for MUL/IMUL on Intel CPUs. adds b168bb8b429 [AArch64][AsmParser] NFC: Cleanup parsing of scalar registers. adds c1e9b6f826c [ARM] Add some missing FP16 VSEL test cases adds 439126f10fd [mips] Guard some macro expansions properly adds 848303cb28a [BasicBlock] Add instructionsWithoutDebug methods to skip d [...] adds 1603ab5697c [llvm-exegesis] Fix PfmIssueCountersTable creation adds 4448c2a7343 [X86][BtVer2] Remove 128-bit F16C InstRW overrides. adds 5e2ab6d5c93 [X86][FMA] Remove FMA reg-reg InstRW scheduler overrides. adds 6881b02b33c [IR/BasicBlockTest] Fix asan failure introduced in rL330316. adds 37562feb1c3 Remove file accidentally added in r330320. adds b6965c7c4fe Lowering x86 adds/addus/subs/subus intrinsics (llvm part) adds 644eb7b4697 [NFC][InstCombine] A few more tests for masked merge add/xo [...] adds 90bb2289e6e [mips] Correct the definitions of the unaligned word memory [...] adds 08c3a991721 [Unittests] Fix plugins test adds 37e180bdc4f [Hexagon] Add/fix patterns for 32/64-bit vector compares an [...] adds e55af336cb1 [X86][BtVer2] Remove SSE4A EXTRQ/EXTRQI InstRW overrides. adds aa16779ee39 [Hexagon] Generate code for vector bswap intrinsics adds 141e6bde5ce [NewGVN] Add ops as dependency if we cannot find a leader f [...] adds 77925f6df31 [llvm-mca][X86] Add mmx instruction to btver2 resource tests adds 4f520606fc4 [AMDGPU] Do not only rely on BB number when finding bottom loop adds 3e0bad65f97 [gold/ThinLTO] Invoke llvm_shutdown when exiting after Thin [...] adds 7effcbd2546 [llvm-objdump] Print "..." instead of random data for virtu [...] adds b7f081acd6a [llvm-objdump] Remove test object file adds 980f5afda1b [Hexagon] Use legal types when lowering CONCAT_VECTORS via [...] adds e21049990ab [if-converter] Handle BBs that terminate in ret during diam [...] adds ed36cef6838 [X86] Merge some MMX instregex adds 4d445a2a381 [Reassociate] fix formatting; NFC adds 9afbe3949f0 [X86] Correct the scheduling data for register forms of XCH [...] adds a950af2c60a [X86][SLM] Fix typo using SandyBridge resources. adds c1d81f2df77 [llvm-mca][X86] Add resource test for every out-of-order sc [...] adds 2c63662d707 [ORC] Make VSO symbol resolution/finalization operations private. adds 6ff81c8a681 [PM/LoopUnswitch] Detect irreducible control flow within lo [...] adds 6b49fde581a [X86] Enable popcnt false dependency breaking on Silvermont [...] adds 52d1558d204 [ORC] Fix an assertion condition from r329934. adds a5747ee16d0 Refine the loop rotation's API adds 3c5b42002c4 [X86] Remove non-existant instruction name from X86Disassem [...] adds c475d7913dc [llvm-objdump] Issue error message when object file cannot [...] adds 8aac3379380 [AMDGPU] Use packed literals with zero either lower or hi part adds 8e055041123 [llvm-mca][FMA] Add FMA resource tests adds c625656e260 [Reassociate] add baseline tests for binop swapping; NFC adds cbec9b05be8 [WebAssembly] Enabled -triple=wasm32-unknown-unknown-wasm p [...] adds 770b506fe44 [llvm-mca][X86] Add prefetch instruction resource tests adds 7256bf169ac [MachineOutliner] NFC: Move EnableLinkOnceODROutlining into [...] adds 98f500f52fa Move a dump() implementation out of line. adds 0af0deeed91 LowerTypeTests: Propagate symver directives adds f2e8d8edd85 Fix build failures for r330387 on buildbots that don't buil [...] adds 289b2361869 [Sparc] Fix addressing mode when using 64-bit values in inl [...] adds 98206475478 AMDGPU: Legalize the operand of SI_INIT_M0 adds 06d4ac89d73 [AArch64][AsmParser] Extend RegOp with integrated 'shift/extend'. adds 1e2a2ae6dec [Sparc] Use synthetic instruction clr to zero register inst [...] adds a96bcd088de Revert "This pass, fixing an erratum in some LEON 2 processors..." adds 04b184b9300 [SSAUpdaterBulk] Use SmallVector instead of SmallPtrSet for uses. adds ba04672474d [SSAUpdaterBulk] Use PredCache in ComputeLiveInBlocks. adds f6646b7a167 [SSAUpdaterBulk] Add * and & to auto. adds 63faaa5e157 Add SPARC support to update_llc_test_checks.py adds e623ebc840a [SSAUpdaterBulk] Add an assert. adds caacf239828 Reapply "[PR16756] Use SSAUpdaterBulk in JumpThreading." on [...] adds 7ad12ae7758 [AArch64][SVE] Added GPR64shifted and GPR64NoXZRshifted reg [...] adds 113fa203569 [AArch64][SVE] Fix diagnostic for SVE LD4 instructions: adds 1ee7070ddf8 [lit] Fix a bug where UNRESOLVED tests were not handled in [...] adds b1203052374 CODE_OWNERS: Take code ownership of llvm-mca. adds a2fbfc91ac4 [LTO] Add stats-file option to LTO/Config.h. adds 50f681d0309 [Dockerfiles] Split checkout and build scripts into separat [...] adds 35a415fc011 [SSAUpdaterBulk] Use SmallVector instead of DenseMap for st [...] adds eca393c1156 [DebugInfo] Fix for split dwarf test on Windows (NFC) adds ef1b331188a [NFC][InstCombine] Regenerate two tests that are affected b [...] adds 8e71a936a4c Revert r330403 and r330413. adds af64333a9f8 Require asserts for stats-file-option tests. adds 2f0f603361d [UpdateTestChecks] Fix update_mca_test_checks.py slowness issue adds f6415de6bf9 [ObjectYAML] Add ability for DWARFYAML to calculate DIE lengths adds 8e6c534e1ed [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+sca [...] adds cb012539241 [X86] Tag CLDEMOTE instruction with WriteLoad scheduling class adds f23938f2441 [X86][BtVer2] Cleanup some old FIXMEs from the model. NFCI. adds 1efc1f18387 Revert "Revert r330403 and r330413." adds e1311cf67ea [CostModel][X86] Add GoldmontPlus cost tests adds a0c7210b953 [CostModel][X86] Split off BtVer2 cost checks adds c004bc17f06 Fix typo in a test. adds b43e74c4874 [CostModel][X86] Add SLM/GLM/BtVer2 compare + division/rema [...] adds 45252fa7dda [CostModel][X86] Add srem/urem constant cost tests adds f02c6abfc7c [DAGCombine] (float)((int) f) --> ftrunc (PR36617) adds 0fe34c66d5e Fix test by allowing it to accept an upper or lower case le [...] adds c01ee6eab4e [CostModel][X86] Add vector element insert/extract cost tests adds 3ebc072a79f [DebugInfo] Use WithColor for more debug line warnings adds 73d8c2e5e3e [NewGVN] Split OpPHI detection and creation. adds e44102606a4 [x86] auto-generate checks; NFC adds b2249a973bb Revert r330431. adds bb0330027c7 [WebAssembly] Distinguish debug/symbol names in the Wasm st [...] adds fba895e25a4 [utils] improve AArch64 asm parser adds 68f9d728cdd Remove llvm-build's --configure-target-def-file. adds ce352b75bc2 [LLD/PDB] Emit first section contribution for DBI Module De [...] adds 99a99056259 [MachineOutliner] Change B instruction for tail calls to TC [...] adds b0e095336fe [X86] WaitPKG instructions adds f407f3fba19 [X86][SandyBridge] Remove duplciate InstRWs from Sandy Brig [...] adds 8200c2d55a7 [Hexagon] Skip fixed-stack indexes in HexagonConstExtenders adds 26c5a9605fa Remove unused argument from emitModuleMetadata. adds ebfa356af41 [Hexagon] Improve HVX instruction selection (bitcast, vsplat) adds 14ef2bb1c44 [Hexagon] hexagon-autohvx was left on again adds 7574b7ef166 [PartialInlining] Fix Crash from holding a reference to a d [...] adds 3b391a578da [HWASan] Introduce non-zero based and dynamic shadow memory [...] adds f8bff0d6512 [llvm-objcopy] Fix sh_link adds 5412111d988 [X86] Add WriteFSign/WriteFLogic scheduler classes adds 68c6a26f031 [llvm-mca][X86] Add MMX/SSE/AES/CLMUL resource SandyBridge tests adds 72054c3dbb3 [ObjCARC] Account for funclet token in storeStrong transform adds c203d72cb42 [ObjCARC] Take BlockColors by const reference. NFC adds 0e937a1da01 [MachineOutliner] XFAIL machine-outliner-noredzone.ll adds 5dd3768d28f Fix typo in test (verify-machine-instrs -> verify-machineinstrs) adds 78ffb44f174 [AArch64] Don't crash trying to resolve __stack_chk_guard. adds c7e248c3291 [PowerPC] fix incorrect vectorization of abs() on POWER9 adds a87cddafd1b [X86][X87] Add missing fldlg2 schedule test adds 3d458841dcc [llvm-mca][X86] Add X87 resource tests adds b9ea85c4def [X86] Strip unnecessary x87 instruction instrw overrides fr [...] adds 87ebc9691b2 [llvm-mca][X86] Add MMX resource tests adds eb497a703fd [X86] Strip unnecessary MMX instruction instrw overrides fr [...] adds cd4182addab [X86][SandyBridge] Strip unnecessary MOVQ/CVT instruction i [...] adds 47dc19d3a63 [llvm-mca][X86] Add SSE resource tests to all models adds adb42c178e5 [X86] Strip unnecessary WriteFShuffle instruction instrw ov [...] adds 78288e4d3d1 [X86] Strip unnecessary WriteFRcp/WriteFRsqrt instruction i [...] adds afefd074c18 [llvm-mca][X86] Add AVX2 resource tests adds 9c642ec90eb [X86][Broadwell] Remove unnecessary VORPD/VORPS instrw over [...] adds 8982c7a5bc4 [X86][Haswell] Strip unnecessary WriteFAdd/WriteFHAdd instr [...] adds 7138e5f726e [InstSimplify] move/add/regenerate checks for tests; NFC adds ce3569799c6 [InstSimplify] move tests for shifts; NFC adds bdf2d487f20 [X86] Add SchedWrites for LDMXCSR/STMXCSR. adds b14e304f175 [X86] Add test cases that show the current codegen for (tru [...] adds 03345f1de96 [X86] Add DAG combine to turn (trunc (srl (mul ext, ext), 1 [...] adds 95f4d00dadc [X86] Strip unnecessary vector integer math, shift-imm, ext [...] adds 0de8924270e [X86][AVX] VPERM2F128/VINSERTF128 should be a shuffle256 sc [...] adds cc7f8fb7111 [X86] Strip unnecessary broadcast/shuffle256 instrw overrid [...] adds ae6875ea1d0 [tools] Use WithColor for printing errors. adds 6d70778ed24 [X86] Strip unnecessary WriteCvtF2I instrw overrides from s [...] adds 52107f01892 [Support] Add optional prefix to convenience helpers in WithColor. adds 8a861286e9c [X86] Strip unnecessary prefetch + vector move/load instrw [...] adds 37f137831d0 [bcanalyzer] Recognize more stream types adds 36e277610af [X86] Remove DATA32_PREFIX. Hack the printing for DATA16_PR [...] adds eb264478e48 [X86] Remove OpSizeIgnore, it's not implemented any differe [...] adds f9cdf3a953a [X86] Change TB to PS on LFENCE instruction. adds c2157439298 [X86] Remove an unnecessary HANDLE_OPTIONAL line from the d [...] adds e375d515ff4 [Support] Fix prefix logic in WithColor. adds aa9bcfc6a2b [llvm-mc] Make error handling more consistent. adds f79bdbd6672 [lli] Make error handling more consistent. adds a9bcdb1ff3a [lli] Fix syntax error: missing ';' adds 6417e64ede8 [test] Fix MC/ELF/nocompression.s adds 0570c7b0201 [llvm-mca][X86] Add POPCNT resource test adds e87218f1ded [X86][SandyBridge] Remove unnecessary WritePOPCNTLd overrid [...] adds 9c07603cbbe [X86] Fix WriteMPSAD/WritePSADBW values to allow us to remo [...] adds 03c56176d2f [InstSimplify, InstCombine] add vector tests with undef elts; NFC adds c3427dcb3e5 [X86] Remove unnecessary WriteFVarBlend/WriteVarBlend InstR [...] adds 2bfd21c0c2f [X86][MMX][SSE] Tag missed PHADD/PHSUB instructions with Wr [...] adds d37d51b92b9 [X86] Fix (completely overridden) WriteFHAdd/WritePHAdd cla [...] adds cf40c3d4061 [InstCombine] add vector test with undef elts; NFC adds 41435b38868 [X86][Atom] Remove unnecessary scalar/vector load/move inst [...] adds 21ad2d42481 [X86][SkylakeServer] Remove unnecessary PMULLD instrw overrides. adds e1bbe842073 [PatternMatch] allow undef elements when matching a vector zero adds a3df84bd43a Test commit access. adds ebe1329c9c4 [X86] Remove unnecessary CVT instrw overrides. adds fe589a2b49c [X86] Remove unnecessary WriteFMul/WriteFRcp/WriteFRsqrt In [...] adds 3070e9a666a [X86] Remove unnecessary WriteFBlend/WriteBlend InstRW overrides. adds aec06286e37 [LLVM-C] Add DIBuilder Bindings For Variable Creation adds 97d0c208072 [llvm-mca][X86] Add BMI/LZCNT/POPCNT resource tests to all [...] adds 7b19e4fd54a [X86][Znver1] Remove unnecessary BMI1 ANDN InstRW overrides. adds 57b516a175e [PM/LoopUnswitch] Fix comment typo. NFC. adds eeb236b7dcf [X86] Add VEX_WIG to VEX encoded version of VCMPPSY/VCMPPDY. adds a9104c62a07 [PM/LoopUnswitch] Remove a buggy assert in the new loop unswitch. adds 83cd5098e06 [AArch64][SVE] Asm: Support for structured ST2, ST3 and ST4 [...] adds 1b68b2eca5b Test commit access. adds 0a556c8c152 Fix BNF nits in TableGen language reference. adds d356fd67325 [LoopSimplify] Fix incorrect SCEV invalidation adds b66694ab520 [LoopUnroll] Fix potentially incorrect SCEV invalidation in [...] adds 8922c109182 [X86] Remove unnecessary MMX reg-mem InstRW scheduler overrides. adds 73211421076 [LoopRotate] Fix incorrect SCEV invalidation in loop rotation adds 5f9640830bd [AArch64][SVE] Asm: Support for contiguous, non-faulting LD [...] adds 49621ae2321 Consistently sort add_subdirectory calls in lib/Target/*/CM [...] adds ae99d3d94c6 AMDGPU: Fix a corner case crash in SIOptimizeExecMasking adds 3db53ca6545 AMDGPU: Fix SDWA peephole for V_AND_B32 adds 99e23bd0c83 List cpp file only once (was added in 147117 and 147117 as [...] adds a5418594dca [X86] Remove instregex matching from CLAC/STAC. adds 75dd90ec3a4 [doc] Removed obsolete -count-aa from AliasAnalysis documentation adds 2fbfc40760b [LLVM-C] Finish Up Scope Bindings adds ec94ea919c9 [DEBUGINFO, NVPTX] Add the test for the debug info of the l [...] adds 5a0bf254cee Sort a target list a bit better. adds cd997a7a919 [LLVM-C] DIBuilderBindings for Subrange and Arrays adds 91f2b63a060 [SelectionDAG] Refactor lowering of atomic memory intrinsics. adds 9269b2bccbb StackSlotColoring: Fix missing skipFunction check adds 7c20cc06694 AMDGPU: Assign enum name to stack ID adds 48c9175fe52 Fix computeSymbolSizes SEGFAULT on invalid file adds c07c4e02980 [X86] Replace x87 instregex with instrs if they only match [...] adds 8c0fb2c4731 AMDGPU: Move a flawed assert when spilling SGPRs adds 72775a354cf Fix -Wtautological-compare warning with npos on Windows adds c9943400631 [MC] Remove MachineInstr reference in MC layer (PR37160) adds aeb3e4fcbba [SelectionDAG] Dump debug locs in SDNodes adds 14d8c6dfc0a [X86] Add disassembler test cases for bswap. adds b6ec859b6cf [HWASan] Switch back to fixed shadow mapping for x86-64 adds 871b8fe06db [AArch64] Add cost model test case for transpose adds 6c92ba3e0b0 [DSE] Teach the pass that atomic memory intrinsics are stores. adds cebbb7c0755 Reland r329956, "AArch64: Introduce a DAG combine for foldi [...] adds f48113f0d58 [CODE_OWNERS] Update my email address. adds 3f46946fed3 [WebAssembly] MC: Refactor section creation code adds dee66509687 [MemCpyOpt] Skip optimizing basic blocks not reachable from entry adds abc9d03bfce [X86] movdiri and movdir64b instructions adds 17e9db0c42b Fix a broken typedef; NFCI adds 4dd24c474b0 [X86] Revert r330638 - accidental commit adds 7f02d6427ab [CallSiteSplit] Make sure we remove nonnull if the paramete [...] adds b3099726027 [AggressiveInstCombine] add tests for PR37098; NFC adds ee05cadf697 [X86][AArch64][NFC] Add tests for masked merge unfolding adds 04273076b90 [DAGCombiner] Unfold scalar masked merge if profitable adds 0597a753723 [X86] Remove unnecessary WriteLEA InstRW overrides. adds 99abef011d5 [LoopInterchange] Do not change LI for BBs in child loops. adds b344f5ad32b [X86] Remove unnecessary BMI2 InstRW overrides. adds e55b052e033 [GlobalISel][Legalizer] Look thro copies while combining G_ [...] adds bffba319b28 [LLVM-C] DIBuilder Bindings For Variable Expressions adds 19c6b95399d [X86] Remove unnecessary vector memory folded InstRW overrides. adds 043b23526d1 [AggressiveInstCombine] Add library initializer routine for [...] adds 6f6553e0da2 [AggressiveInstCombine] Add createAggressiveInstCombinerPas [...] adds a6786e9cb26 [HWASan] Use dynamic shadow memory on Android only (LLVM) adds 557491f34d4 Reland r301880(!): "[InstSimplify] Handle selects of GEPs w [...] adds f7d7c68c751 [AggressiveInstCombine] Add aggressive inst combiner to the [...] adds b5b7fce64c1 InstCombine: Fix layering by not including Scalar.h in InstCombine adds 1f039215102 Fix build breaks in examples due to moving stuff from Scala [...] adds bdd8ac7826b Remove code that's almost always dead, and harmful if not. adds 3eb9432cd20 Mostly revert r330672. adds 5bef44a156a Change if-conditionals to else-if as they should all be mut [...] adds 0a219a22e15 Reflow formatting after previous NFC commit. adds 76f6bf2a288 [NFC] Add clarification comment adds 903870a8da3 Remove unused function HexagonEarlyIfConversion::replacePhi [...] adds eceadea7706 [PM/LoopUnswitch] Remove another over-aggressive assert. adds 1e1ca09b35b [X86] Add a BSWAP16 instruction using the 32-bit encoding p [...] adds 9d4b43cf243 [NFC] Use forgetTopmostLoop instead of logic duplication adds 3c8c5ef2e4d [NFC] Use FileCheck in test adds ae1ca02d148 Recommit "[llvm-objcopy] Switch over to using TableGen for [...] adds 7f71e973940 [llvm-objcopy] Adjust the code for the old versions of msvc adds d5a2fd47b68 [LVI] Fix typo. NFC adds a92eb5b1f3c [Support/Path] Add more tests and improve failure messages [...] adds c3aaa9b38e1 Link to AggressiveInstCombine in a few places. Unbreaks bui [...] adds 903ed71cb90 [AArch64][SVE] Asm: Support for contiguous, first-faulting [...] adds 0c47f856a1a [LoopInfo] Verify BBMap tracks innermost loops for BBs. adds da589ee06ad [NFC] Remove recently added SE verification because it may [...] adds cefae4fb96e [CodeGen] Do not allow opt-bisect-limit to skip ScalarizeMa [...] adds 97ee2baf098 [llvm-mca][CommandGuide] Fix typo in example. adds 2d93770624e [mips] Correct the patterns for bswap adds b6bee651995 Correct dwarf unwind information in function epilogue adds fef8b01d9b1 [PM/LoopUnswitch] Fix a bug in the loop block set formation [...] adds b91ac890b26 [CodeGen] Print user-friendly debug locations as MI comments adds ad168c34945 [X86] Replace action Promote with Expand for operation ISD: [...] adds a9a87be18b9 [MC] Remove orphan MCSchedModel::computeReciprocalThroughpu [...] adds 2574f6647ee [X86] Add vector element insertion/extraction scheduler classes adds 18d09b9a77f [X86] Fix missing cfi from sitofp checks adds d0c01140be8 Fix Wdocumentation warnings. NFCI. adds a6bf70d02a3 [SystemZ] Use preferred 16-byte function alignment adds 6d80e6324bb [X86] Remove unnecessary FMA reg-mem InstRW scheduler overrides. adds 0f80c5447f7 [llvm-mca] Refactor the Scheduler interface in preparation [...] adds 5b7ab74398a [LoadStoreVectorize] Ignore interleaved invariant loads. adds b99e72106ad Fix some layering in AggressiveInstCombine (avoiding inclus [...] adds 70f3bbf514c Remove LLVM_INSTALL_CCTOOLS_SYMLINKS adds 7537653e9a6 [lit] Remove spurious `-` in invocation of lit in `shtest-x [...] adds e5ad7684b57 [InstCombine] regenerate checks; NFC adds fc4e13c88fc [AMDGPU][Waitcnt] NFC. Cleanup some code/naming consistency [...] adds 6ddbc3eac4a [InstCombine] regenerate checks; NFC adds 6f8184d949f [mips] Show an error if register number is out of range adds 9830843b265 [llvm-mca] Default the output asm dialect used by the instr [...] adds 7d78f54577d [X86][IVB] Add F16C resource tests. adds f862b68e42a [X86][BtVer2] Fix VCVTPS2PHmr/VCVTPS2PHYmr latencies adds 7fe67cc2ad8 [ADT] Remove ilist_default_traits adds 59def0db59d [X86][F16C] Add WriteCvtF2FSt scheduling class adds 5e83467a58e [LoopInterchange] Make isProfitableForVectorization slightl [...] adds e8b06de3786 [LV][VPlan] Detect outer loops for explicit vectorization. adds f2df8a65f44 Reland "[mips] Guard traps for microMIPS correctly" adds f8dd899c6c0 Let TableGen write output only if it changed, instead of do [...] adds 9596ad894f4 [AVX512] VPERMQ/VPERMPD/VPERMIL single op shuffles are not [...] adds 0e90219cfdc [LoopInterchange] Add REQUIRES: asserts to test. adds 194a4e0c230 [WebAssembly] Use section index in relocation section header adds 37c88ba012b [XOP] v4i32 IFMA 'VPMACS' instructions should use the Write [...] adds dbe20f7ece5 [AMDGPU] Truncate packed inline constant adds c2a684aafa1 [lit] Report line number for failed RUN command adds 4882062d7b8 [X86] Split off PHMINPOSUW to their own schedule class adds 33b053f159a [llvm-mca] Remove unused flag -verbose. NFC adds 422ac9ee805 [test] Update llc checks for CodeGen/X86/avg.ll adds c8da0cf0f08 [X86][SKX] Setup WriteFMul and remove unnecessary InstRW sc [...] adds 210f16960b3 [cmake] Fix libc++ detection adds 620db41ce74 [Support] fix countLeadingZeros for types shorter than int adds 46e550273c4 [bugpoint] Fix crash when testing for miscompilation. adds 8801c5f87be [wasm] Fix uninitialized memory introduced in r330749. adds 1fb60f8e003 AMDGPU/GlobalISel: Add support for amdgpu_ps calling convention adds 98befe3296b [InstCombine] move tests for select with bit-test of condit [...] adds 608fcd9862f [CaptureTracking] Fixup const correctness of DomTree arg (NFC) adds ebab8e7d8d1 [X86][AArch64][NFC] Add tests for masked merge unfolding wi [...] adds 727ef0e543b [docs] Add a note on non-deterministic sorting order of equ [...] adds 5011204f5c7 AMDGPU/GlobalISel: Fall-back to SelectionDAG for non-void f [...] adds e843f71e41f AMDGPU: Remove deprecated llvm.AMDGPU.kilp intrinsic adds 13059298290 Bring back APInt self-move assignment check for MSVC only adds 86e361fbbcf [llvm-objcopy] Adjust the help message adds 17c3c080839 [X86] Account for partial stack slot spills (PR30821) adds 16e61f3c897 Fix path separator checks on Windows adds df527edd375 [DAGCombiner][X86] When promoting loads don't use ZEXTLOAD [...] adds bd42bc726f0 [MachineOutliner] Check for explicit uses of LR/W30 in MI operands adds 685477eba1e [PM/LoopUnswitch] Begin teaching SimpleLoopUnswitch to use [...] adds b99fab9a2a2 [DivRemPairs] Fix non-determinism in use list order. adds 54a51fd6b1f [X86] Auto-generate complete checks. NFC adds f861cfb472f Merging r46043: ------------------------------------------- [...] adds 57fd3bde975 [TableGen] Fix bad indentation in tablegen output file. adds 925ebe73277 [DebugInfo] Invalidate debug info in ReassociatePass::Rewri [...] adds 4dbfefddbb0 [AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/s [...] adds 7fa40771cd3 [LoopInterchange] Use getExitBlock()/getExitingBlock instea [...] adds 81554797999 [llvm-mca] Remove method Instruction::isZeroLatency(). NFCI adds e508042fca2 [llvm-mca] Default to the native host cpu if flag -mcpu is [...] adds 5ce6b66393e [mips] Fix the definition of sync, synci adds b7acab1156b [llvm-mca] run clang-format on a bunch of files. NFC adds beba25ef7bb [X86][SNB] Remove unnecessary WriteFBlendLd InstRW schedule [...] adds 83e2d95494f [X86][SKX] Setup WriteFAdd and remove unnecessary InstRW sc [...] adds b3a293eadb1 [UpdateTestChecks] Change update_mca_test_checks.py file mo [...] adds a2dfca18bd7 [llvm-mca] Add a new option category for views. adds e914bb329fd Avoid a warning on pointer casting, NFC adds a19138250c8 [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556) adds 4d8977d8c70 [X86][AArch64][NFC] Finish adding 'bad' tests for masked me [...] adds f69cb881594 [X86] Split WriteFMA into XMM, Scalar and YMM/ZMM scheduler [...] adds 37cfbc28b21 [llvm-mca][X86] Updated fma3 tests after rL330820 adds d7511a6154f [mips] Teach the delay slot filler to transform 'jal' for m [...] adds 7b0e2e0edb1 [RISCV] Support "call" pseudoinstruction in the MC layer adds 59bf3bda3c6 [RISCV] Expand function call to "call" pseudoinstruction adds 677f7d70cd1 [llvm-mca] Make ViewOptions static. NFCI adds f15e442e766 Fix typo in static_assert for size of LoadSDNodeBitfields. adds 11236cb48b5 [AArch64][GlobalISel] Implement selection for the llvm.trap [...] adds 538d0b3d18b [CostModel][X86] Recursive call for cost of imul for packed [...] adds 1f4d93bdb6e [InstCombine] add tests for select to logic folds; NFC adds 3d8c29de7bb [InstCombine] clean up foldSelectICmpAnd(); NFC adds ea0775ec4a0 Rename Attributes.gen, Intrinsics.gen to Attributes.inc, In [...] adds 152c656c6b8 [ICP] Do not attempt type matching for variable length arguments. adds 5e0c3d56ab9 Don't list a source file twice. adds a96f6b88c13 [RISCV] Allow call pseudoinstruction to be used to call a f [...] adds 8bd0ee70dad Revert r330755 "[lit] Report line number for failed RUN command" adds 81d3291b19c [X86] Form MUL_IMM for multiplies with 3/5/9 to encourage L [...] adds 26c891e9119 [CostModel][X86] Add div/rem tests for non-uniform constant [...] adds 5fc3ea70fc4 Rename sancov.cc to sancov.cpp adds 557b2891e65 [WebAssebmly] Add Module name to WasmSymbol adds 2bcb33333d7 IWYU llvm-config.h for LLVM_VERSION_STRING adds bea0f24e1c2 [MIR] Add support for debug metadata for fixed stack objects adds e1300f7ef8e [SimplifyLibcalls] Atoi, strtol replacements adds b922196f7a1 [AMDGPU] Waitcnt pass: add debug options new 96501d2a948 Release 2018-04-24 for google/stable @r330864 new e5ed4adb505 Release 2018-04-24 for google/stable @r330764 new f8df945fd4b Release 2018-04-24 for google/stable @r330764 new aab320fc7fa Cherry-pick @=r330893 to google/stable for 2018-04-24 new a282a5fb585 Cherry-pick @=r330947 to google/stable for 2018-04-24 new 34a55b97e48 Cherry-pick @=r330950 to google/stable for 2018-04-24 new ce0ab76f978 Cherry-pick @=r330951 to google/stable for 2018-04-24 new 4cc4ad34895 Cherry-pick @=r330997 to google/stable for 2018-04-24 new 81aee6ad323 Cherry-pick @=r331237 to google/stable for 2018-04-24

The 9 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: BRANCH_HISTORY | 7 + CMakeLists.txt | 10 +- CODE_OWNERS.TXT | 9 +- bindings/go/llvm/DIBuilderBindings.cpp | 204 - bindings/go/llvm/DIBuilderBindings.h | 94 - bindings/go/llvm/IRBindings.cpp | 3 - bindings/go/llvm/IRBindings.h | 2 - bindings/go/llvm/dibuilder.go | 116 +- bindings/go/llvm/ir.go | 55 +- bindings/go/llvm/ir_test.go | 7 +- bindings/go/llvm/transforms_scalar.go | 1 + bindings/python/llvm/core.py | 3 + cmake/config-ix.cmake | 90 +- cmake/modules/AddLLVM.cmake | 9 +- cmake/modules/FindLibpfm.cmake | 23 + cmake/modules/HandleLLVMOptions.cmake | 4 +- cmake/modules/HandleLLVMStdlib.cmake | 6 +- cmake/modules/LLVMConfig.cmake.in | 2 + cmake/modules/LLVMProcessSources.cmake | 18 +- cmake/modules/TableGen.cmake | 20 +- docs/AMDGPUAsmGFX7.rst | 1249 + docs/AMDGPUAsmGFX8.rst | 1660 + docs/AMDGPUAsmGFX9.rst | 1795 + docs/AMDGPUOperandSyntax.rst | 1055 + docs/AMDGPUUsage.rst | 335 +- docs/AliasAnalysis.rst | 33 +- docs/BitCodeFormat.rst | 3 + docs/CMake.rst | 25 +- docs/CodingStandards.rst | 4 +- docs/CommandGuide/dsymutil.rst | 11 + docs/CommandGuide/index.rst | 2 + docs/CommandGuide/lit.rst | 2 + docs/CommandGuide/llvm-cov.rst | 12 + docs/CommandGuide/llvm-exegesis.rst | 58 + docs/CommandGuide/llvm-mca.rst | 194 + docs/Coroutines.rst | 26 + docs/Docker.rst | 58 +- docs/ExceptionHandling.rst | 2 +- docs/GarbageCollection.rst | 10 +- docs/LangRef.rst | 525 +- docs/Lexicon.rst | 6 + docs/MIRLangRef.rst | 64 +- docs/ProgrammersManual.rst | 2 +- docs/ReleaseNotes.rst | 41 + docs/TableGen/LangIntro.rst | 40 +- docs/TableGen/LangRef.rst | 34 +- docs/TableGen/index.rst | 2 +- docs/XRay.rst | 25 +- docs/XRayExample.rst | 14 +- docs/tutorial/LangImpl02.rst | 12 +- docs/tutorial/LangImpl03.rst | 2 +- docs/tutorial/LangImpl04.rst | 6 +- docs/tutorial/LangImpl05.rst | 14 +- docs/tutorial/LangImpl06.rst | 2 +- .../BuildingAJIT/Chapter1/KaleidoscopeJIT.h | 4 +- .../BuildingAJIT/Chapter2/KaleidoscopeJIT.h | 17 +- .../BuildingAJIT/Chapter3/KaleidoscopeJIT.h | 10 +- .../BuildingAJIT/Chapter4/KaleidoscopeJIT.h | 11 +- .../BuildingAJIT/Chapter5/KaleidoscopeJIT.h | 11 +- examples/Kaleidoscope/Chapter4/toy.cpp | 3 +- examples/Kaleidoscope/Chapter5/toy.cpp | 5 +- examples/Kaleidoscope/Chapter6/toy.cpp | 5 +- examples/Kaleidoscope/Chapter7/toy.cpp | 6 +- examples/Kaleidoscope/include/KaleidoscopeJIT.h | 4 +- include/llvm-c/Comdat.h | 75 + include/llvm-c/Core.h | 178 +- include/llvm-c/DataTypes.h | 90 + include/llvm-c/DebugInfo.h | 670 + include/llvm-c/Disassembler.h | 147 +- include/llvm-c/DisassemblerTypes.h | 160 + include/llvm-c/Initialization.h | 1 + include/llvm-c/OrcBindings.h | 34 +- include/llvm-c/Support.h | 2 +- include/llvm-c/TargetMachine.h | 8 + include/llvm-c/Transforms/InstCombine.h | 43 + include/llvm-c/Transforms/Scalar.h | 9 +- include/llvm-c/Transforms/Utils.h | 50 + include/llvm-c/Types.h | 7 +- include/llvm/ADT/MapVector.h | 22 +- include/llvm/ADT/PointerUnion.h | 6 + include/llvm/ADT/STLExtras.h | 32 + include/llvm/ADT/Statistic.h | 22 + include/llvm/ADT/StringSwitch.h | 13 +- include/llvm/ADT/Triple.h | 1 - include/llvm/ADT/ilist.h | 17 +- include/llvm/Analysis/AliasAnalysis.h | 4 +- include/llvm/Analysis/ConstantFolding.h | 6 + include/llvm/Analysis/DivergenceAnalysis.h | 11 +- include/llvm/Analysis/LoopAccessAnalysis.h | 14 + include/llvm/Analysis/LoopInfo.h | 8 +- include/llvm/Analysis/LoopInfoImpl.h | 16 +- include/llvm/Analysis/MemoryLocation.h | 8 + include/llvm/Analysis/MemorySSA.h | 22 +- include/llvm/Analysis/MemorySSAUpdater.h | 11 +- include/llvm/Analysis/MustExecute.h | 64 + include/llvm/Analysis/ObjCARCAnalysisUtils.h | 10 + include/llvm/Analysis/ObjectUtils.h | 42 - include/llvm/Analysis/Passes.h | 8 + include/llvm/Analysis/ScalarEvolution.h | 99 +- include/llvm/Analysis/ScalarEvolutionExpander.h | 2 +- include/llvm/Analysis/TargetLibraryInfo.def | 36 + include/llvm/Analysis/TargetTransformInfo.h | 74 +- include/llvm/Analysis/TargetTransformInfoImpl.h | 18 + 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lib/Target/AArch64/AArch64TargetTransformInfo.h | 3 + lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp | 831 +- lib/Target/AArch64/CMakeLists.txt | 20 +- .../AArch64/Disassembler/AArch64Disassembler.cpp | 92 + .../AArch64/InstPrinter/AArch64InstPrinter.cpp | 77 +- .../AArch64/InstPrinter/AArch64InstPrinter.h | 4 +- .../AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp | 23 +- .../MCTargetDesc/AArch64MachObjectWriter.cpp | 54 +- lib/Target/AArch64/SVEInstrFormats.td | 391 + lib/Target/AMDGPU/AMDGPU.td | 18 +- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 17 +- lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 7 +- lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 13 +- lib/Target/AMDGPU/AMDGPUInstrInfo.cpp | 10 + lib/Target/AMDGPU/AMDGPUInstrInfo.h | 17 + lib/Target/AMDGPU/AMDGPUInstructions.td | 11 + lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 124 +- lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 5 +- lib/Target/AMDGPU/AMDGPUMachineFunction.h | 2 +- .../AMDGPU/AMDGPUOpenCLEnqueuedBlockLowering.cpp | 64 +- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 74 + lib/Target/AMDGPU/AMDGPURegisterInfo.cpp | 3 +- lib/Target/AMDGPU/AMDGPUSearchableTables.td | 99 + lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 6 +- lib/Target/AMDGPU/AMDGPUSubtarget.h | 33 +- lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 +- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 40 +- lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 6 + .../AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp | 3 +- lib/Target/AMDGPU/AMDILCFGStructurizer.cpp | 2 +- lib/Target/AMDGPU/AMDKernelCodeT.h | 10 +- lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 49 +- lib/Target/AMDGPU/BUFInstructions.td | 36 +- lib/Target/AMDGPU/CMakeLists.txt | 22 +- lib/Target/AMDGPU/DSInstructions.td | 6 + .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 19 +- lib/Target/AMDGPU/GCNIterativeScheduler.cpp | 2 +- .../AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp | 10 + lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h | 2 + .../MCTargetDesc/AMDGPUHSAMetadataStreamer.cpp | 20 +- lib/Target/AMDGPU/MIMGInstructions.td | 434 +- lib/Target/AMDGPU/R600ISelLowering.cpp | 2 +- lib/Target/AMDGPU/SIAnnotateControlFlow.cpp | 2 +- lib/Target/AMDGPU/SIDefines.h | 7 + lib/Target/AMDGPU/SIFoldOperands.cpp | 32 +- lib/Target/AMDGPU/SIFrameLowering.cpp | 89 +- lib/Target/AMDGPU/SIISelLowering.cpp | 348 +- lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 183 +- lib/Target/AMDGPU/SIInstrInfo.cpp | 48 +- lib/Target/AMDGPU/SIInstrInfo.td | 17 + lib/Target/AMDGPU/SIInstructions.td | 15 +- lib/Target/AMDGPU/SILowerI1Copies.cpp | 4 +- lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 7 +- lib/Target/AMDGPU/SIMachineFunctionInfo.h | 9 + lib/Target/AMDGPU/SIMachineScheduler.cpp | 58 +- lib/Target/AMDGPU/SIOptimizeExecMasking.cpp | 2 +- lib/Target/AMDGPU/SIPeepholeSDWA.cpp | 84 +- lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 + lib/Target/AMDGPU/SISchedule.td | 2 +- lib/Target/AMDGPU/SIShrinkInstructions.cpp | 2 +- lib/Target/AMDGPU/SMInstructions.td | 265 +- lib/Target/AMDGPU/SOPInstructions.td | 99 +- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 70 +- lib/Target/AMDGPU/Utils/AMDGPULaneDominator.cpp | 75 + lib/Target/AMDGPU/Utils/AMDGPULaneDominator.h | 24 + lib/Target/AMDGPU/Utils/AMDKernelCodeTInfo.h | 1 - lib/Target/AMDGPU/Utils/CMakeLists.txt | 1 + lib/Target/AMDGPU/VOP1Instructions.td | 71 +- lib/Target/AMDGPU/VOP2Instructions.td | 38 +- lib/Target/AMDGPU/VOP3Instructions.td | 40 +- lib/Target/AMDGPU/VOP3PInstructions.td | 4 +- lib/Target/AMDGPU/VOPCInstructions.td | 4 +- lib/Target/AMDGPU/VOPInstructions.td | 63 +- lib/Target/ARC/ARCAsmPrinter.cpp | 2 +- lib/Target/ARC/ARCInstrFormats.td | 2 +- lib/Target/ARC/ARCInstrInfo.td | 58 +- lib/Target/ARC/CMakeLists.txt | 13 +- lib/Target/ARM/ARMBaseInstrInfo.cpp | 12 +- lib/Target/ARM/ARMCallLowering.cpp | 2 +- lib/Target/ARM/ARMCallingConv.h | 3 + lib/Target/ARM/ARMCallingConv.td | 16 +- lib/Target/ARM/ARMComputeBlockSize.cpp | 1 + lib/Target/ARM/ARMFastISel.cpp | 2 +- lib/Target/ARM/ARMFrameLowering.cpp | 18 +- lib/Target/ARM/ARMFrameLowering.h | 2 + lib/Target/ARM/ARMISelDAGToDAG.cpp | 4 +- lib/Target/ARM/ARMISelLowering.cpp | 103 +- lib/Target/ARM/ARMISelLowering.h | 3 +- lib/Target/ARM/ARMInstrNEON.td | 155 +- lib/Target/ARM/ARMInstrVFP.td | 14 +- lib/Target/ARM/ARMInstructionSelector.cpp | 4 +- lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 16 +- lib/Target/ARM/ARMScheduleA57.td | 3 + lib/Target/ARM/ARMScheduleA9.td | 10 +- lib/Target/ARM/ARMScheduleR52.td | 45 +- lib/Target/ARM/ARMScheduleSwift.td | 37 +- lib/Target/ARM/ARMTargetMachine.cpp | 5 +- lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 161 +- lib/Target/ARM/CMakeLists.txt | 19 +- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 2 - lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 2 +- lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 2 +- lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp | 2 +- lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 20 +- lib/Target/ARM/MCTargetDesc/CMakeLists.txt | 1 - lib/Target/AVR/AVRISelLowering.cpp | 3 + lib/Target/AVR/CMakeLists.txt | 8 +- lib/Target/BPF/AsmParser/BPFAsmParser.cpp | 8 +- lib/Target/BPF/BPF.h | 2 + lib/Target/BPF/BPFISelDAGToDAG.cpp | 2 +- lib/Target/BPF/BPFISelLowering.cpp | 8 +- lib/Target/BPF/BPFMIPeephole.cpp | 294 +- lib/Target/BPF/BPFTargetMachine.cpp | 9 + lib/Target/BPF/CMakeLists.txt | 13 +- lib/Target/BPF/InstPrinter/BPFInstPrinter.cpp | 1 - lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp | 11 +- lib/Target/Hexagon/CMakeLists.txt | 5 +- lib/Target/Hexagon/Hexagon.td | 44 +- lib/Target/Hexagon/HexagonAsmPrinter.cpp | 95 +- lib/Target/Hexagon/HexagonAsmPrinter.h | 16 +- lib/Target/Hexagon/HexagonBlockRanges.cpp | 2 +- lib/Target/Hexagon/HexagonBranchRelaxation.cpp | 9 +- lib/Target/Hexagon/HexagonCommonGEP.cpp | 2 +- lib/Target/Hexagon/HexagonConstExtenders.cpp | 53 +- lib/Target/Hexagon/HexagonDepDecoders.h | 13 - lib/Target/Hexagon/HexagonDepIICScalar.td | 485 - lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 67 +- lib/Target/Hexagon/HexagonExpandCondsets.cpp | 7 +- lib/Target/Hexagon/HexagonFixupHwLoops.cpp | 10 +- lib/Target/Hexagon/HexagonFrameLowering.cpp | 4 +- lib/Target/Hexagon/HexagonGenInsert.cpp | 2 +- lib/Target/Hexagon/HexagonGenMux.cpp | 12 +- lib/Target/Hexagon/HexagonHardwareLoops.cpp | 1 + lib/Target/Hexagon/HexagonHazardRecognizer.cpp | 40 +- lib/Target/Hexagon/HexagonHazardRecognizer.h | 17 +- lib/Target/Hexagon/HexagonISelDAGToDAG.cpp | 253 +- lib/Target/Hexagon/HexagonISelDAGToDAG.h | 6 +- lib/Target/Hexagon/HexagonISelDAGToDAGHVX.cpp | 75 +- lib/Target/Hexagon/HexagonISelLowering.cpp | 321 +- lib/Target/Hexagon/HexagonISelLowering.h | 16 +- lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 90 +- lib/Target/Hexagon/HexagonInstrInfo.cpp | 233 +- lib/Target/Hexagon/HexagonInstrInfo.h | 6 +- lib/Target/Hexagon/HexagonIntrinsics.td | 11 +- lib/Target/Hexagon/HexagonLoopIdiomRecognition.cpp | 3 +- lib/Target/Hexagon/HexagonMachineScheduler.cpp | 341 +- lib/Target/Hexagon/HexagonMachineScheduler.h | 52 +- lib/Target/Hexagon/HexagonNewValueJump.cpp | 15 +- lib/Target/Hexagon/HexagonOptAddrMode.cpp | 192 +- lib/Target/Hexagon/HexagonPatterns.td | 242 +- lib/Target/Hexagon/HexagonPatternsHVX.td | 108 +- lib/Target/Hexagon/HexagonPseudo.td | 62 +- lib/Target/Hexagon/HexagonRegisterInfo.td | 52 +- lib/Target/Hexagon/HexagonSplitDouble.cpp | 44 +- lib/Target/Hexagon/HexagonStoreWidening.cpp | 20 +- lib/Target/Hexagon/HexagonSubtarget.cpp | 108 +- lib/Target/Hexagon/HexagonSubtarget.h | 11 + lib/Target/Hexagon/HexagonTargetTransformInfo.cpp | 228 +- lib/Target/Hexagon/HexagonTargetTransformInfo.h | 77 +- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp | 56 +- .../Hexagon/HexagonVectorLoopCarriedReuse.cpp | 1 + .../Hexagon/MCTargetDesc/HexagonInstPrinter.cpp | 19 +- .../Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp | 8 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 7 +- lib/Target/Hexagon/RDFDeadCode.cpp | 2 +- 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