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from 85e879897af [Hexagon] Speedup NumNodesBlocking calculation. NFCI. new 271bf6ebf9d AMDGPU: Use correct register names in inline assembly

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Summary of changes: lib/Target/AMDGPU/AMDGPURegAsmNames.inc | 349 +++++++++++++++++ lib/Target/AMDGPU/SIRegisterInfo.cpp | 59 +++ lib/Target/AMDGPU/SIRegisterInfo.h | 2 + test/CodeGen/AMDGPU/branch-relax-spill.ll | 420 ++++++++++----------- test/CodeGen/AMDGPU/exceed-max-sgprs.ll | 142 +++---- test/CodeGen/AMDGPU/flat-scratch-reg.ll | 14 +- test/CodeGen/AMDGPU/illegal-sgpr-to-vgpr-copy.ll | 20 +- test/CodeGen/AMDGPU/indirect-addressing-si.ll | 2 +- test/CodeGen/AMDGPU/inline-asm.ll | 12 +- test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.pk.u16.u8.ll | 16 +- test/CodeGen/AMDGPU/llvm.amdgcn.mqsad.u32.u8.ll | 34 +- test/CodeGen/AMDGPU/llvm.amdgcn.qsad.pk.u16.u8.ll | 12 +- test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll | 10 +- test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll | 88 ++--- test/CodeGen/AMDGPU/skip-if-dead.ll | 12 +- test/CodeGen/AMDGPU/spill-scavenge-offset.ll | 14 +- test/CodeGen/AMDGPU/undefined-subreg-liverange.ll | 6 +- 17 files changed, 811 insertions(+), 401 deletions(-) create mode 100644 lib/Target/AMDGPU/AMDGPURegAsmNames.inc