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from 4f55aa85a874 Merge tag 'fbdev-for-6.9-rc1' of git://git.kernel.org/pub/ [...] new e8aff71ca930 objtool/LoongArch: Enable objtool to be built new b2d23158e6c8 objtool/LoongArch: Implement instruction decoder new b8e85e6f3a09 objtool/x86: Separate arch-specific and generic parts new 3c7266cd7bc5 objtool/LoongArch: Enable orc to be built new d5ab2bc36c6b objtool: Check local label in add_dead_ends() new e91c5e4c21b0 objtool: Check local label in read_unwind_hints() new cb8a2ef0848c LoongArch: Add ORC stack unwinder support new 199cc14cb4f1 LoongArch: Add kernel livepatching support new 8b5db5e5337e LoongArch: Select ARCH_HAS_CURRENT_STACK_POINTER in Kconfig new f48ad26e5e57 LoongArch: Select HAVE_ARCH_USERFAULTFD_MINOR in Kconfig new c87e12e0e8c1 LoongArch: Change __my_cpu_offset definition to avoid mis- [...] new d42ab9af605e LoongArch: Move {dmw,tlb}_virt_to_page() definition to page.h new 82bf60a6fed8 LoongArch: Remove superfluous flush_dcache_page() definition new 9c68ece8b2a5 LoongArch: Define the __io_aw() hook as mmiowb() new fea1c949f6ca LoongArch/crypto: Clean up useless assignment operations new 1e3cd03c54b7 Merge tag 'loongarch-6.9' of git://git.kernel.org/pub/scm/ [...] new 3a6dd5f614a1 riscv: remove unneeded #include <asm-generic/export.h> new 021d23428bdb RISC-V: build: Allow LTO to be selected new df513ed49f00 RISC-V: add helper function to read the vector VLEN new 34ca4ec628de RISC-V: add TOOLCHAIN_HAS_VECTOR_CRYPTO new 178f3856436c RISC-V: hook new crypto subdir into build-system new eb24af5d7a05 crypto: riscv - add vector crypto accelerated AES-{ECB,CBC [...] new bb54668837a0 crypto: riscv - add vector crypto accelerated ChaCha20 new 600a3853dfa0 crypto: riscv - add vector crypto accelerated GHASH new 8c8e40470ffe crypto: riscv - add vector crypto accelerated SHA-{256,224} new b3415925a08b crypto: riscv - add vector crypto accelerated SHA-{512,384} new 563a5255afa2 crypto: riscv - add vector crypto accelerated SM3 new b8d06352bbf3 crypto: riscv - add vector crypto accelerated SM4 new 67daf84203a0 Merge patch series "RISC-V crypto with reworked asm files" new d38e2e7bcb3e clocksource: extend the max_delta_ns of timer-riscv and ti [...] new e2d6b54b935a Revert "RISC-V: mark hibernation as nonportable" new 71a5849aedaa mm: Change mmap_rnd_bits_max to __ro_after_init new 7df1ff5a5cd6 riscv: mm: Update mmap_rnd_bits_max new d7e76ce7b76e Merge patch series "riscv: Increase mmap_rnd_bits_max on Sv48/57" new 40d1bb92a493 riscv: tlb: convert __p*d_free_tlb() to inline functions new 69be3fb111e7 riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMU new 3f910b7a522e riscv: enable HAVE_FAST_GUP if MMU new 7f43d57b900d Merge patch series "riscv: support fast gup" new 5014396af9bb riscv: blacklist assembly symbols for kprobe new dded618c07fd RISC-V: Remove duplicated include in smpboot.c new 05d450aabd73 riscv: Support RANDOMIZE_KSTACK_OFFSET new cb4ede926134 riscv: Avoid code duplication with generic bitops implementation new d6cfd1770f20 membarrier: riscv: Add full memory barrier in switch_mm() new a14d11a0f5f4 membarrier: Create Documentation/scheduler/membarrier.rst new 4ff4c745a16c locking: Introduce prepare_sync_core_cmd() new cd9b29014dc6 membarrier: riscv: Provide core serializing command new 0420af54c2c2 Merge patch series "membarrier: riscv: Core serializing command" new 45e0b0fd6dc5 riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520 new aba3f18aba6b Merge commit '3aff0c459e77' into for-next new 886516fae2b7 RISC-V: fix check for zvkb with tip-of-tree clang new b8e00bdf253e Merge tag 'irq-for-riscv-02-23-24' of ssh://gitolite.kerne [...] new be5e8872b3fb riscv: errata: Rename defines for Andes new b88727d554f0 dt-bindings: riscv: Add Andes interrupt controller compati [...] new 95113bb70515 riscv: dts: renesas: r9a07g043f: Update compatible string [...] new ea0e0178e101 perf: RISC-V: Eliminate redundant interrupt enable/disable [...] new bc969d6cc96a perf: RISC-V: Introduce Andes PMU to support perf event sampling new 61609bf2b29d dt-bindings: riscv: Add Andes PMU extension description new 270fc77e7b0e riscv: dts: renesas: Add Andes PMU extension for r9a07g043f new f5102e31c209 riscv: andes: Support specifying symbolic firmware and har [...] new a13a806dfb8a Merge patch series "Support Andes PMU extension" new 5a83e7313ee1 riscv: lib: Introduce has_fast_unaligned_access() new 313130c62cf1 riscv: Only check online cpus for emulated accesses new 6e5ce7f2eae3 riscv: Decouple emulated unaligned accesses from access speed new f413aae96cda riscv: Set unaligned access speed at compile time new 2b2ca354674b Merge patch series "riscv: Use Kconfig to set unaligned ac [...] new 2bb7e0c49302 riscv: Fix compilation error with FAST_GUP and rv32 new 3b6be8d23575 Merge patch "riscv: Fix compilation error with FAST_GUP and rv32" new 0fd283cb64c0 Merge patch series "Support Andes PMU extension" new 099dbac6e90c Merge patch series "riscv: Use Kconfig to set unaligned ac [...] new b5b4287accd7 riscv: mm: Use hint address in mmap if available new 73d05262a2ca selftests: riscv: Generalize mm selftests new 371a3c2055db docs: riscv: Define behavior of mmap new 07f2c040fa51 Merge patch series "riscv: mm: Extend mappable memory up t [...] new 700c2d9b1b17 riscv: vector: Fix a typo of preempt_v new 6be7ee4bebd1 riscv: Improve arch_get_mmap_end() macro new 9dc30419248f riscv: Replace direct thread flag check with is_compat_task() new 4c0b5a451675 riscv: add compile-time test into is_compat_task() new 5917ea17ad07 riscv: Introduce is_compat_thread() into compat.h new 2a8986fc5e1c riscv: Introduce set_compat_task() in asm/compat.h new 728e7ea2b56d Merge patch series "riscv: Introduce compat-mode helpers & [...] new 6649182a383c cpuidle: RISC-V: Move few functions to arch/riscv new 4877fc92142f ACPI: RISC-V: Add LPI driver new 359df7c5be4b ACPI: Enable ACPI_PROCESSOR for RISC-V new 85ab6fdf3791 Merge patch series "RISC-V: ACPI: Add LPI support" new 28e4748e5e3d riscv: Use kcalloc() instead of kzalloc() new 01261e24cfab riscv: Only flush the mm icache when setting an exec pte new 30f3ffbee86b ACPI: RISC-V: Add CPPC driver new 7ee1378736f0 cpufreq: Move CPPC configs to common Kconfig and add RISC-V new 282b9df4e960 RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ new 028d1aee1f07 Merge patch series "RISC-V: ACPI: Enable CPPC based cpufre [...] new da215b089b5d crypto: riscv - parallelize AES-CBC decryption new c70dfa4a2723 crypto: riscv - add vector crypto accelerated AES-CBC-CTS new 89f4fd7b1ab7 riscv/barrier: Define __{mb,rmb,wmb} new b3c8064ccc44 riscv/barrier: Define RISCV_FULL_BARRIER new c85688e2b0f0 riscv/barrier: Consolidate fence definitions new 9133e6e6908d riscv/barrier: Add missing space after ',' new cd6c916ccf21 Merge patch series "riscv/barrier: tidying up barrier-rela [...] new eeb7a8933e71 Merge patch series "riscv: mm: Extend mappable memory up t [...] new a9ad73295cc1 riscv: Fix syscall wrapper for >word-size arguments new c150b809f7de Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.or [...]

The 100 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: Documentation/arch/riscv/vm-layout.rst | 16 +- Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +- .../devicetree/bindings/riscv/extensions.yaml | 7 + .../sched/membarrier-sync-core/arch-support.txt | 18 +- Documentation/scheduler/index.rst | 1 + Documentation/scheduler/membarrier.rst | 39 ++ MAINTAINERS | 4 +- arch/loongarch/Kconfig | 8 + arch/loongarch/Kconfig.debug | 11 + arch/loongarch/Makefile | 23 +- arch/loongarch/crypto/crc32-loongarch.c | 2 - arch/loongarch/include/asm/Kbuild | 3 + arch/loongarch/include/asm/bug.h | 1 + arch/loongarch/include/asm/cacheflush.h | 3 - arch/loongarch/include/asm/exception.h | 2 + arch/loongarch/include/asm/io.h | 2 + arch/loongarch/include/asm/module.h | 7 + arch/loongarch/include/asm/orc_header.h | 18 + arch/loongarch/include/asm/orc_lookup.h | 31 + arch/loongarch/include/asm/orc_types.h | 58 ++ arch/loongarch/include/asm/page.h | 3 + arch/loongarch/include/asm/percpu.h | 7 +- arch/loongarch/include/asm/pgtable.h | 3 - arch/loongarch/include/asm/qspinlock.h | 18 - arch/loongarch/include/asm/stackframe.h | 3 + arch/loongarch/include/asm/thread_info.h | 2 + arch/loongarch/include/asm/unwind.h | 20 +- arch/loongarch/include/asm/unwind_hints.h | 28 + arch/loongarch/kernel/Makefile | 4 + arch/loongarch/kernel/entry.S | 5 + arch/loongarch/kernel/fpu.S | 7 + arch/loongarch/kernel/genex.S | 6 + arch/loongarch/kernel/lbt.S | 3 + arch/loongarch/kernel/mcount_dyn.S | 6 + arch/loongarch/kernel/module.c | 22 +- arch/loongarch/kernel/relocate_kernel.S | 7 +- arch/loongarch/kernel/rethook_trampoline.S | 1 + arch/loongarch/kernel/setup.c | 2 + arch/loongarch/kernel/stacktrace.c | 41 ++ arch/loongarch/kernel/traps.c | 42 +- arch/loongarch/kernel/unwind_orc.c | 528 +++++++++++++++++ arch/loongarch/kernel/vmlinux.lds.S | 3 + arch/loongarch/kvm/switch.S | 9 +- arch/loongarch/lib/clear_user.S | 3 + arch/loongarch/lib/copy_user.S | 3 + arch/loongarch/lib/memcpy.S | 3 + arch/loongarch/lib/memset.S | 3 + arch/loongarch/mm/tlb.c | 27 +- arch/loongarch/mm/tlbex.S | 9 + arch/loongarch/vdso/Makefile | 1 + arch/riscv/Kbuild | 1 + arch/riscv/Kconfig | 80 ++- arch/riscv/Makefile | 5 + arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 +- arch/riscv/configs/defconfig | 3 + arch/riscv/crypto/Kconfig | 93 +++ arch/riscv/crypto/Makefile | 23 + arch/riscv/crypto/aes-macros.S | 156 +++++ arch/riscv/crypto/aes-riscv64-glue.c | 637 +++++++++++++++++++++ arch/riscv/crypto/aes-riscv64-zvkned-zvbb-zvkg.S | 312 ++++++++++ arch/riscv/crypto/aes-riscv64-zvkned-zvkb.S | 146 +++++ arch/riscv/crypto/aes-riscv64-zvkned.S | 339 +++++++++++ arch/riscv/crypto/chacha-riscv64-glue.c | 101 ++++ arch/riscv/crypto/chacha-riscv64-zvkb.S | 294 ++++++++++ arch/riscv/crypto/ghash-riscv64-glue.c | 168 ++++++ arch/riscv/crypto/ghash-riscv64-zvkg.S | 72 +++ arch/riscv/crypto/sha256-riscv64-glue.c | 137 +++++ .../crypto/sha256-riscv64-zvknha_or_zvknhb-zvkb.S | 225 ++++++++ arch/riscv/crypto/sha512-riscv64-glue.c | 133 +++++ arch/riscv/crypto/sha512-riscv64-zvknhb-zvkb.S | 203 +++++++ arch/riscv/crypto/sm3-riscv64-glue.c | 112 ++++ arch/riscv/crypto/sm3-riscv64-zvksh-zvkb.S | 123 ++++ arch/riscv/crypto/sm4-riscv64-glue.c | 107 ++++ arch/riscv/crypto/sm4-riscv64-zvksed-zvkb.S | 117 ++++ arch/riscv/errata/andes/errata.c | 10 +- arch/riscv/include/asm/asm.h | 10 + arch/riscv/include/asm/atomic.h | 17 +- arch/riscv/include/asm/barrier.h | 21 +- arch/riscv/include/asm/bitops.h | 138 +---- arch/riscv/include/asm/cmpxchg.h | 5 +- arch/riscv/include/asm/compat.h | 19 + arch/riscv/include/asm/cpufeature.h | 31 +- arch/riscv/include/asm/elf.h | 11 +- arch/riscv/include/asm/errata_list.h | 13 +- arch/riscv/include/asm/fence.h | 10 +- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/io.h | 8 +- arch/riscv/include/asm/membarrier.h | 50 ++ arch/riscv/include/asm/mmio.h | 5 +- arch/riscv/include/asm/mmiowb.h | 2 +- arch/riscv/include/asm/pgalloc.h | 67 ++- arch/riscv/include/asm/pgtable.h | 32 +- arch/riscv/include/asm/processor.h | 31 +- arch/riscv/include/asm/simd.h | 4 +- arch/riscv/include/asm/suspend.h | 3 + arch/riscv/include/asm/sync_core.h | 29 + arch/riscv/include/asm/syscall_wrapper.h | 53 +- arch/riscv/include/asm/tlb.h | 18 + arch/riscv/include/asm/vector.h | 11 + arch/riscv/include/asm/vendorid_list.h | 2 +- arch/riscv/kernel/Makefile | 4 +- arch/riscv/kernel/alternative.c | 2 +- arch/riscv/kernel/cpufeature.c | 256 +-------- arch/riscv/kernel/entry.S | 3 + arch/riscv/kernel/pi/Makefile | 3 + arch/riscv/kernel/ptrace.c | 6 +- arch/riscv/kernel/smpboot.c | 1 - arch/riscv/kernel/suspend.c | 49 ++ arch/riscv/kernel/sys_hwprobe.c | 13 + arch/riscv/kernel/traps.c | 17 +- arch/riscv/kernel/traps_misaligned.c | 17 +- arch/riscv/kernel/unaligned_access_speed.c | 281 +++++++++ arch/riscv/lib/csum.c | 7 +- arch/riscv/lib/uaccess_vector.S | 1 - arch/riscv/mm/cacheflush.c | 4 +- arch/riscv/mm/context.c | 2 + arch/riscv/mm/init.c | 6 + arch/riscv/mm/pgtable.c | 2 +- crypto/Kconfig | 3 + drivers/acpi/Kconfig | 2 +- drivers/acpi/riscv/Makefile | 4 +- drivers/acpi/riscv/cppc.c | 157 +++++ drivers/acpi/riscv/cpuidle.c | 81 +++ drivers/clocksource/timer-clint.c | 2 +- drivers/clocksource/timer-riscv.c | 2 +- drivers/cpufreq/Kconfig | 29 + drivers/cpufreq/Kconfig.arm | 26 - drivers/cpuidle/cpuidle-riscv-sbi.c | 49 +- drivers/perf/Kconfig | 14 + drivers/perf/riscv_pmu_sbi.c | 37 +- include/asm-generic/bitops/__ffs.h | 8 +- include/asm-generic/bitops/__fls.h | 8 +- include/asm-generic/bitops/ffs.h | 8 +- include/asm-generic/bitops/fls.h | 8 +- include/linux/compiler.h | 9 + include/linux/mm.h | 2 +- include/linux/sync_core.h | 16 +- init/Kconfig | 3 + kernel/sched/core.c | 16 +- kernel/sched/membarrier.c | 13 +- mm/mmap.c | 2 +- scripts/Makefile | 7 +- tools/arch/loongarch/include/asm/inst.h | 161 ++++++ tools/arch/loongarch/include/asm/orc_types.h | 58 ++ tools/include/linux/bitops.h | 11 + tools/objtool/Makefile | 4 + tools/objtool/arch/loongarch/Build | 3 + tools/objtool/arch/loongarch/decode.c | 356 ++++++++++++ .../objtool/arch/loongarch/include/arch/cfi_regs.h | 22 + tools/objtool/arch/loongarch/include/arch/elf.h | 30 + .../objtool/arch/loongarch/include/arch/special.h | 33 ++ tools/objtool/arch/loongarch/orc.c | 171 ++++++ tools/objtool/arch/loongarch/special.c | 15 + tools/objtool/arch/x86/Build | 1 + tools/objtool/arch/x86/orc.c | 188 ++++++ tools/objtool/check.c | 52 +- tools/objtool/include/objtool/elf.h | 1 + tools/objtool/include/objtool/orc.h | 14 + tools/objtool/orc_dump.c | 69 +-- tools/objtool/orc_gen.c | 113 +--- .../riscv/{sifive/u74 => andes/ax45}/firmware.json | 0 .../arch/riscv/andes/ax45/instructions.json | 127 ++++ .../pmu-events/arch/riscv/andes/ax45/memory.json | 57 ++ .../arch/riscv/andes/ax45/microarch.json | 77 +++ tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + tools/testing/selftests/riscv/mm/mmap_bottomup.c | 23 +- tools/testing/selftests/riscv/mm/mmap_default.c | 23 +- tools/testing/selftests/riscv/mm/mmap_test.h | 107 ++-- 168 files changed, 7155 insertions(+), 1013 deletions(-) create mode 100644 Documentation/scheduler/membarrier.rst create mode 100644 arch/loongarch/include/asm/orc_header.h create mode 100644 arch/loongarch/include/asm/orc_lookup.h create mode 100644 arch/loongarch/include/asm/orc_types.h delete mode 100644 arch/loongarch/include/asm/qspinlock.h create mode 100644 arch/loongarch/include/asm/unwind_hints.h create mode 100644 arch/loongarch/kernel/unwind_orc.c create mode 100644 arch/riscv/crypto/Kconfig create mode 100644 arch/riscv/crypto/Makefile create mode 100644 arch/riscv/crypto/aes-macros.S create mode 100644 arch/riscv/crypto/aes-riscv64-glue.c create mode 100644 arch/riscv/crypto/aes-riscv64-zvkned-zvbb-zvkg.S create mode 100644 arch/riscv/crypto/aes-riscv64-zvkned-zvkb.S create mode 100644 arch/riscv/crypto/aes-riscv64-zvkned.S create mode 100644 arch/riscv/crypto/chacha-riscv64-glue.c create mode 100644 arch/riscv/crypto/chacha-riscv64-zvkb.S create mode 100644 arch/riscv/crypto/ghash-riscv64-glue.c create mode 100644 arch/riscv/crypto/ghash-riscv64-zvkg.S create mode 100644 arch/riscv/crypto/sha256-riscv64-glue.c create mode 100644 arch/riscv/crypto/sha256-riscv64-zvknha_or_zvknhb-zvkb.S create mode 100644 arch/riscv/crypto/sha512-riscv64-glue.c create mode 100644 arch/riscv/crypto/sha512-riscv64-zvknhb-zvkb.S create mode 100644 arch/riscv/crypto/sm3-riscv64-glue.c create mode 100644 arch/riscv/crypto/sm3-riscv64-zvksh-zvkb.S create mode 100644 arch/riscv/crypto/sm4-riscv64-glue.c create mode 100644 arch/riscv/crypto/sm4-riscv64-zvksed-zvkb.S create mode 100644 arch/riscv/include/asm/membarrier.h create mode 100644 arch/riscv/include/asm/sync_core.h create mode 100644 arch/riscv/kernel/unaligned_access_speed.c create mode 100644 drivers/acpi/riscv/cppc.c create mode 100644 drivers/acpi/riscv/cpuidle.c create mode 100644 tools/arch/loongarch/include/asm/inst.h create mode 100644 tools/arch/loongarch/include/asm/orc_types.h create mode 100644 tools/objtool/arch/loongarch/Build create mode 100644 tools/objtool/arch/loongarch/decode.c create mode 100644 tools/objtool/arch/loongarch/include/arch/cfi_regs.h create mode 100644 tools/objtool/arch/loongarch/include/arch/elf.h create mode 100644 tools/objtool/arch/loongarch/include/arch/special.h create mode 100644 tools/objtool/arch/loongarch/orc.c create mode 100644 tools/objtool/arch/loongarch/special.c create mode 100644 tools/objtool/arch/x86/orc.c create mode 100644 tools/objtool/include/objtool/orc.h copy tools/perf/pmu-events/arch/riscv/{sifive/u74 => andes/ax45}/firmware.json (100%) create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/instructions.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/memory.json create mode 100644 tools/perf/pmu-events/arch/riscv/andes/ax45/microarch.json