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from cf7570b9ac8 [tblgen][PredicateExpander] Add the ability to describe mor [...] new 893f08bea2e [InstSimplify] fold icmp based on range of abs/nabs new 91533e99d40 AMDGPU: Remove PHI loop condition optimization new 776a459079f AMDGPU: Rewrite SILowerI1Copies to always stay on SALU

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Summary of changes: include/llvm/IR/IntrinsicsAMDGPU.td | 8 - lib/Analysis/InstructionSimplify.cpp | 42 ++ lib/Target/AMDGPU/AMDGPUInstrInfo.td | 8 - lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 +- lib/Target/AMDGPU/SIAnnotateControlFlow.cpp | 86 +-- lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 8 +- lib/Target/AMDGPU/SIInstructions.td | 16 - lib/Target/AMDGPU/SILowerControlFlow.cpp | 29 - lib/Target/AMDGPU/SILowerI1Copies.cpp | 830 ++++++++++++++++++--- lib/Target/AMDGPU/Utils/AMDGPULaneDominator.cpp | 75 -- lib/Target/AMDGPU/Utils/AMDGPULaneDominator.h | 24 - lib/Target/AMDGPU/Utils/CMakeLists.txt | 1 - test/CodeGen/AMDGPU/add_i1.ll | 4 +- test/CodeGen/AMDGPU/i1-copy-from-loop.ll | 30 +- test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll | 38 + test/CodeGen/AMDGPU/i1-copy-phi.ll | 16 +- test/CodeGen/AMDGPU/inline-asm.ll | 9 +- test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll | 30 +- test/CodeGen/AMDGPU/loop_break.ll | 97 +-- test/CodeGen/AMDGPU/multi-divergent-exit-region.ll | 47 +- test/CodeGen/AMDGPU/multilevel-break.ll | 109 ++- test/CodeGen/AMDGPU/nested-loop-conditions.ll | 44 +- test/CodeGen/AMDGPU/select-opt.ll | 1 - test/CodeGen/AMDGPU/sgpr-control-flow.ll | 30 +- test/CodeGen/AMDGPU/si-annotate-cf.ll | 49 +- test/CodeGen/AMDGPU/sub_i1.ll | 4 +- test/CodeGen/AMDGPU/valu-i1.ll | 24 +- test/CodeGen/AMDGPU/waitcnt-looptest.ll | 2 +- test/Transforms/InstSimplify/icmp-abs-nabs.ll | 90 +-- 29 files changed, 1135 insertions(+), 618 deletions(-) delete mode 100644 lib/Target/AMDGPU/Utils/AMDGPULaneDominator.cpp delete mode 100644 lib/Target/AMDGPU/Utils/AMDGPULaneDominator.h create mode 100644 test/CodeGen/AMDGPU/i1-copy-phi-uniform-branch.ll