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from 60e99901aef LoongArch: Fix up r15-4130 new 34ae3a992a0 [RISC-V][PR target/116615] RISC-V: Use default LOGICAL_OP_N [...] new c94adf02d31 aarch64: Expand CTZ to RBIT + CLZ for SVE [PR109498]

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Summary of changes: gcc/config/aarch64/aarch64-sve.md | 17 +++++++++ gcc/config/riscv/riscv.h | 2 -- gcc/testsuite/gcc.target/aarch64/sve/ctz.c | 49 ++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/cset-sext-sfb.c | 2 +- 4 files changed, 67 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ctz.c