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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allnoconfig in repository toolchain/ci/llvm-project.

from 89abe1cf83a [InstCombine] foldICmpUsingKnownBits - use KnownBits signed [...] adds df812115e3c [CodeGen, Transforms] Use llvm::any_of (NFC) adds e457896a6ef [CodeGen] Remove unused function hasInlineAsmMemConstraint (NFC) adds ff3749fc793 [NFC] SimplifyCFGOpt::simplifyUnreachable(): pacify unused [...] adds b3021a72a6d [IR][InstCombine] Add m_ImmConstant(), that matches on non- [...] adds da4c7e15df3 [NFC][InstCombine] Autogenerate check lines in vec_shuffle.ll test adds 1fda23367d4 [NFC][InstCombine] Add test for `a & ~(a ^ b)` pattern adds 5b78303433c [InstCombine] Fold `a & ~(a ^ b)` to `x & y` adds 8001dcbd50c [NFC][InstCombine] Add test coverage for `(x ^ C) ^ y` pattern adds d9ebaeeb468 [InstCombine] Hoist xor-by-constant from xor-by-value adds 6e074a8324d [NFC][LoopIdiom] Improve test coverage for 'left-shift-unti [...] adds 25aebe2ccfb [LoopIdiom] 'left-shift-until-bittest': keep no-wrap flags [...] adds afd03cd3358 [RISCV] Define vector single-width reduction intrinsic. adds 912740a864f [RISCV] Add intrinsics for vrgather instruction adds 351c216f36a [RISCV] Define vector mask-register logical intrinsics. adds d6ff5cf995d [Target] Use llvm::any_of (NFC) adds da4a637e991 [RISCV] Define vpopc/vfirst intrinsics. adds e0721a09922 [AArch64][GlobalISel] Notify observer of mutated instructio [...] adds 438bc157a47 [libObject] - Add more ELF types to LLVM_ELF_IMPORT_TYPES_E [...] adds 177779e8dd9 [llvm-readelf/obj] - Improve the warning reported when unab [...] adds 893c84d71c4 [obj2yaml] - Dump the content of a broken hash table properly. adds a2ca6bbda61 [Flang][OpenMP] Add semantic check for OpenMP Private, Firs [...] adds 621ad468d99 [mlir] Async: lowering async.value to LLVM adds 61422c8b661 [mlir] Async: add support for lowering async value operands [...] adds b96a6ea0a94 [BasicAA] Make sure context instruction is symmetric adds a3614a31c46 [BasicAA] Pass context instruction to isKnownNonZero() new b0e6007c825 [InstCombine] Add additional tests for known non zero (NFC) new 35676a4f9a5 [InstCombine] Generalize icmp handling in isKnownNonZero()

The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: flang/lib/Semantics/resolve-directives.cpp | 41 +- flang/test/Semantics/omp-private03.f90 | 39 + llvm/include/llvm/Analysis/BasicAliasAnalysis.h | 3 + llvm/include/llvm/CodeGen/Analysis.h | 5 - llvm/include/llvm/IR/IntrinsicsRISCV.td | 74 + llvm/include/llvm/IR/PatternMatch.h | 43 +- llvm/include/llvm/Object/ELF.h | 26 - llvm/include/llvm/Object/ELFObjectFile.h | 9 - llvm/include/llvm/Object/ELFTypes.h | 30 +- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 11 +- llvm/lib/Analysis/ValueTracking.cpp | 77 +- llvm/lib/CodeGen/Analysis.cpp | 21 - llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp | 9 +- llvm/lib/CodeGen/MultiHazardRecognizer.cpp | 7 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 7 - llvm/lib/ObjectYAML/ELFEmitter.cpp | 16 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 6 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 + .../Target/AMDGPU/AMDGPURewriteOutArguments.cpp | 7 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 5 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 364 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 4 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 15 + .../Transforms/InstCombine/InstCombineCalls.cpp | 4 +- .../Transforms/InstCombine/InstCombineNegator.cpp | 3 +- .../InstCombine/InstructionCombining.cpp | 7 +- .../Instrumentation/ControlHeightReduction.cpp | 7 +- llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 50 +- llvm/lib/Transforms/Utils/CodeMoverUtils.cpp | 45 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 1 + llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +- .../test/Analysis/BasicAA/assume-index-positive.ll | 16 + llvm/test/Analysis/BasicAA/sequential-gep.ll | 11 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 3624 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 4630 ++++++++++++++++++++ llvm/test/Transforms/Attributor/nonnull.ll | 50 +- llvm/test/Transforms/InstCombine/and-xor-or.ll | 43 + .../hoist-xor-by-constant-from-xor-by-value.ll | 75 + .../invert-variable-mask-in-masked-merge-scalar.ll | 5 +- .../invert-variable-mask-in-masked-merge-vector.ll | 5 +- llvm/test/Transforms/InstCombine/known-non-zero.ll | 100 +- llvm/test/Transforms/InstCombine/or-xor.ll | 68 +- .../unfold-masked-merge-with-const-mask-scalar.ll | 6 +- .../unfold-masked-merge-with-const-mask-vector.ll | 6 +- .../InstCombine/vec_shuffle-inseltpoison.ll | 4 +- llvm/test/Transforms/InstCombine/vec_shuffle.ll | 12 +- llvm/test/Transforms/InstCombine/xor2.ll | 44 +- .../LoopIdiom/X86/left-shift-until-bittest.ll | 1875 ++++---- llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 10 +- llvm/test/tools/obj2yaml/ELF/hash-section.yaml | 21 + llvm/tools/llvm-lipo/llvm-lipo.cpp | 5 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 66 +- llvm/tools/obj2yaml/elf2yaml.cpp | 22 +- mlir/include/mlir/ExecutionEngine/AsyncRuntime.h | 30 + mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 576 ++- mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt | 2 + mlir/lib/ExecutionEngine/AsyncRuntime.cpp | 69 +- .../Conversion/AsyncToLLVM/convert-to-llvm.mlir | 92 + mlir/test/mlir-cpu-runner/async-value.mlir | 81 + 104 files changed, 31284 insertions(+), 1358 deletions(-) create mode 100644 flang/test/Semantics/omp-private03.f90 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll create mode 100644 llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor [...] create mode 100644 mlir/test/mlir-cpu-runner/async-value.mlir