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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allmodconfig in repository toolchain/ci/llvm-project.

from 984d08c680a Expand on the qfProcessInfo documentation, add examples fro [...] adds 784892c9641 [MachineOutliner] Disable outlining from noreturn functions adds 442ddffe138 [clang] fix a typo from r372531 adds 4f75a73796f Use named constant to indicate all lanes, to handle 32 and [...] adds 68eefbb0643 [lit] Use better name for "test in parallel" concept adds 68d01d94290 [debugserver] Don't link against Cocoa, it's not needed. adds b3e3934347f Add an off-by-default option to enable testing for gdb pret [...] adds 6a954748c8b [NFC][InstCombine] Tests for right-shift shift amount reass [...] adds 3c56cc920fb [NFC][InstCombine] Tests for bit test via highest sign-bit [...] adds 007452532b3 [NFC][InstCombine] Autogenerate icmp-shr-lt-gt.ll test adds ae738641d53 [NFC][InstCombine] Autogenerate shift.ll test adds f304d4d185d [InstCombine] Right-shift shift amount reassociation with t [...] adds fb5af8b9b93 [InstCombine] Fold 'icmp eq/ne (?trunc (lshr/ashr %x, bitwi [...] adds 50428826988 [MachO] Move nlist parsing into helper function (NFC) adds cd5cd7d14c7 [test] Run TestLaunchWithShellExpand with /bin/sh on POSIX. adds 67cfa79c010 Revert [CodeGen] Do the Simple Early Return in block-placem [...] adds 58fd6b5b9c8 [libomptarget][nfc] Update remaining uint32 to use lanemask_t adds 6a2673605e5 Invalidate assumption cache before outlining. adds fadc84ae9a9 [libc++] Localize common build flags into a single CMake function adds 9627b26c40a [libc++] Guard cxx_experimental settings behind LIBCXX_ENAB [...] adds 4e5d9e120be [MachO] Reduce indentation further in ParseSymtab (NFC) adds 50afaa9d34d Add a unittest to verify for assumption cache adds ea835f5ce84 [RISCV] Added missing ImmLeaf predicates adds 9fe5d730c70 [Test] Add a test case fo a missed oppurtunity in implicit [...] adds d5a4dad2061 Fix a *nasty* miscompile in experimental unordered atomic lowering adds 482f4d9aa9d Expose ProvidePositionalOption as a public API adds 559265c8daf [Diagnostics] Use Expr::isKnownToHaveBooleanValue() to chec [...] adds 3acc649b86f [NFCI] Slightly improve warning message adds 68f58a75a76 Do not install lit-cpuid adds b1f0183e572 [UnitTests] Try and pacify gcc-5 adds 375a84bb75a [clang-format] SpacesInSquareBrackets should affect lambdas [...] adds f609c0a303e BranchFolding - IsBetterFallthrough - assert non-null point [...] adds 20692a0d3d3 SemaStmt - silence static analyzer getAs<> null dereference [...] adds 0e82722f9a1 Remove redundant !HasDependentValue check. NFCI. adds 22b68731956 TreeTransform - silence static analyzer getAs<> null derefe [...] adds f4cc3b3e10e SemaTemplate - silence static analyzer getAs<> null derefer [...] adds 83b81c1f6ee [Diagnostics] Highlight expr's source range for -Wbool-operation adds 43bbca92284 RewriteObjC - silence static analyzer getAs<> null derefere [...] adds 41c934acaf8 [SelectionDAG] Add tests for LKK algorithm adds 68f21b360b9 Try to fix sphinx indentation error adds 9ecacb0d54f [X86] lowerShuffleAsLanePermuteAndRepeatedMask - variable r [...] adds e2321bb4488 [SLP] avoid reduction transform on patterns that the backen [...] new 8815be04ec1 [X86][AVX] Push sign extensions of comparison bool results [...]

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Summary of changes: clang/docs/ClangFormatStyleOptions.rst | 3 +- clang/docs/ReleaseNotes.rst | 8 +- clang/include/clang/Basic/DiagnosticSemaKinds.td | 2 +- clang/lib/Format/TokenAnnotator.cpp | 7 +- clang/lib/Frontend/Rewrite/RewriteObjC.cpp | 15 +- clang/lib/Sema/SemaChecking.cpp | 2 +- clang/lib/Sema/SemaExpr.cpp | 3 +- clang/lib/Sema/SemaStmt.cpp | 12 +- clang/lib/Sema/SemaTemplate.cpp | 8 +- clang/lib/Sema/TreeTransform.h | 8 +- clang/test/Sema/warn-bitwise-negation-bool.c | 2 + .../test/Sema/warn-integer-constants-in-ternary.c | 2 +- clang/test/SemaCXX/warn-xor-as-pow.cpp | 2 +- clang/unittests/Format/FormatTest.cpp | 7 +- libcxx/CMakeLists.txt | 12 + libcxx/src/CMakeLists.txt | 30 +- libcxx/test/CMakeLists.txt | 16 +- .../TestLaunchWithShellExpand.py | 4 + .../Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp | 384 +++-- lldb/tools/debugserver/source/CMakeLists.txt | 2 - lldb/utils/lit-cpuid/CMakeLists.txt | 2 +- llvm/include/llvm/Analysis/TargetTransformInfo.h | 10 + llvm/include/llvm/Support/CommandLine.h | 3 + llvm/include/llvm/Transforms/Utils/CodeExtractor.h | 5 + llvm/lib/Analysis/TargetTransformInfo.cpp | 53 + llvm/lib/CodeGen/BranchFolding.cpp | 2 + llvm/lib/CodeGen/MachineBlockPlacement.cpp | 46 - llvm/lib/CodeGen/MachineOutliner.cpp | 6 + .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 7 +- llvm/lib/Support/CommandLine.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 6 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 86 +- llvm/lib/Transforms/IPO/HotColdSplitting.cpp | 5 - .../Transforms/InstCombine/InstCombineCompares.cpp | 28 + .../Transforms/InstCombine/InstCombineShifts.cpp | 34 +- llvm/lib/Transforms/Utils/CodeExtractor.cpp | 28 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 15 +- .../CodeGen/AArch64/machine-outliner-noreturn.mir | 56 + llvm/test/CodeGen/AArch64/srem-lkk.ll | 149 ++ llvm/test/CodeGen/AArch64/srem-vector-lkk.ll | 324 ++++ llvm/test/CodeGen/AArch64/urem-lkk.ll | 103 ++ llvm/test/CodeGen/AArch64/urem-vector-lkk.ll | 267 ++++ llvm/test/CodeGen/PowerPC/block-placement.mir | 12 +- llvm/test/CodeGen/PowerPC/srem-lkk.ll | 149 ++ llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 1675 +++++++++++++++++++ llvm/test/CodeGen/PowerPC/urem-lkk.ll | 106 ++ llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll | 1338 ++++++++++++++++ llvm/test/CodeGen/RISCV/srem-lkk.ll | 583 +++++++ llvm/test/CodeGen/RISCV/srem-vector-lkk.ll | 1689 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/urem-lkk.ll | 354 ++++ llvm/test/CodeGen/RISCV/urem-vector-lkk.ll | 1419 ++++++++++++++++ llvm/test/CodeGen/X86/atomic-unordered.ll | 78 +- llvm/test/CodeGen/X86/bitcast-and-setcc-256.ll | 161 +- llvm/test/CodeGen/X86/bitcast-and-setcc-512.ll | 124 +- llvm/test/CodeGen/X86/implicit-null-check.ll | 68 +- llvm/test/CodeGen/X86/srem-lkk.ll | 159 ++ llvm/test/CodeGen/X86/srem-vector-lkk.ll | 556 +++++++ llvm/test/CodeGen/X86/urem-lkk.ll | 108 ++ llvm/test/CodeGen/X86/urem-vector-lkk.ll | 378 +++++ .../HotColdSplit/assumption-cache-invalidation.ll | 12 + llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll | 177 +- ...ft-amount-reassociation-with-truncation-ashr.ll | 178 +++ ...ft-amount-reassociation-with-truncation-lshr.ll | 178 +++ ...ift-amount-reassociation-with-truncation-shl.ll | 34 - llvm/test/Transforms/InstCombine/shift.ll | 230 +-- ...n-bit-test-via-right-shifting-all-other-bits.ll | 168 ++ .../Transforms/SLPVectorizer/X86/bad-reduction.ll | 156 +- llvm/unittests/TableGen/AutomataTest.cpp | 8 +- .../Transforms/Utils/CodeExtractorTest.cpp | 52 + llvm/utils/lit/lit/main.py | 23 +- llvm/utils/lit/lit/run.py | 20 +- llvm/utils/lit/tests/discovery.py | 2 +- llvm/utils/lit/tests/parallelism-groups.py | 2 +- .../deviceRTLs/nvptx/src/data_sharing.cu | 8 +- .../libomptarget/deviceRTLs/nvptx/src/interface.h | 16 +- openmp/libomptarget/deviceRTLs/nvptx/src/loop.cu | 3 +- .../deviceRTLs/nvptx/src/omptarget-nvptx.h | 2 +- .../libomptarget/deviceRTLs/nvptx/src/parallel.cu | 18 +- .../libomptarget/deviceRTLs/nvptx/src/reduction.cu | 12 +- openmp/libomptarget/deviceRTLs/nvptx/src/sync.cu | 4 +- .../deviceRTLs/nvptx/src/target_impl.h | 2 + 81 files changed, 11122 insertions(+), 906 deletions(-) create mode 100644 llvm/test/CodeGen/AArch64/machine-outliner-noreturn.mir create mode 100644 llvm/test/CodeGen/AArch64/srem-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-lkk.ll create mode 100644 llvm/test/CodeGen/AArch64/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/srem-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/urem-lkk.ll create mode 100644 llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/srem-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/urem-lkk.ll create mode 100644 llvm/test/CodeGen/RISCV/urem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/X86/srem-lkk.ll create mode 100644 llvm/test/CodeGen/X86/srem-vector-lkk.ll create mode 100644 llvm/test/CodeGen/X86/urem-lkk.ll create mode 100644 llvm/test/CodeGen/X86/urem-vector-lkk.ll create mode 100644 llvm/test/Transforms/InstCombine/shift-amount-reassociation-wit [...] create mode 100644 llvm/test/Transforms/InstCombine/shift-amount-reassociation-wit [...] create mode 100644 llvm/test/Transforms/InstCombine/sign-bit-test-via-right-shifti [...]