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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_debug in repository toolchain/ci/binutils-gdb.

from da72876cc5 Automatic date update in version.in adds a547eaf18c gdb: re-format with black 21.9b0 adds 37260e0df0 gdb: re-format with black 21.12b0 adds 05f62e0c9a Re: Fix an undefined behaviour in the BFD library's DWARF parser adds 6628ac006d Adjust compare_link_order for unstable qsort adds 4095db4c9c sim: fix mingw builds with replacement gnulib open adds 444cc278b9 bfd: unify texi generation rules adds 7d554943ba sim: mips/or1k: drop redundant arg to bitsize macro adds 23ff54c27d RISC-V: Support svinval extension with frozen version 1.0. adds 3518022233 aarch64: Add support for Armv9.1-A to Armv9.3-A adds b3e4d9326f arm: Add support for Armv8.7-A and Armv8.8-A adds a2b1ea81ba arm: Add support for Armv9.1-A to Armv9.3-A adds 61ab1364c7 When loading separate debug info files, also attempt to loca [...] adds f3be70df1b Fix AVR assembler so that it creates relocs that will work w [...] new 240eab1e59 Automatic date update in version.in

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: bfd/doc/Makefile.am | 121 +++++------------- bfd/doc/Makefile.in | 137 ++++++--------------- bfd/dwarf1.c | 8 +- bfd/elfxx-riscv.c | 3 + bfd/version.h | 2 +- binutils/ChangeLog | 12 ++ binutils/dwarf.c | 116 ++++++++++++++++- binutils/dwarf.h | 1 + binutils/testsuite/binutils-all/debuginfod.exp | 6 +- gas/ChangeLog | 10 ++ gas/NEWS | 6 +- gas/config/tc-aarch64.c | 3 + gas/config/tc-arm.c | 19 ++- gas/config/tc-avr.c | 26 ++++ gas/config/tc-avr.h | 3 + gas/doc/c-aarch64.texi | 3 +- gas/doc/c-arm.texi | 2 + gas/testsuite/gas/aarch64/armv9_1.d | 12 ++ gas/testsuite/gas/aarch64/armv9_1.s | 5 + gas/testsuite/gas/aarch64/armv9_1_invalid.d | 1 + gas/testsuite/gas/aarch64/armv9_1_invalid.l | 2 + gas/testsuite/gas/aarch64/armv9_1_invalid.s | 2 + gas/testsuite/gas/aarch64/armv9_2.d | 13 ++ gas/testsuite/gas/aarch64/armv9_2.s | 6 + gas/testsuite/gas/aarch64/armv9_2_invalid.d | 1 + gas/testsuite/gas/aarch64/armv9_2_invalid.l | 5 + gas/testsuite/gas/aarch64/armv9_2_invalid.s | 6 + gas/testsuite/gas/aarch64/armv9_3.d | 17 +++ gas/testsuite/gas/aarch64/armv9_3.s | 11 ++ gas/testsuite/gas/aarch64/armv9_invalid.d | 1 + gas/testsuite/gas/aarch64/armv9_invalid.l | 3 + gas/testsuite/gas/aarch64/armv9_invalid.s | 3 + gas/testsuite/gas/all/gas.exp | 4 +- gas/testsuite/gas/arm/attr-march-armv8_7-a.d | 17 +++ gas/testsuite/gas/arm/attr-march-armv8_8-a.d | 17 +++ gas/testsuite/gas/arm/attr-march-armv9_1-a.d | 17 +++ gas/testsuite/gas/arm/attr-march-armv9_2-a.d | 17 +++ gas/testsuite/gas/arm/attr-march-armv9_3-a.d | 17 +++ gas/testsuite/gas/arm/bfloat16-armv8.7-a.d | 5 + gas/testsuite/gas/arm/bfloat16-armv8.8-a.d | 5 + gas/testsuite/gas/arm/bfloat16-armv9.1-a.d | 5 + gas/testsuite/gas/arm/bfloat16-armv9.2-a.d | 5 + gas/testsuite/gas/arm/bfloat16-armv9.3-a.d | 5 + gas/testsuite/gas/arm/i8mm-armv8.7-a.d | 5 + gas/testsuite/gas/arm/i8mm-armv8.8-a.d | 5 + gas/testsuite/gas/arm/i8mm-armv9.1-a.d | 5 + gas/testsuite/gas/arm/i8mm-armv9.2-a.d | 5 + gas/testsuite/gas/arm/i8mm-armv9.3-a.d | 5 + gas/testsuite/gas/avr/diffreloc_withrelax.d | 4 +- gas/testsuite/gas/avr/pc-relative-reloc.d | 2 +- gas/testsuite/gas/elf/elf.exp | 2 +- gas/testsuite/gas/riscv/svinval.d | 15 +++ gas/testsuite/gas/riscv/svinval.s | 5 + gdb/gdb-gdb.py.in | 7 +- gdb/python/lib/gdb/__init__.py | 1 - .../gdb.multi/multi-target-info-inferiors.py | 14 ++- gdb/testsuite/gdb.python/py-events.py | 9 +- include/opcode/aarch64.h | 102 +++++++++------ include/opcode/arm.h | 9 ++ include/opcode/riscv-opc.h | 16 +++ include/opcode/riscv.h | 1 + ld/ChangeLog | 7 ++ ld/ldelfgen.c | 11 +- ld/testsuite/ld-avr/avr-prop-7.d | 4 +- ld/testsuite/ld-avr/avr-prop-8.d | 3 +- ld/testsuite/ld-avr/pr13402.d | 6 +- opcodes/riscv-opc.c | 7 ++ sim/common/sim-io.c | 4 +- sim/mips/configure | 3 +- sim/mips/configure.ac | 3 +- sim/or1k/configure | 2 +- sim/or1k/configure.ac | 2 +- 72 files changed, 671 insertions(+), 273 deletions(-) create mode 100644 gas/testsuite/gas/aarch64/armv9_1.d create mode 100644 gas/testsuite/gas/aarch64/armv9_1.s create mode 100644 gas/testsuite/gas/aarch64/armv9_1_invalid.d create mode 100644 gas/testsuite/gas/aarch64/armv9_1_invalid.l create mode 100644 gas/testsuite/gas/aarch64/armv9_1_invalid.s create mode 100644 gas/testsuite/gas/aarch64/armv9_2.d create mode 100644 gas/testsuite/gas/aarch64/armv9_2.s create mode 100644 gas/testsuite/gas/aarch64/armv9_2_invalid.d create mode 100644 gas/testsuite/gas/aarch64/armv9_2_invalid.l create mode 100644 gas/testsuite/gas/aarch64/armv9_2_invalid.s create mode 100644 gas/testsuite/gas/aarch64/armv9_3.d create mode 100644 gas/testsuite/gas/aarch64/armv9_3.s create mode 100644 gas/testsuite/gas/aarch64/armv9_invalid.d create mode 100644 gas/testsuite/gas/aarch64/armv9_invalid.l create mode 100644 gas/testsuite/gas/aarch64/armv9_invalid.s create mode 100644 gas/testsuite/gas/arm/attr-march-armv8_7-a.d create mode 100644 gas/testsuite/gas/arm/attr-march-armv8_8-a.d create mode 100644 gas/testsuite/gas/arm/attr-march-armv9_1-a.d create mode 100644 gas/testsuite/gas/arm/attr-march-armv9_2-a.d create mode 100644 gas/testsuite/gas/arm/attr-march-armv9_3-a.d create mode 100644 gas/testsuite/gas/arm/bfloat16-armv8.7-a.d create mode 100644 gas/testsuite/gas/arm/bfloat16-armv8.8-a.d create mode 100644 gas/testsuite/gas/arm/bfloat16-armv9.1-a.d create mode 100644 gas/testsuite/gas/arm/bfloat16-armv9.2-a.d create mode 100644 gas/testsuite/gas/arm/bfloat16-armv9.3-a.d create mode 100644 gas/testsuite/gas/arm/i8mm-armv8.7-a.d create mode 100644 gas/testsuite/gas/arm/i8mm-armv8.8-a.d create mode 100644 gas/testsuite/gas/arm/i8mm-armv9.1-a.d create mode 100644 gas/testsuite/gas/arm/i8mm-armv9.2-a.d create mode 100644 gas/testsuite/gas/arm/i8mm-armv9.3-a.d create mode 100644 gas/testsuite/gas/riscv/svinval.d create mode 100644 gas/testsuite/gas/riscv/svinval.s