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from e41b243302e amdgcn: Add preprocessor builtins for every processor type new fa144175c9c RISC-V: Add duplicate vector support. new 3b16afeb3f6 RISC-V: Add attributes for VSETVL PASS new c126e144d40 RISC-V: Remove tail && mask policy operand for vmclr, vmset [...]

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Summary of changes: gcc/config/riscv/constraints.md | 5 + gcc/config/riscv/predicates.md | 5 + gcc/config/riscv/riscv-protos.h | 15 + gcc/config/riscv/riscv-selftests.cc | 127 ++++++ gcc/config/riscv/riscv-v.cc | 130 +++++- gcc/config/riscv/riscv-vector-switch.def | 97 ++--- gcc/config/riscv/riscv.cc | 15 +- gcc/config/riscv/riscv.h | 3 + gcc/config/riscv/vector-iterators.md | 9 + gcc/config/riscv/vector.md | 240 ++++++++++- gcc/testsuite/gcc.target/riscv/rvv/base/dup-1.c | 521 ++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/rvv/base/dup-2.c | 75 ++++ 12 files changed, 1173 insertions(+), 69 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/dup-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/dup-2.c