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from 41f9733d3d3 Virtualize TargetInstrInfo::getRegClass() new c18c17dc527 [AMDGPU] gfx1010 core wave32 changes

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Summary of changes: lib/Target/AMDGPU/AMDGPU.td | 6 +- lib/Target/AMDGPU/AMDGPUInstrInfo.td | 8 +- .../AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 6 + lib/Target/AMDGPU/SIInstrInfo.h | 9 + lib/Target/AMDGPU/SIInstrInfo.td | 21 +- lib/Target/AMDGPU/SIInstructions.td | 34 +- lib/Target/AMDGPU/SIRegisterInfo.td | 2 - lib/Target/AMDGPU/VOP2Instructions.td | 4 +- lib/Target/AMDGPU/VOP3Instructions.td | 4 +- lib/Target/AMDGPU/VOPCInstructions.td | 2 +- test/CodeGen/AMDGPU/add3.ll | 9 + test/CodeGen/AMDGPU/add_i1.ll | 12 +- test/CodeGen/AMDGPU/add_shl.ll | 6 + test/CodeGen/AMDGPU/and_or.ll | 6 + .../AMDGPU/hsa-metadata-kernel-code-props-v3.ll | 2 +- test/CodeGen/AMDGPU/huge-private-buffer.ll | 27 +- test/CodeGen/AMDGPU/insert-skip-from-vcc.mir | 20 + .../AMDGPU/large-work-group-promote-alloca.ll | 20 +- test/CodeGen/AMDGPU/mubuf-legalize-operands.mir | 1 + test/CodeGen/AMDGPU/or3.ll | 5 + test/CodeGen/AMDGPU/regbank-reassign.mir | 18 + test/CodeGen/AMDGPU/shl_add.ll | 5 + test/CodeGen/AMDGPU/shl_or.ll | 8 + test/CodeGen/AMDGPU/smrd.ll | 1 + test/CodeGen/AMDGPU/sub_i1.ll | 12 +- test/CodeGen/AMDGPU/wave32.ll | 1140 ++++++++++++++++++++ test/CodeGen/AMDGPU/xor3.ll | 8 + test/CodeGen/AMDGPU/xor_add.ll | 5 + test/MC/AMDGPU/gfx10-constant-bus.s | 10 + test/MC/AMDGPU/wave32.s | 412 +++++++ test/MC/Disassembler/AMDGPU/gfx10-sgpr-max.txt | 6 + test/MC/Disassembler/AMDGPU/wave32.txt | 164 +++ 32 files changed, 1933 insertions(+), 60 deletions(-) create mode 100644 test/CodeGen/AMDGPU/wave32.ll create mode 100644 test/MC/AMDGPU/wave32.s create mode 100644 test/MC/Disassembler/AMDGPU/wave32.txt