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from 5b945243c77 RISC-V: Support VLS unary floating-point patterns new eceb45bb2e0 ada: Private extensions with the keyword "synchronized" are [...] new 005888670a1 ada: TSS finalize address subprogram generation for constrained... new e1817426e85 RISC-V: Fix RVV can change mode class bug

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Summary of changes: gcc/ada/exp_ch3.adb | 4 ++ gcc/ada/exp_ch7.adb | 28 +++++++++++- gcc/ada/sem_ch3.adb | 12 +++-- gcc/config/riscv/riscv.cc | 20 +++++++-- gcc/testsuite/gnat.dg/sync_tag_discriminals.adb | 51 +++++++++++++++++++++ gcc/testsuite/gnat.dg/sync_tag_finalize.adb | 60 +++++++++++++++++++++++++ gcc/testsuite/gnat.dg/sync_tag_limited.adb | 50 +++++++++++++++++++++ 7 files changed, 217 insertions(+), 8 deletions(-) create mode 100644 gcc/testsuite/gnat.dg/sync_tag_discriminals.adb create mode 100644 gcc/testsuite/gnat.dg/sync_tag_finalize.adb create mode 100644 gcc/testsuite/gnat.dg/sync_tag_limited.adb