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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allyesconfig in repository toolchain/ci/llvm-project.

from c822edc11bf Revert "[Concepts] Instantiate invented template type param [...] adds 1ac1c4b4850 [Concepts] Instantiate invented template type parameter typ [...] adds 4e9209ab592 [RISCV] Scheduler description for the Rocket core adds 94c79ce5740 Revert "[AMDGPU] Invert the handling of skip insertion." adds b905b85eedf [BPF] fix a bug in BPFMISimplifyPatchable pass with -O0 adds 5cca13d43b7 AMDGPU/R600: Emit rodata in text segment adds fa51929f03f R600: Fix failing testcase adds 7ad47b46b55 [clang-tidy] Fixed crash 44745 in readability-else-after-return adds 4ea9a4aba4a Declare __builtin_strlen in StringRef.h as constexpr adds d2a710ea784 Actually, don't try to use __builtin_strlen in StringRef.h [...] adds 165a6367631 [libcxxabi] Fix layout of __cxa_exception for win64

No new revisions were added by this update.

Summary of changes: .../readability/ElseAfterReturnCheck.cpp | 4 + .../checkers/readability-else-after-return.cpp | 13 + clang/lib/Sema/SemaTemplateInstantiate.cpp | 129 +++++++++ clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 46 +-- .../instantiate-abbreviated-template.cpp | 29 ++ libcxxabi/src/cxa_exception.h | 10 +- llvm/include/llvm/ADT/StringRef.h | 3 +- llvm/lib/Target/AMDGPU/AMDGPU.h | 3 - llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 2 - llvm/lib/Target/AMDGPU/CMakeLists.txt | 1 - llvm/lib/Target/AMDGPU/SIInsertSkips.cpp | 5 +- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 10 +- .../Target/AMDGPU/SIRemoveShortExecBranches.cpp | 158 ----------- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 2 +- llvm/lib/Target/BPF/BPFMISimplifyPatchable.cpp | 7 +- llvm/lib/Target/RISCV/RISCV.td | 9 + llvm/lib/Target/RISCV/RISCVInstrFormats.td | 3 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 109 +++---- llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 64 +++-- llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 156 +++++++---- llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 69 +++-- llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 72 +++-- llvm/lib/Target/RISCV/RISCVInstrInfoM.td | 39 ++- llvm/lib/Target/RISCV/RISCVSchedRocket32.td | 213 ++++++++++++++ llvm/lib/Target/RISCV/RISCVSchedRocket64.td | 214 ++++++++++++++ llvm/lib/Target/RISCV/RISCVSchedule.td | 138 +++++++++ .../AMDGPU/GlobalISel/divergent-control-flow.ll | 11 +- .../AMDGPU/atomic_optimizations_local_pointer.ll | 312 ++++++++++++++------- .../AMDGPU/atomic_optimizations_pixelshader.ll | 2 +- llvm/test/CodeGen/AMDGPU/branch-condition-and.ll | 5 +- llvm/test/CodeGen/AMDGPU/branch-relaxation.ll | 9 +- llvm/test/CodeGen/AMDGPU/call-skip.ll | 9 +- llvm/test/CodeGen/AMDGPU/collapse-endcf.ll | 49 ++-- .../CodeGen/AMDGPU/control-flow-fastregalloc.ll | 15 +- llvm/test/CodeGen/AMDGPU/convergent-inlineasm.ll | 8 +- llvm/test/CodeGen/AMDGPU/cse-phi-incoming-val.ll | 2 +- .../AMDGPU/divergent-branch-uniform-condition.ll | 11 +- llvm/test/CodeGen/AMDGPU/else.ll | 3 +- llvm/test/CodeGen/AMDGPU/global-constant.ll | 6 + llvm/test/CodeGen/AMDGPU/hoist-cond.ll | 2 +- .../test/CodeGen/AMDGPU/insert-skips-flat-vmem.mir | 2 +- llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir | 2 +- .../CodeGen/AMDGPU/insert-skips-ignored-insts.mir | 2 +- .../CodeGen/AMDGPU/insert-skips-kill-uncond.mir | 2 +- .../test/CodeGen/AMDGPU/mubuf-legalize-operands.ll | 6 +- llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll | 3 +- .../CodeGen/AMDGPU/r600-constant-array-fixup.ll | 6 +- llvm/test/CodeGen/AMDGPU/ret_jump.ll | 23 +- llvm/test/CodeGen/AMDGPU/si-annotate-cf-noloop.ll | 2 + .../si-lower-control-flow-unreachable-block.ll | 10 +- llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir | 2 +- .../CodeGen/AMDGPU/skip-branch-taildup-ret.mir | 2 +- llvm/test/CodeGen/AMDGPU/skip-branch-trap.ll | 7 +- llvm/test/CodeGen/AMDGPU/skip-if-dead.ll | 13 +- llvm/test/CodeGen/AMDGPU/smrd_vmem_war.ll | 2 +- .../stack-pointer-offset-relative-frameindex.ll | 3 +- .../CodeGen/AMDGPU/subreg-coalescer-undef-use.ll | 5 +- llvm/test/CodeGen/AMDGPU/uniform-cfg.ll | 2 +- .../AMDGPU/uniform-loop-inside-nonuniform.ll | 2 + llvm/test/CodeGen/AMDGPU/valu-i1.ll | 42 +-- llvm/test/CodeGen/AMDGPU/wave32.ll | 16 +- llvm/test/CodeGen/AMDGPU/wqm.ll | 5 +- llvm/test/CodeGen/BPF/optnone-1.ll | 52 ++++ 63 files changed, 1554 insertions(+), 609 deletions(-) create mode 100644 clang/test/SemaTemplate/instantiate-abbreviated-template.cpp delete mode 100644 llvm/lib/Target/AMDGPU/SIRemoveShortExecBranches.cpp create mode 100644 llvm/lib/Target/RISCV/RISCVSchedRocket32.td create mode 100644 llvm/lib/Target/RISCV/RISCVSchedRocket64.td create mode 100644 llvm/lib/Target/RISCV/RISCVSchedule.td create mode 100644 llvm/test/CodeGen/BPF/optnone-1.ll