This is an automated email from the git hooks/post-receive script.

tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/llvm-project.

from f863df9a0510 [RISCV][NFC] Add common check prefix to reduce duplicate c [...] adds ddc90da47848 [mlir] Printing oilist element adds e4e281eae933 Revert "[bootstrap] Allow passing options to sub-builds fo [...] adds 23423c0ea8d4 [TableGen] Fix a misuse of getValueAsBitsInit adds ecd7a0132a34 [RISCV] Add basic cost model for vector casting adds 902f4708fe1d [NFC] [Coroutines] Remove unnecessary check and constraint [...] adds b950a0d44d8a [libc][Obvious] Remove an unnecessary dep and use inline_memcpy. adds 1d259f9f0202 [mlir][affine] Add affine.min / affine.max canonicalization. adds 6902734eb38b [X86] Simplify attributes of the generated memory folding [...] adds abe997bb2dd6 [CMake][Fuchsia] Switch to lld on Apple platforms adds 0ff19b190569 [RISCV][NFC] Add some check prefixes to remove redundant c [...] adds abb5a985e96a [RISCV] Support mask policy for RVV IR intrinsics. adds 2ddd57ae1ec4 [clang][dataflow] Model the behavior of optional and std swap adds a9656bd1bc37 [CodeGen][OpenMP] Make EmitLoadOfPointer() type consistent adds 767ec883e375 [CodeGen] Avoid deprecated Address ctor in EmitLoadOfPointer() adds 8b295d1ca2cc Cleanup includes: Linker adds b8f0e12847f5 [CodeGen] Remove some uses of deprecated Address constructor adds f1985a3f855d Cleanup includes: Transforms/IPO adds 3e7a8aab759a [clang-tidy] Don't try to build CTTestTidyModule for Windo [...] adds f42b1954a0e8 [CodeGen][RISCV] Avoid deprecated address constructor adds 86cc731f4c50 [WebAssembly] Always emit functype directives for defined [...] adds 1579090141c5 Reland "[pseudo] Split greatergreater token." adds 9ab18cc53537 [RISCV] Add policy operand for masked vid and viota IR int [...] adds a53b689f0ce6 Fix missing include under -DEXPENSIVE_CHECK adds 021b42367ab5 [X86] Rename MMX_MOVD64from64rm to MMX_MOVD64from64mr b/c [...] adds 51ba13b1aea3 [CGStmtOpenMP] Remove uses of deprecated Address constructor adds 7de383c89213 [VP] Fix VPintrinsic::getStaticVectorLength for vp.merge|select adds 0a488cba2c1b [AMDGPU] use scalar shift for SALU users in frame index el [...] adds 5a65f0b4d9fa [X86][SandyBridge] Remove superfluous mmx store from vecto [...] adds ebec5e5c8f12 [flang][OpenMP] Lowering critical construct adds 73777b4c35a3 [Debugify] Optimize debugify original mode adds 7636c9a9297d [AMDGPU] use scalar shift for SALU users in frame index el [...] adds c56dd20f69bf [AArch64] Add extra insert subvector cost model tests. NFC adds c4f31d1da582 [InstCombine] add tests for shift-of-bswap; NFC adds 9e9bda2e8f5b [InstCombine] try to narrow shifted bswap-of-zext

No new revisions were added by this update.

Summary of changes: .../pseudo/include/clang-pseudo/Token.h | 3 +- clang-tools-extra/pseudo/lib/Lex.cpp | 16 +- clang-tools-extra/pseudo/lib/cxx.bnf | 14 +- clang-tools-extra/pseudo/unittests/TokenTest.cpp | 20 + clang-tools-extra/test/CMakeLists.txt | 12 +- clang/cmake/caches/Fuchsia-stage2.cmake | 12 +- clang/cmake/caches/Fuchsia.cmake | 12 +- clang/include/clang/Basic/riscv_vector.td | 50 +- .../Models/UncheckedOptionalAccessModel.cpp | 57 + clang/lib/CodeGen/BackendUtil.cpp | 4 +- clang/lib/CodeGen/CGCUDANV.cpp | 6 +- clang/lib/CodeGen/CGExpr.cpp | 8 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 15 +- clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp | 3 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 96 +- clang/lib/CodeGen/CodeGenFunction.h | 3 + clang/lib/CodeGen/CodeGenModule.cpp | 5 +- .../OpenMP/target_data_use_device_addr_codegen.cpp | 4 +- .../UncheckedOptionalAccessModelTest.cpp | 94 +- flang/lib/Lower/OpenMP.cpp | 45 +- flang/lib/Semantics/resolve-directives.cpp | 39 +- flang/test/Lower/OpenMP/critical.f90 | 41 + libc/loader/linux/x86_64/CMakeLists.txt | 2 +- libc/loader/linux/x86_64/start.cpp | 7 +- libc/src/stdlib/CMakeLists.txt | 1 - libcxx/utils/ci/run-buildbot | 2 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 71 +- llvm/include/llvm/IR/VPIntrinsics.def | 5 + llvm/include/llvm/Transforms/IPO/AlwaysInliner.h | 4 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 7 +- .../llvm/Transforms/IPO/ForceFunctionAttrs.h | 3 +- llvm/include/llvm/Transforms/IPO/FunctionAttrs.h | 4 +- llvm/include/llvm/Transforms/IPO/GlobalDCE.h | 9 +- llvm/include/llvm/Transforms/IPO/IROutliner.h | 2 - .../llvm/Transforms/IPO/InferFunctionAttrs.h | 4 +- llvm/include/llvm/Transforms/IPO/Inliner.h | 1 - llvm/include/llvm/Transforms/IPO/Internalize.h | 1 - llvm/include/llvm/Transforms/IPO/ModuleInliner.h | 3 - .../llvm/Transforms/IPO/PassManagerBuilder.h | 1 - .../llvm/Transforms/IPO/SampleContextTracker.h | 8 +- .../llvm/Transforms/IPO/SampleProfileProbe.h | 12 +- .../llvm/Transforms/IPO/StripDeadPrototypes.h | 3 +- .../llvm/Transforms/IPO/ThinLTOBitcodeWriter.h | 3 +- .../llvm/Transforms/IPO/WholeProgramDevirt.h | 5 +- llvm/include/llvm/Transforms/Utils/Debugify.h | 38 +- llvm/lib/IR/IntrinsicInst.cpp | 7 +- llvm/lib/Linker/IRMover.cpp | 8 +- llvm/lib/Linker/LinkModules.cpp | 1 - llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 120 +- llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h | 13 +- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 45 +- llvm/lib/Target/RISCV/RISCVInstrFormats.td | 5 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 27 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 48 + llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 5 + .../Target/WebAssembly/WebAssemblyAsmPrinter.cpp | 101 +- .../lib/Target/WebAssembly/WebAssemblyAsmPrinter.h | 2 +- llvm/lib/Target/X86/X86InstrFoldTables.cpp | 2 +- llvm/lib/Target/X86/X86InstrMMX.td | 2 +- llvm/lib/Target/X86/X86SchedSandyBridge.td | 3 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 5 +- llvm/lib/Transforms/IPO/AlwaysInliner.cpp | 6 - llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 7 +- llvm/lib/Transforms/IPO/Attributor.cpp | 13 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 2 +- llvm/lib/Transforms/IPO/CrossDSOCFI.cpp | 5 - .../lib/Transforms/IPO/DeadArgumentElimination.cpp | 2 - llvm/lib/Transforms/IPO/ExtractGV.cpp | 1 - llvm/lib/Transforms/IPO/ForceFunctionAttrs.cpp | 1 + llvm/lib/Transforms/IPO/FunctionAttrs.cpp | 2 +- llvm/lib/Transforms/IPO/FunctionImport.cpp | 3 - llvm/lib/Transforms/IPO/FunctionSpecialization.cpp | 3 - llvm/lib/Transforms/IPO/GlobalDCE.cpp | 1 - llvm/lib/Transforms/IPO/GlobalOpt.cpp | 2 - llvm/lib/Transforms/IPO/HotColdSplitting.cpp | 16 +- llvm/lib/Transforms/IPO/IROutliner.cpp | 1 - llvm/lib/Transforms/IPO/InferFunctionAttrs.cpp | 3 - llvm/lib/Transforms/IPO/InlineSimple.cpp | 7 - llvm/lib/Transforms/IPO/Inliner.cpp | 6 - llvm/lib/Transforms/IPO/Internalize.cpp | 3 - llvm/lib/Transforms/IPO/LoopExtractor.cpp | 5 - llvm/lib/Transforms/IPO/MergeFunctions.cpp | 5 +- llvm/lib/Transforms/IPO/ModuleInliner.cpp | 14 +- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 1 - llvm/lib/Transforms/IPO/PartialInlining.cpp | 3 - llvm/lib/Transforms/IPO/PassManagerBuilder.cpp | 9 - llvm/lib/Transforms/IPO/PruneEH.cpp | 3 - llvm/lib/Transforms/IPO/SampleProfile.cpp | 13 +- llvm/lib/Transforms/IPO/SampleProfileProbe.cpp | 8 +- .../Transforms/IPO/SyntheticCountsPropagation.cpp | 5 - llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp | 1 - .../Transforms/InstCombine/InstCombineShifts.cpp | 15 + llvm/lib/Transforms/ObjCARC/ObjCARC.h | 1 - llvm/lib/Transforms/Utils/Debugify.cpp | 119 +- llvm/runtimes/CMakeLists.txt | 11 - .../Analysis/CostModel/AArch64/shuffle-other.ll | 82 ++ llvm/test/Analysis/CostModel/RISCV/cast.ll | 306 +++++ llvm/test/CodeGen/AMDGPU/frame-index.mir | 186 +++ llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll | 438 +++---- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 636 +++------- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 627 +++------- llvm/test/CodeGen/RISCV/rvv/masked-tama.ll | 1313 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll | 1240 ++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll | 1240 ++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll | 1240 ++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll | 67 - llvm/test/CodeGen/RISCV/rvv/vid.ll | 84 +- llvm/test/CodeGen/RISCV/rvv/viota.ll | 88 +- llvm/test/CodeGen/WebAssembly/byval.ll | 12 +- llvm/test/CodeGen/WebAssembly/cfg-stackify-eh.ll | 38 +- .../test/CodeGen/WebAssembly/function-pointer64.ll | 1 + llvm/test/CodeGen/WebAssembly/functype-emission.ll | 6 +- .../WebAssembly/inlineasm-output-template.ll | 9 +- llvm/test/CodeGen/WebAssembly/multi-return.ll | 18 +- llvm/test/CodeGen/WebAssembly/stack-protector.ll | 4 +- llvm/test/MC/WebAssembly/stack-ptr-mclower.ll | 3 + llvm/test/Transforms/InstCombine/lshr.ll | 95 ++ llvm/tools/llvm-profgen/ProfileGenerator.h | 1 + llvm/tools/opt/opt.cpp | 11 +- llvm/unittests/Transforms/Utils/DebugifyTest.cpp | 24 +- llvm/utils/TableGen/FixedLenDecoderEmitter.cpp | 11 +- llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 15 +- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 4 +- mlir/lib/Dialect/Affine/IR/AffineOps.cpp | 81 +- mlir/test/Dialect/Affine/canonicalize.mlir | 38 +- mlir/test/Dialect/Linalg/codegen-strategy.mlir | 2 +- mlir/test/Dialect/Linalg/fusion-pattern.mlir | 18 +- mlir/test/Dialect/Linalg/fusion-sequence.mlir | 21 +- .../test/Dialect/Linalg/fusion-tensor-pattern.mlir | 8 +- mlir/test/Dialect/Linalg/fusion.mlir | 20 +- mlir/test/Dialect/Linalg/hoist-padding.mlir | 8 +- mlir/test/Dialect/Linalg/pad.mlir | 10 +- .../test/Dialect/Linalg/tile-and-fuse-tensors.mlir | 22 +- mlir/test/Dialect/Linalg/tile-conv.mlir | 8 +- mlir/test/Dialect/Linalg/tile-tensors.mlir | 2 +- mlir/test/Dialect/Linalg/tile.mlir | 12 +- mlir/test/Dialect/SCF/for-loop-peeling.mlir | 4 +- mlir/test/IR/traits.mlir | 6 +- mlir/test/lib/Dialect/Test/TestOps.td | 9 +- mlir/tools/mlir-tblgen/OpFormatGen.cpp | 186 ++- 140 files changed, 7584 insertions(+), 2116 deletions(-) create mode 100644 flang/test/Lower/OpenMP/critical.f90 create mode 100644 llvm/test/Analysis/CostModel/RISCV/cast.ll create mode 100644 llvm/test/CodeGen/AMDGPU/frame-index.mir create mode 100644 llvm/test/CodeGen/RISCV/rvv/masked-tama.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll delete mode 100644 llvm/test/CodeGen/RISCV/rvv/vadd-policy.ll