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from 7ea501d3ea6 MATCH: Make zero_one_valued_p non-recursive fully new 28f16f6d9b4 RISC-V: Bugfix for scalar move with merged operand new aad0c3e197f RISC-V: Support VLS mode for vec_set

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Summary of changes: gcc/config/riscv/autovec.md | 8 ++--- gcc/config/riscv/riscv-protos.h | 4 +++ .../gcc.target/riscv/rvv/autovec/vls/def.h | 18 +++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-1.c | 35 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-10.c | 31 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-11.c | 29 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-12.c | 21 +++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-13.c | 20 +++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-14.c | 19 ++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-15.c | 18 +++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-16.c | 21 +++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-17.c | 20 +++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-18.c | 19 ++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-19.c | 18 +++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-2.c | 33 ++++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-20.c | 20 +++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-21.c | 19 ++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-22.c | 18 +++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-3.c | 31 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-4.c | 29 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-5.c | 35 ++++++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-6.c | 33 ++++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-7.c | 31 +++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-8.c | 29 ++++++++++++++++++ .../gcc.target/riscv/rvv/autovec/vls/vec-set-9.c | 33 ++++++++++++++++++++ .../riscv/rvv/base/scalar-move-merged-run-1.c | 29 ++++++++++++++++++ 26 files changed, 617 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-10.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-11.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-12.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-13.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-14.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-15.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-16.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-17.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-18.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-19.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-20.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-21.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-22.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-5.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-7.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-8.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/vec-set-9.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar-move-merged-run-1.c