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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allmodconfig in repository toolchain/ci/llvm-project.

from 30365472489 Precommit analysis/etc tests for inselt poison placeholder adds 9939cf5a564 [ExecutionEngine, Linker] Use erase_if (NFC) adds 200b15af45a [Analysis] Remove spliceFunction (NFC) adds b8cb1802a8a [obj2yaml] - Dump the content of a broken GNU hash table properly. adds 90177912a4d Revert "[InstCombine] Fold gep inbounds of null to null" adds 61177943c9c [AMDGPU] Use MUBUF instructions for global address space access adds e0751234ef0 [CodeGen] Add "noreturn" attirbute to _Unwind_Resume adds ef2f843347b Revert "[InstCombine] Check inbounds in load/store of gep n [...] adds ce4413e4894 Moved dwarf_eh_resume.ll from Generic to X86 folder adds fb468953082 [Support] Explicitly state that KnownBits::getMinValue/getM [...] adds 6895581fd2c [Support] Add KnownBits::getSignedMinValue/getSignedMaxValu [...] adds 89abe1cf83a [InstCombine] foldICmpUsingKnownBits - use KnownBits signed [...] adds df812115e3c [CodeGen, Transforms] Use llvm::any_of (NFC) adds e457896a6ef [CodeGen] Remove unused function hasInlineAsmMemConstraint (NFC) adds ff3749fc793 [NFC] SimplifyCFGOpt::simplifyUnreachable(): pacify unused [...] adds b3021a72a6d [IR][InstCombine] Add m_ImmConstant(), that matches on non- [...] adds da4c7e15df3 [NFC][InstCombine] Autogenerate check lines in vec_shuffle.ll test adds 1fda23367d4 [NFC][InstCombine] Add test for `a & ~(a ^ b)` pattern adds 5b78303433c [InstCombine] Fold `a & ~(a ^ b)` to `x & y` adds 8001dcbd50c [NFC][InstCombine] Add test coverage for `(x ^ C) ^ y` pattern adds d9ebaeeb468 [InstCombine] Hoist xor-by-constant from xor-by-value adds 6e074a8324d [NFC][LoopIdiom] Improve test coverage for 'left-shift-unti [...] adds 25aebe2ccfb [LoopIdiom] 'left-shift-until-bittest': keep no-wrap flags [...] adds afd03cd3358 [RISCV] Define vector single-width reduction intrinsic. adds 912740a864f [RISCV] Add intrinsics for vrgather instruction adds 351c216f36a [RISCV] Define vector mask-register logical intrinsics. new d6ff5cf995d [Target] Use llvm::any_of (NFC)

The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference.

Summary of changes: llvm/docs/AMDGPUUsage.rst | 5 + llvm/include/llvm/Analysis/CallGraph.h | 7 - llvm/include/llvm/CodeGen/Analysis.h | 5 - llvm/include/llvm/IR/IntrinsicsRISCV.td | 52 + llvm/include/llvm/IR/PatternMatch.h | 43 +- llvm/include/llvm/Support/KnownBits.h | 24 +- llvm/lib/Analysis/CallGraph.cpp | 14 - llvm/lib/CodeGen/Analysis.cpp | 21 - llvm/lib/CodeGen/DwarfEHPrepare.cpp | 2 + llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp | 9 +- llvm/lib/CodeGen/MultiHazardRecognizer.cpp | 7 +- llvm/lib/ExecutionEngine/SectionMemoryManager.cpp | 8 +- llvm/lib/Linker/IRMover.cpp | 3 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 6 +- .../Target/AMDGPU/AMDGPURewriteOutArguments.cpp | 7 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 34 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 23 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 5 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 272 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 4 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 15 + .../Transforms/InstCombine/InstCombineCalls.cpp | 4 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 51 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 24 +- .../Transforms/InstCombine/InstCombineNegator.cpp | 3 +- .../InstCombine/InstructionCombining.cpp | 14 +- .../Instrumentation/ControlHeightReduction.cpp | 7 +- llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 50 +- llvm/lib/Transforms/Utils/CodeMoverUtils.cpp | 45 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 1 + llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +- .../irtranslator-invoke-probabilities.ll | 2 +- llvm/test/CodeGen/AMDGPU/lower-kernargs.ll | 5 +- llvm/test/CodeGen/AMDGPU/memory-legalizer-fence.ll | 2 +- .../AMDGPU/memory-legalizer-global-agent.ll | 838 ++-- .../AMDGPU/memory-legalizer-global-nontemporal.ll | 18 +- .../AMDGPU/memory-legalizer-global-singlethread.ll | 838 ++-- .../AMDGPU/memory-legalizer-global-system.ll | 838 ++-- .../AMDGPU/memory-legalizer-global-wavefront.ll | 838 ++-- .../AMDGPU/memory-legalizer-global-workgroup.ll | 838 ++-- .../CodeGen/AMDGPU/memory-legalizer-local-agent.ll | 402 +- .../AMDGPU/memory-legalizer-local-nontemporal.ll | 38 +- .../AMDGPU/memory-legalizer-local-singlethread.ll | 402 +- .../AMDGPU/memory-legalizer-local-system.ll | 402 +- .../AMDGPU/memory-legalizer-local-wavefront.ll | 402 +- .../AMDGPU/memory-legalizer-local-workgroup.ll | 402 +- .../AMDGPU/memory-legalizer-private-nontemporal.ll | 78 +- llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 3624 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 4630 ++++++++++++++++++++ llvm/test/CodeGen/X86/dwarf_eh_resume.ll | 23 + llvm/test/Transforms/InstCombine/and-xor-or.ll | 43 + llvm/test/Transforms/InstCombine/getelementptr.ll | 6 +- .../hoist-xor-by-constant-from-xor-by-value.ll | 75 + .../invert-variable-mask-in-masked-merge-scalar.ll | 5 +- .../invert-variable-mask-in-masked-merge-vector.ll | 5 +- llvm/test/Transforms/InstCombine/load.ll | 5 +- llvm/test/Transforms/InstCombine/or-xor.ll | 68 +- llvm/test/Transforms/InstCombine/store.ll | 5 +- .../unfold-masked-merge-with-const-mask-scalar.ll | 6 +- .../unfold-masked-merge-with-const-mask-vector.ll | 6 +- .../InstCombine/vec_shuffle-inseltpoison.ll | 4 +- llvm/test/Transforms/InstCombine/vec_shuffle.ll | 12 +- llvm/test/Transforms/InstCombine/xor2.ll | 44 +- .../LoopIdiom/X86/left-shift-until-bittest.ll | 1875 ++++---- llvm/test/tools/obj2yaml/ELF/gnu-hash-section.yaml | 21 +- llvm/tools/llvm-lipo/llvm-lipo.cpp | 5 +- llvm/tools/obj2yaml/elf2yaml.cpp | 4 +- llvm/unittests/Support/KnownBitsTest.cpp | 14 + 109 files changed, 32501 insertions(+), 4287 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll create mode 100644 llvm/test/CodeGen/X86/dwarf_eh_resume.ll create mode 100644 llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor [...]